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https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/665217/lmx2594-open-drain-muxout
我在一个板上有3个lmx2594，我尝试通过一个SPI总线与所有3个主板通信。 MUXout引脚似乎不是漏极开路，因此当所有3个合成器共享该行时，它会阻止我读回寄存器。 数据表指示此引脚是推拉式。 是否有办法将此引脚配置为漏极开路？
