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https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1064580/cdcdb400-clock-zero-delay-buffers
你(们)好
请建议使用一个输入和两个输出、或者一个输入和四个输出时钟缓冲器以下是此时钟缓冲器的要求
100MHz 输入和100MHz 输出
输出阻抗为85欧姆
您好、Gareth、
CDCDB400是一 款1 HCSL 输入、4 HCSL 输出缓冲器、默认具有集成的85 Ω 输出阻抗。 它可以接受100MHz 输入/输出。
此致、
Jennifer
