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https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/942543/lmk00105-lmk00105sq-nop-power-down-sequence-with-a-spike
当我们直接切断系统的电源， 如图所示的波形时、CLK OUT 中出现尖峰、请帮助检查设计原理图并期待您的回复。
e2e.ti.com/.../CLK_5F00_SCH.pdf
也许我们可以改进电源序列。 您能否在同一图中测量电源波形？ 让我们看看 VDD 和 VDDO。
如果器件断电、整个系统是否断电？ 想了解这种行为是个问题的原因。
此致、 通道
