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https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/796888/lmk04828-if-possible-to-generate-a-sysref-whose-duty-cyle-is-not-50
您好！
我有疑问：
如果在不使用 SYNC 引脚的情况下能够生成如下图所示的信号、其占空比不是50%？
