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https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/724737/cdc3rl02-external-bias-to-clk_out1-2
缓冲器输出 CLK_OUT1/2能否从外部电路获取偏置电压？ 或者需要添加串联交流耦合电容以防止任何外部电路偏置 CLK_OUT 1/2？
