我想使用DDS的输出频率作为PLL的参考信号激励PLL，把PLL当成倍频器使用产生5.8GHz-6GHz的chirp信号，DDS的输出频率在180MHz-190MHz,分频器N为32，DDS的频率步进精度很细（Hz级别），想知道总的调频周期以及锁存一个频率点的时间，数据手册和仿真软件并没有调频锁存时间的计算，请问我该如何进行研究呢，VCO校准又需不需要时间呢，请问时间是多少，我需要知道这些时间
I want to use the output frequency of DDS as the reference signal of PLL to stimulate PLL, and use PLL as a frequency multiplier to generate chirp signals of 5.8GHz-6GHz. The output frequency of DDS is 180MHz-190MHz, the frequency divider N is 32, and the frequency stepping accuracy of DDS is very fine (Hz level). If I want to know the total frequency modulation cycle and the time to latch a frequency point, the data manual and simulation software do not have the calculation of frequency modulation latch time, may I ask how I should conduct research? Does VCO calibration need time
一样是这个问题，我现在使用DDS的48MHz-50MHz输出到LMX2572，我只配置了一次寄存器（R【0】的FCAL_EN = 1），将LMX2572的PLL_N设置为120，理论上输出应该是5.76GHz-6GHz,但是我使用DDS点频模式输出一个一个频点，例如DDS输出48MHz，LMX2572输出5.76Ghz正确,但是当我的DDS输出48.5MHz时，LMX2572输出并不是正确的值，一般偏小，如何我复位单片机后，LMX2572的输出就正常了，意思就是跳频步进大一点输出就不正常（例如上面说的，DDS从48MHz跳到48.4MHz时PLL输出是正常的，但是继续从48.4MHz跳到48.5MHz后PLL输出也不正常），是因为VCO要校准吗，我的LMX2572输出频段都在VCO6的频段，并且我把开启寄存器的开启校准位（R[0]的FCAL_EN = 1）放到我的程序主循环里，所有频点输出都正常了，但是在输出频点的周围有杂散的脉冲（很近并且幅值和频点相近），所以我想实现DDS激励LMX2572输出调频波（chirp）可选吗，回到校准的问题，为什么VCO还需要控制校准，我使用的都是同一个VCO（vco6）,本人不理解，我看其他的PLL或者VCO没有提到校准，并且看到其他DDS激励PLL的方案也没有说到VCO校准，是LMX2572系列特有的吗，或许我对PLL原理还不熟悉，请问大家，谢谢（经过测试，LMX2572单独输出频率是正常的）
It is the same problem. Now I use 48MHz-50MHz of DDS to output to LMX2572. I configured the register (FCAL_EN = 1 of R [0]) only once, and set the PLL_N of LMX2572 to 120. Theoretically, the output should be 5.76ghz-6ghz, but I use DDS dot frequency mode to output one frequency point after another, for example, DDS output 48MHz, LMX2572 output 5.76GHz is correct, but when my DDS output 48.5MHz, the output of LMX2572 is not the correct value, which is generally too small. After I reset the MCU, the output of LMX2572 is normal, which means that the output is abnormal when the frequency hopping step is larger (for example, as mentioned above, the PLL output is normal when the DDS jumps from 48MHz to 48.4MHz, but the PLL output is also abnormal when the DDS continues to jump from 48.4MHz to 48.8.5 MHz). Is it because VCO needs to be calibrated? My LMX2572 output frequency band is all in the VCO6 frequency band, and I put the on calibration bit of the on register (FCAL_EN = 1 of R[0]) into the main loop of my program. All frequency outputs are normal, but there are stray pulses around the output frequency (very close and the amplitude is similar to the frequency). Therefore, I want to realize the optional frequency modulation wave (chirp) output of DDS excitation LMX2572. Back to the question of calibration, why does VCO need to control calibration? I use the same VCO (vco6), which I don't understand. I see that calibration is not mentioned in other PLL or VCO. Besides, other DDS incentive PLL schemes do not mention VCO calibration, is it unique to LMX2572 series? Perhaps I am not familiar with the principle of PLL, please tell me, thank you(After testing, LMX2572 individual output frequency is normal)
