您好
我们研究系统中的实时问题。
主要思路是测试任务对中断的响应时间(通过信标端口)并测量任务唤醒时间中的抖动。
设置：
125us 的中断、将信标布置到任务、随后发布另一个信标。
在2个位置/任务中对 CPU 时间戳计数器进行采样。 进行一次发送。
我们总共有2个跃点、即从 ISR 发布的信标、任务唤醒、采样时间、并且将信标布置到下一个较低优先级的任务、再进行采样。
我们将测量表示任务唤醒中抖动的时间戳差异。
随着每个新的"跳"抖动的增加、系统节拍(1毫秒)和抖动之间存在明显的相关性。
看起来 Tick 通知花费太多的时间或者 CPU 只是很慢。
我已检查 DDR 已缓存且两个 I/D 缓存均已打开。
是否可以检查 SOC 配置、是否可能某些 PLL/频率设置不正确？
你好，穆库尔
我实现了用于测量任务唤醒抖动的循环测试、请遵循 xSemaphoreTag/xSemaphoreGive 对。
1、任务1由中断唤醒
2.任务2由任务1唤醒
3.任务3由任务2唤醒
优先级1< 2< 3
我 在每个任务中测量唤醒时间的抖动。
如果我有一个任务抖动是几微秒、如果3个抖动低至28微秒、那么将任务一无作为是不合逻辑的。
请遵循以下变量：
此致
罗斯法尔
您好
您可以监控这些计数器。
您可以停止调试器并每次置0以重新开始测量。 您应该会看到接近125的值(除以800.0后)
[0]是 ISR 周期时间
[1]、[2]、[3]任务周期时间。
尝试"按原样"、然后在主代码中注释掉。
gHop4Task = xTaskCreateStatic( empty_hop4，/*指向实现该任务的函数的指针。 */
gHop5Task = xTaskCreateStatic( empty_hop5，/*指向实现该任务的函数的指针。 */
您好
您能否提供有关如何将(附加属性到)自动生成的 ISR 包装器移动到特定存储器部分的说明：
谢谢 
罗斯法尔
你好，Rasty，
我尝试过两种方法。 一种方法是_attribute 方法、另一种方法是在链接器命令文件中将函数保留在.text 中。
在我的测试中、我发现第二种方法很简单、因为我们不需要更新生成的文件。
请尝试以下方法。 只需更新链接器 cmd 文件以将函数保留在 TCM 存储器中即可。
也在同一链接器命令文件中定义了 TCMA 存储器大小。
/* This is the stack that is used by code running within main()
* In case of NORTOS,
* - This means all the code outside of ISR uses this stack
* In case of FreeRTOS
* - This means all the code until vTaskStartScheduler() is called in main()
* uses this stack.
* - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
*/
--stack_size=16384
/* This is the heap size for malloc() API in NORTOS and FreeRTOS
* This is also the heap used by pvPortMalloc in FreeRTOS
*/
--heap_size=32768
-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
/* This is the size of stack when R5 is in IRQ mode
* In NORTOS,
* - Here interrupt nesting is enabled
* - This is the stack used by ISRs registered as type IRQ
* In FreeRTOS,
* - Here interrupt nesting is disabled
* - This is stack that is used initally when a IRQ is received
* - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
* - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
*/
__IRQ_STACK_SIZE = 256;
/* This is the size of stack when R5 is in IRQ mode
* - In both NORTOS and FreeRTOS nesting is disabled for FIQ
*/
__FIQ_STACK_SIZE = 256;
__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */
__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */
SECTIONS
{
/* This has the R5F entry point and vector table, this MUST be at 0x0 */
.vectors:{} palign(8) > R5F_VECS
/*.controlfnc:{} palign(8) > R5F_TCMA*/
/* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
* i.e this cannot be placed in DDR
*/
GROUP {
.text.hwi: palign(8)
.text.cache: palign(8)
.text.mpu: palign(8)
.text.boot: palign(8)
.text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
} > MSRAM
/* This is rest of code. This can be placed in DDR if DDR is available and needed */
GROUP {
.text: {} palign(8) /* This is where code resides */
.rodata: {} palign(8) /* This is where const's go */
} > DDR ///MSRAM
/* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
GROUP {
.data: {} palign(8) /* This is where initialized globals and static go */
} > DDR ///MSRAM
/* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
GROUP {
.bss: {} palign(8) /* This is where uninitialized globals go */
RUN_START(__BSS_START)
RUN_END(__BSS_END)
.sysmem: {} palign(8) /* This is where the malloc heap goes */
.stack: {} palign(8) /* This is where the main() stack goes */
} > DDR ///MSRAM
/* This is where the stacks for different R5F modes go */
GROUP {
.irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
RUN_START(__IRQ_STACK_START)
RUN_END(__IRQ_STACK_END)
.fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
RUN_START(__FIQ_STACK_START)
RUN_END(__FIQ_STACK_END)
.svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
RUN_START(__SVC_STACK_START)
RUN_END(__SVC_STACK_END)
.abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
RUN_START(__ABORT_STACK_START)
RUN_END(__ABORT_STACK_END)
.undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
RUN_START(__UNDEFINED_STACK_START)
RUN_END(__UNDEFINED_STACK_END)
} > DDR ///MSRAM
/* Sections needed put into TCM */
GROUP {
CRITICAL_DATA_SECTION: {} palign(8) /* critical data section */
CRITICAL_TEXT_SECTION: {} palign(8) /* critical text section */
} > DDR ///MSRAM
/* Sections needed for C++ projects */
GROUP {
.ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
.init_array: {} palign(8) /* Contains function pointers called before main */
.fini_array: {} palign(8) /* Contains function pointers called after main */
} > MSRAM
/* General purpose user shared memory, used in some examples */
.bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
/* this is used when Debug log's to shared memory are enabled, else this is not used */
.bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
/* this is used only when IPC RPMessage is enabled, else this is not used */
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
GROUP {
.text.TimerP_isr0 : {} palign(8)
.text.TimerTick : {} palign(8)
} > R5F_TCMA
/*.DDR_UNCACHED.filebuf: {} palign(8) > DDR_UNCACHED*/
}
/*
NOTE: Below memory is reserved for DMSC usage
- During Boot till security handoff is complete
0x701E0000 - 0x701FFFFF (128KB)
- After "Security Handoff" is complete (i.e at run time)
0x701F4000 - 0x701FFFFF (48KB)
Security handoff is complete when this message is sent to the DMSC,
TISCI_MSG_SEC_HANDOVER
This should be sent once all cores are loaded and all application
specific firewall calls are setup.
*/
MEMORY
{
R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
/* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
/* when using multi-core application's i.e more than one R5F/M4F active, make sure
* this memory does not overlap with other R5F's
*/
MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000
DDR : ORIGIN = 0x80000000 , LENGTH = 0x80000
/* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
* other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
*/
FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000
DDR_UNCACHED : ORIGIN = 0x80080000 , LENGTH = 0x70000
/* shared memory segments */
/* On R5F,
* - make sure there is a MPU entry which maps below regions as non-cache
*/
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180
LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180
RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
}
请查看"Memory Allocation"窗口。 上述两项功能 仅存储在 TCM 存储器中。
我已经尝试过 TCMA、并对其他 存储器区域采用相同的过程 。
此致、
S.Anil.