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部件号：TSW14J57EVM “线程：测试， TSW14J58EVM”中讨论的其它部件
您好，
客户在使用此设备时遇到错误，请参阅下面的详细信息。
“我们有一台设备连接到另一台 AFE79XX 系列和 TSW14J57。 当我们运行 Latte 设置程序时，我们收到一个错误“无法获取 RX 的链接”
我们不知道这是因为我们按下了 AFE79XX 上的按钮(SW1重置和 SW2重置)，因为它以前工作正常。
请参阅日志文本。
#====== #Executing .. AFE79xx/bringup/setup.py #Start Time 2022-02-15 20:08:09.268000 AFE79xxLibraryPG1p0 spi - USB Instrument created. resetDevice Purge MPSSE mode set Kintex RegProgrammer - USB Instrument created. Kintex RegProgrammer - USB Instrument created. Kintex RegProgrammer - USB Instrument created. #Done executing .. AFE79xx/bringup/setup.py #End Time 2022-02-15 20:08:16.795000 #Execution Time = 7.52700018883 s #================ ERRORS:0, WARNINGS:0 ================# #====== #Executing .. AFE79xx/bringup/devInit.py #Start Time 2022-02-15 20:08:23.953000 Power Card - USB Instrument created. Reset the FPGA and try again. Loaded Libraries #Done executing .. AFE79xx/bringup/devInit.py #End Time 2022-02-15 20:09:10.857000 #Execution Time = 46.9040000439 s #================ ERRORS:1, WARNINGS:0 ================# #====== #Executing .. AFE79xx/bringup/AFE79xx_EVM_Mode7.py #Start Time 2022-02-15 20:09:30.249000 TXA cannot be enabled when TXB is disabled. Consider enabling TXB instead of TXA. The External Sysref Frequency should be an integer factor of: 3.84MHz 2T2R1F Number: 0 Valid Configuration: True laneRateRx: 14745.6 laneRateFb: 14745.6 laneRateTx: 14745.6 2T2R1F Number: 1 Valid Configuration: True laneRateRx: 14745.6 laneRateFb: 14745.6 laneRateTx: 14745.6 Device Initialization for ChipVersion: 2.0 LMK Clock Divider - Device registers reset. LMK Clock Divider - Device registers reset. REFCLOCK is used from LMK source, ensure board connections are ok to do the same DONOT_OPEN_Atharv_FULL - Device registers reset. chipType: 0xa chipId: 0x78 chipVersion: 0x20 SPIA has got control of PLL pages PLL Pages SPI control relinquished. Fuse farm load autoload done successful No autload error Fuse farm load autoload done successful No autload error SPIA has got control of PLL pages PLL Locked PLL Pages SPI control relinquished. SPIA has got control of PLL pages PLL Pages SPI control relinquished. SPIA has got control of PLL pages PLL Pages SPI control relinquished. SPIA has got control of PLL pages PLL Pages SPI control relinquished. Sysref Read as expected Waiting for MACRO_DONE bit to go high, Count: 1 Got MACRO_ERROR : EXECUTION_ERROR MACRO_OPCODE : 0x13 MACRO_NAME : POWER_UP_CALIB Macro Error Status Interpretation is Undefined in MacroLib ERROR INTERPRETATION is : Not Interpreted ###########Device DAC JESD-RX 0 Link Status########### LOS Indicator for (Serdes Loss of signal) lane 0: 1 Serdes-FIFO error for lane 0: 1 LOS Indicator for (Serdes Loss of signal) lane 1: 1 Serdes-FIFO error for lane 1: 1 LOS Indicator for (Serdes Loss of signal) lane 2: 1 Serdes-FIFO error for lane 2: 1 LOS Indicator for (Serdes Loss of signal) lane 3: 1 Serdes-FIFO error for lane 3: 1 Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good. CS State TX0: 0b00000000 . It is expected to be 0b10101010 FS State TX0: 0b00000000 . It is expected to be 0b01010101 Couldn't get the link up for device RX: 0; Alarms: 0xff00 ################################### ###########Device DAC JESD-RX 1 Link Status########### Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good. CS State TX0: 0b00000000 . It is expected to be 0b10101010 FS State TX0: 0b00000000 . It is expected to be 0b01010101 Couldn't get the link up for device RX: 1; Alarms: 0x0 ################################### #Done executing .. AFE79xx/bringup/AFE79xx_EVM_Mode7.py #End Time 2022-02-15 20:11:38.483000 #Execution Time = 128.233999968 s #================ ERRORS:23, WARNINGS:1 ================# #====== #Executing .. AFE79xx/bringup/bringup.py #Start Time 2022-02-15 20:14:10.114000 The External Sysref Frequency should be an integer factor of: 3.84MHz 2T2R1F Number: 0 Valid Configuration: True laneRateRx: 14745.6 laneRateFb: 14745.6 laneRateTx: 14745.6 2T2R1F Number: 1 Valid Configuration: True laneRateRx: 14745.6 laneRateFb: 14745.6 laneRateTx: 14745.6 Device Initialization for ChipVersion: 2.0 LMK Clock Divider - Device registers reset. LMK Clock Divider - Device registers reset. REFCLOCK is used from LMK source, ensure board connections are ok to do the same DONOT_OPEN_Atharv_FULL - Device registers reset. chipType: 0xa chipId: 0x78 chipVersion: 0x20 SPIA has got control of PLL pages PLL Pages SPI control relinquished. Fuse farm load autoload done successful No autload error Fuse farm load autoload done successful No autload error SPIA has got control of PLL pages PLL Locked PLL Pages SPI control relinquished. SPIA has got control of PLL pages PLL Pages SPI control relinquished. SPIA has got control of PLL pages PLL Pages SPI control relinquished. SPIA has got control of PLL pages PLL Pages SPI control relinquished. Sysref Read as expected ###########Device DAC JESD-RX 0 Link Status########### LOS Indicator for (Serdes Loss of signal) lane 0: 1 Serdes-FIFO error for lane 0: 1 LOS Indicator for (Serdes Loss of signal) lane 1: 1 Serdes-FIFO error for lane 1: 1 LOS Indicator for (Serdes Loss of signal) lane 2: 1 Serdes-FIFO error for lane 2: 1 LOS Indicator for (Serdes Loss of signal) lane 3: 1 Serdes-FIFO error for lane 3: 1 Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good. CS State TX0: 0b00000000 . It is expected to be 0b10101010 FS State TX0: 0b00000000 . It is expected to be 0b01010101 Couldn't get the link up for device RX: 0; Alarms: 0xff00 ################################### ###########Device DAC JESD-RX 1 Link Status########### LOS Indicator for (Serdes Loss of signal) lane 0: 1 Serdes-FIFO error for lane 0: 1 LOS Indicator for (Serdes Loss of signal) lane 1: 1 Serdes-FIFO error for lane 1: 1 LOS Indicator for (Serdes Loss of signal) lane 2: 1 LOS Indicator for (Serdes Loss of signal) lane 3: 1 Serdes-FIFO error for lane 3: 1 Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good. CS State TX0: 0b00000000 . It is expected to be 0b10101010 FS State TX0: 0b00000000 . It is expected to be 0b01010101 Couldn't get the link up for device RX: 1; Alarms: 0xbf00 ################################### #Done executing .. AFE79xx/bringup/bringup.py #End Time 2022-02-15 20:15:46.452000 #Execution Time = 96.3379998207 s #================ ERRORS:25, WARNINGS:1 ================#
请提前感谢。
此致，
五月纳德
