[参考译文] TSW14J57EVM：软件和硬件触发不起作用

您好、Louis、

感谢您的耐心等待。 请将随附的.ini 文件复制到以下文件路径、然后重置捕获板连接并重新选择...JMODE0_TRIG 作为 ADC。 然后、您应该能够触发您的捕获。

C：\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J57revE Details\ADC 文件

e2e.ti.com/.../ADC12DJxx00_5F00_JMODE0_5F00_trig.ini

谢谢、

Drew

保存以上述名称命名的以下内容：

[ADC]

Interface name="TSW14J57RevE_16L_XCVR_ADCDDRDACBRAM"
Number of channels=1
Channel Pattern=1
Data Postprocessing=0
\\operation:operand
\\operaion
\\0=bit shift
\\1=xor
\\2=and
\\3=or
\\4=not
\\operand
\\value(+ve if bitshift by right and -ve if bitshift by left)
\\E.g 0:-2,1:1024
\\bitshift by left 2 times and then xor by 1024
Number of Bits=12
Max sample Rate=6400000001
Register_Config="-"
\\[Register Address]:[Register Value]:[Number of Bytes to be sent as]
DLL Version=1.0
Read EVM Setup Procedure="EVM Setup Procedure not available"
\\use <> as delimiter for newline
Menu Enable="Trigger Option"

[Version 1.0]

JESD IP Core_CS=0
JESD IP Core_F=1
JESD IP Core_HD=1
JESD IP Core_K=32
JESD IP Core_L=8
JESD IP Core_M=4
JESD IP Core_N=16
JESD IP Core_NTotal=16
JESD IP Core_S=1
JESD IP Core_SCR=1
JESD IP Core_Tailbits=0
JESD IP Core_LaneSync=1
JESD IP Core_Subclass=1
JESD IP Core_JESDV=1
\\MIF Config= 0.611G to 10G:RX:RX_PMA_x40

Trigger Input Polarity Selection = 1
Trigger Output Default State = 0
Trigger Output Pulse Width = 40
Sysref Based Master Slave Trigger = 0
Is Capture Trigger SMA = 1

MIF Config= 1.5G to 3.21G:RX:RX_PMA_x20,3.21G to 16G:RX:RX_PMA_x40

\\List of Lane Rate Range,PLL Type and their MIF File names that needs to be configured,separated by ":"
\\These MIF Files need to be present under MIF Files Folder
Fabric PLL Counter = 1.5G to 3.21G:0x080404,3.21G to 16G:0x080202
Invert Sync Polarity = 0 
\\Invert Sync polarity, 1:invert; 0: do not invert
Invert Serdes Data = 240  
\\Invert Serdes Data, 1:invert; 0: do not invert
Enable Individual Lane Inversion = 1
\\Enable Individual Lane Inversion, 1:lanewise inverting enabled; 0:do not invert
\\Invert physical lanes 4-7
\\Invert Serdes Data bitwise inversion setting values from 0 to 65535 legal for 16 lanes
Transceiver Mode = 0  
\\1:xcvr mode; 0: TX/RX only mode
Lane Mapping=lane0:3,lane1:0,lane2:2,lane3:1,lane4:7,lane5:4,lane6:6,lane7:5
\\Lane pattern for the LMF modes
Group 128 bits Flag = 1
\\If 1, will group 128 bits from each DDR, and then apply the channel pattern
\\If this parameter is not present, it will follow the earlier mode used in v2.40
Bit Packing = 1
\\0 - Data are not bit packed. 
\\1 -  Data are bit packed(MSB aligned) without any padded zeroes
Bit Packing Channel Pattern =C1S1[11:0],C1S9[11:0],C1S17[11:4],C1S3[11:0],C1S11[11:0],C1S19[11:4],C1S5[11:0],C1S13[11:0],C1S21[11:4],C1S7[11:0],C1S15[11:0],C1S23[11:4],C1S2[11:0],C1S10[11:0],C1S18[11:4],C1S4[11:0],C1S12[11:0],C1S20[11:4],C1S6[11:0],C1S14[11:0],C1S22[11:4],C1S8[11:0],C1S16[11:0],C1S24[11:4],C1S17[3:0],C1S25[11:0],C1S33[11:0],T[4],C1S19[3:0],C1S27[11:0],C1S35[11:0],T[4],C1S21[3:0],C1S29[11:0],C1S37[11:0],T[4],C1S23[3:0],C1S31[11:0],C1S39[11:0],T[4],C1S18[3:0],C1S26[11:0],C1S34[11:0],T[4],C1S20[3:0],C1S28[11:0],C1S36[11:0],T[4],C1S22[3:0],C1S30[11:0],C1S38[11:0],T[4],C1S24[3:0],C1S32[11:0],C1S40[11:0],T[4]
\\Channel and Sample number starts from 1. Bit numbering starts from 0
\\Tail bits are specified by T[No of Tail Bits]
\\Channel pattern should be formed as the data will be in transceiver mode.
\\(i.e) In RX only mode, take 128 bits from DDRA, 128 bits from DDRB,followed by next 128 bits from DDRA, etc..
Lane Rate Adjustment Factor=0.8