This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1160373/tfp410-vsync-hsync-to-de-assertion-timing
HSYNC/VSYNC 置位周期是否至少为1 Tpixel、或者您是否需要多个周期？ 如果我需要多个周期、是否必须遵循 VESA-CVT 规范第3.6节？
在消隐期间、HSYNC 和 VSYNC 在一个 Tpixel 边界上输出(不需要多个周期)。 这些信号在 IDCK 的上升沿或下降沿被锁存。
