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https://e2e.ti.com/support/logic-group/logic/f/logic-forum/972167/sn74lvc2g07-output-leakage-when-vin-is-powered-down
当输入电压为低电平(0V)时、如果 SN74LVC2G07的输出连接到高电平(例如3.3V 通过1k 上拉电阻)、输出中会出现什么类型的泄漏？
当 Vin 为低电平时、输出将主动驱动为低电平。 在这种情况下、泄漏无关紧要、因为实际输出电流要大得多。
如果您实际上是指 VCC = 0V：这被指定为 Ioff。
抱歉-我指的是 Vcc = 0V
谢谢！
