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https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1334278/sn74lv165a-integrate-level-testing-issue-with-ic-last-bit-not-responding-to-pulses
您好！
我们在集成测试过程中遇到此 IC 问题。 此 IC 的最后位数据输出不响应脉冲、即使在通过开关提供输入到数据输入时也是如此。
请帮我解决这个问题。
波形看起来不错。 (由于上升沿、CLK 上有16个时钟脉冲、CLK_INH 上有17个时钟脉冲。)
请具体指明波形的哪个部分不可预期。
