This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1393299/sn74lvc244a-what-is-the-state-of-input-a-when-oe-pull-high
工具与软件：
您好、先生
当 OE 拉为高电平时、输出阻抗(Y 侧)为高电平、输入侧如何？
我们想知道在这种情况下、一侧的阻抗是高阻抗还是低阻抗、还是悬空？
谢谢你
CMOS 输入始终具有高阻抗。
CMOS 输入绝不能悬空、例如、您必须连接有效的逻辑电压。
