[参考译文] MSP430FR2155：MSP430FR2155

#include <msp430.h>
#include "driverlib/MSP430FR2xx_4xx/inc/hw_memmap.h"
#include "stdint.h"


#define RTC_CLOCKSOURCE_SMCLK       RTCSS__SMCLK
#define RTC_CLOCKSOURCE_ACLK        RTCSS__XT1CLK

void RTC_start(uint16_t, uint16_t);

void RTCInit()
{
    HWREG16(RTC_BASE + OFS_RTCCTL) &= ~(RTCSS_3 | RTCPS_7);
    HWREG16(RTC_BASE + OFS_RTCMOD) = 32767;
    RTC_start(RTC_BASE,  RTCSS_1);
}

void InitTimer()
{
    HWREG16(TIMER_B0_BASE + OFS_TBxCTL) = TBSSEL__SMCLK;
    HWREG16(TIMER_B0_BASE + OFS_TBxCCR0) = 239;
    HWREG16(TIMER_B0_BASE + OFS_TBxCCTL0) |= CCIE;

    HWREG16(TIMER_B0_BASE + OFS_TBxCTL) |=  MC__UP;
}

void RTC_start(uint16_t baseAddress, uint16_t clockSource)
{
    HWREG16(baseAddress + OFS_RTCCTL) &= ~RTCSS_3;

#ifdef RTCCKSEL
    HWREG16(SYS_BASE + OFS_SYSCFG2) &= ~RTCCKSEL;

    if(clockSource == RTC_CLOCKSOURCE_ACLK)
    {
        HWREG16(SYS_BASE + OFS_SYSCFG2) |= RTCCKSEL;
        HWREG16(baseAddress + OFS_RTCCTL) |= RTCSS_1;
    }
    else
    {
        HWREG16(baseAddress + OFS_RTCCTL) |= clockSource;
    }
#else
    HWREG16(baseAddress + OFS_RTCCTL) |= clockSource;
#endif

    HWREG16(baseAddress + OFS_RTCCTL) |= RTCSR;
}

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;                    // Stop watchdog timer

    // Configure two FRAM waitstate as required by the device datasheet for MCLK
    // operation at 24MHz(beyond 8MHz) _before_ configuring the clock system.
    FRCTL0 = FRCTLPW | NWAITS_2 ;

    P2SEL1 |= BIT6 | BIT7;                       // P2.6~P2.7: crystal pins
    do
    {
        CSCTL7 &= ~(XT1OFFG | DCOFFG);           // Clear XT1 and DCO fault flag
        SFRIFG1 &= ~OFIFG;
    } while (SFRIFG1 & OFIFG);                   // Test oscillator fault flag

    __bis_SR_register(SCG0);                     // disable FLL
    CSCTL3 |= SELREF__XT1CLK;                    // Set XT1 as FLL reference source
    CSCTL0 = 0;                                  // clear DCO and MOD registers
    CSCTL1 |= DCORSEL_7;                         // Set DCO = 24MHz
    CSCTL2 = FLLD_0 + 731;                       // DCOCLKDIV = 24MHz
    __delay_cycles(3);
    __bic_SR_register(SCG0);                     // enable FLL
    while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));   // FLL locked

    CSCTL4 = SELMS__DCOCLKDIV | SELA__XT1CLK;   // set XT1 (~32768Hz) as ACLK source, ACLK = 32768Hz
                                                 // default DCOCLKDIV as MCLK and SMCLK source

    P1DIR |= BIT0 | BIT1 | BIT2;                 // set ACLK SMCLK and LED pin as output
    P1SEL1 |= BIT0 | BIT1;                       // set ACLK and  SMCLK pin as second function

    PM5CTL0 &= ~LOCKLPM5;                        // Disable the GPIO power-on default high-impedance mode
                                                 // to activate previously configured port settings

    RTCInit();
    InitTimer();
    _enable_interrupts();


    while(1)
    {
        LPM0;
    }
}
uint16_t delta[128];
uint16_t count, pre_rtc;

#pragma vector = TIMER0_B0_VECTOR
__interrupt void TIMER0_B0_ISR(void)
{

    delta[count] = RTCCNT - pre_rtc;
    pre_rtc = RTCCNT;
    count++;

    if (count>=120)
    {
           HWREG16(TIMER_B0_BASE + OFS_TBxCTL) &=  ~MC;

           /* set a break point on nop() */
           _nop();

           HWREG16(TIMER_B0_BASE + OFS_TBxCTL) |=  MC__UP;


    }
}