[参考译文] MSP430FR2355：19200年以上时 UART 不工作？

        if (ISR.UARTmssgRcvdFlag)
        {
            applicationUART.pSysCommsA->UCAxIE &= ~UCRXIE;

#include "main.h"

void init_ClockTo16MHz(void);
static void Software_Trim();
void UART_Init(void);
uint16_t itoa(uint16_t k);

struct HardFlags ISR = {F};

static __vo uint8_t buffer[MSSG_LENGTH] = { [ 0 ... MSSG_LENGTH - 1] = 0 }, monitor = 0;

__vo uint8_t mssgLength = 0;


int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;   // stop watchdog timer
    PM5CTL0 &= ~LOCKLPM5;
    init_ClockTo16MHz();
    UART_Init();



    while(1)
    {
        __bis_SR_register( LPM3_bits + GIE);

        if (ISR.UARTmssgRcvdFlag)
        {
            UCA1IE &= ~UCRXIE;
            ISR.UARTmssgRcvdFlag = F;
            mssgLength = 0;
            UCA1IFG &= ~UCRXIFG;
            UCA1IE |= UCRXIE;
        }

    }
}

#pragma vector=USCI_A1_VECTOR
__interrupt void COMM_ISR(void)
{
    switch(__even_in_range(UCA1IV, USCI_UART_UCTXCPTIFG))
    {
      case USCI_NONE: break;
      case USCI_UART_UCRXIFG:
          buffer[mssgLength] = UCA1RXBUF;


          if (buffer[mssgLength] == 0x0D)
          {
              ISR.UARTmssgRcvdFlag = T;
              LPM3_EXIT;
          }

          mssgLength++;
          break;
      case USCI_UART_UCTXIFG:
          break;
      case USCI_UART_UCSTTIFG: break;
      case USCI_UART_UCTXCPTIFG: break;
    }
}

#ifdef LOCAL
void UART_Init(void)
{
    P4SEL0 |= BIT3 | BIT2;
    UCA1CTLW0 |= UCSWRST;
    UCA1CTLW0 |= UCSSEL__SMCLK;
    //UCA1BR0 = 52; //19200
    UCA1BR0 = 13; //115200
    UCA1BR1 = 0x00;
    //UCA1MCTLW = 0x4900 | UCOS16 | UCBRF_1; //19200
    UCA1MCTLW = 0x8400 | UCOS16 | UCBRF_0; //115200
    UCA1CTLW0 &= ~UCSWRST;

    UCA1IFG &= ~UCRXIFG;
    UCA1IE |= UCRXIE;

}


void init_ClockTo16MHz(void)
{
    FRCTL0 = FRCTLPW | NWAITS_1;
    P2SEL1 |= BIT6 | BIT7;
    do
    {
        CSCTL7 &= ~(XT1OFFG | DCOFFG);           // Clear XT1 and DCO fault flag
        SFRIFG1 &= ~OFIFG;
    } while (SFRIFG1 & OFIFG);                   // Test oscillator fault flag

    __bis_SR_register(SCG0);                     // disable FLL
    CSCTL3 |= SELREF__XT1CLK;                    // Set XT1 as FLL reference source
    CSCTL1 |= DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_5;// DCOFTRIM=5, DCO Range = 16MHz
    CSCTL2 = FLLD_0 + 487;                       // DCOCLKDIV = 16MHz
    __delay_cycles(3);
    __bic_SR_register(SCG0);                     // enable FLL
    Software_Trim();
    while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));
    CSCTL5 |= DIVS_1;
    CSCTL4 = SELMS__DCOCLKDIV | SELA__XT1CLK;   // set XT1 (~32768Hz) as ACLK source, ACLK = 32768Hz
}


static void Software_Trim()
{
    unsigned int oldDcoTap = 0xffff;
    unsigned int newDcoTap = 0xffff;
    unsigned int newDcoDelta = 0xffff;
    unsigned int bestDcoDelta = 0xffff;
    unsigned int csCtl0Copy = 0;
    unsigned int csCtl1Copy = 0;
    unsigned int csCtl0Read = 0;
    unsigned int csCtl1Read = 0;
    unsigned int dcoFreqTrim = 3;
    unsigned char endLoop = 0;

    do
    {
        CSCTL0 = 0x100;                         // DCO Tap = 256
        do
        {
            CSCTL7 &= ~DCOFFG;                  // Clear DCO fault flag
        }while (CSCTL7 & DCOFFG);               // Test DCO fault flag

        __delay_cycles((unsigned int)3000 * 16);// Wait FLL lock status (FLLUNLOCK) to be stable
                                                           // Suggest to wait 24 cycles of divided FLL reference clock
        while((CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)) && ((CSCTL7 & DCOFFG) == 0));

        csCtl0Read = CSCTL0;                   // Read CSCTL0
        csCtl1Read = CSCTL1;                   // Read CSCTL1

        oldDcoTap = newDcoTap;                 // Record DCOTAP value of last time
        newDcoTap = csCtl0Read & 0x01ff;       // Get DCOTAP value of this time
        dcoFreqTrim = (csCtl1Read & 0x0070)>>4;// Get DCOFTRIM value

        if(newDcoTap < 256)                    // DCOTAP < 256
        {
            newDcoDelta = 256 - newDcoTap;     // Delta value between DCPTAP and 256
            if((oldDcoTap != 0xffff) && (oldDcoTap >= 256)) // DCOTAP cross 256
                endLoop = 1;                   // Stop while loop
            else
            {
                dcoFreqTrim--;
                CSCTL1 = (csCtl1Read & (~DCOFTRIM)) | (dcoFreqTrim<<4);
            }
        }
        else                                   // DCOTAP >= 256
        {
            newDcoDelta = newDcoTap - 256;     // Delta value between DCPTAP and 256
            if(oldDcoTap < 256)                // DCOTAP cross 256
                endLoop = 1;                   // Stop while loop
            else
            {
                dcoFreqTrim++;
                CSCTL1 = (csCtl1Read & (~DCOFTRIM)) | (dcoFreqTrim<<4);
            }
        }

        if(newDcoDelta < bestDcoDelta)         // Record DCOTAP closest to 256
        {
            csCtl0Copy = csCtl0Read;
            csCtl1Copy = csCtl1Read;
            bestDcoDelta = newDcoDelta;
        }

    }while(endLoop == 0);                      // Poll until endLoop == 1

    CSCTL0 = csCtl0Copy;                       // Reload locked DCOTAP
    CSCTL1 = csCtl1Copy;                       // Reload locked DCOFTRIM
    while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked
}
#endif