[参考译文] MSP430FR4133：MSP430FR4133多 ADC 采样行为不符合使用示例的预期

#include <msp430.h>

unsigned int ADC_Result[3];                                    // 8-bit ADC conversion result array
unsigned int i;

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;                                   // Stop WDT
    
    // Configure ADC A0~8 pins
    SYSCFG2 |= ADCPCTL0 | ADCPCTL5 | ADCPCTL8;
  
    // Disable the GPIO power-on default high-impedance mode to activate
    // previously configured port settings
    PM5CTL0 &= ~LOCKLPM5;

    // Configure ADC 
    ADCCTL0 |= ADCSHT_2 | ADCON;                                // 16ADCclks, ADC ON
    ADCCTL1 |= ADCSHP | ADCSHS_2 | ADCCONSEQ_3;                 // ADC clock MODCLK, sampling timer, TA1.1B trig.,repeat sequence
    ADCCTL2 |= ADCRES;                                         // 10-bit conversion results
    ADCMCTL0 |= ADCINCH_8 | ADCSREF_0;                          // A0~2(EoS); Vref=Vcc
    ADCIE |= ADCIE0;                                            // Enable ADC conv complete interrupt
    
    // Configure reference
    PMMCTL0_H = PMMPW_H;                                        // Unlock the PMM registers
    PMMCTL2 |= INTREFEN;                                        // Enable internal reference
    __delay_cycles(400);                                        // Delay for reference settling
    __no_operation();

    // Configure TA1.1B as ADC trigger signal
    // Note: The TA1.1B is configured for 200us 50% PWM, which will trigger ADC
    // sample-and-conversion every 200us. The period of TA1.1B trigger event
    // should be more than the time period taken for ADC sample-and-conversion
    // and ADC interrupt service routine of each channel, which is about 57us in this code
    TA1CCR0 = 200-1;                                            // PWM Period, 200us
    TA1CCTL1 = OUTMOD_7;                                        // CCR1 reset/set
    TA1CCR1 = 100;                                              // CCR1 PWM duty cycle, 50%
    TA1CTL = TASSEL__SMCLK | MC__UP | TACLR;                    // SMCLK, up mode, clear TAR

    while(1)                                
    {
        i = 2;

        ADCCTL0 |= ADCENC;                                      // Enable ADC
        TA1CTL |= TACLR;                                        // Clear TAR to start the ADC sample-and-conversion
        __bis_SR_register(LPM0_bits | GIE);                     // Enter LPM0 w/ interrupts
        __no_operation();                                       // Only for debugger

    }
}

// ADC interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=ADC_VECTOR
__interrupt void ADC_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC_VECTOR))) ADC_ISR (void)
#else
#error Compiler not supported!
#endif
{
    switch(__even_in_range(ADCIV,ADCIV_ADCIFG))
    {
        case ADCIV_NONE: 
            break;                              
        case ADCIV_ADCOVIFG: 
            break;             
        case ADCIV_ADCTOVIFG: 
            break;            
        case ADCIV_ADCHIIFG: 
            break;             
        case ADCIV_ADCLOIFG: 
            break;             
        case ADCIV_ADCINIFG: 
            break;             
        case ADCIV_ADCIFG:
            ADC_Result[i] = ADCMEM0;
            if(i == 0)
            {
                __no_operation();                               // Only for debugger
                i = 2;
            }
            else
            {
                i--;
            }
            break;                                             
        default: 
            break; 
    }  
}

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 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
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 *
 *******************************************************************************
 * 
 *                       MSP430 CODE EXAMPLE DISCLAIMER
 *
 * MSP430 code examples are self-contained low-level programs that typically
 * demonstrate a single peripheral function or device feature in a highly
 * concise manner. For this the code may rely on the device's power-on default
 * register values and settings such as the clock configuration and care must
 * be taken when combining code from several examples to avoid potential side
 * effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
 * for an API functional library-approach to peripheral configuration.
 *
 * --/COPYRIGHT--*/
//******************************************************************************
//  MSP430FR413x Demo - ADC, Sample A2/A1/A0, internal 1.5V Ref.
//
//  Description: This example works on Repeat-sequence-of-channels Mode
//  with TA1.1B as the trigger signal.
//  A2/A1/A0 is sampled 16ADCclks with reference to 1.5V.
//  Internal oscillator times sample (16x) and conversion(13x).
//  Inside ADC_ISR A2/A1/A0 sample value put into array ADC_Result[3].
//  ACLK = default REFO ~32768Hz, MCLK = SMCLK = default DCODIV ~1MHz.
//
//  Note: The TA1.1B is configured for 200us 50% PWM, which will trigger ADC
//  sample-and-conversion every 200us. The period of TA1.1B trigger event
//  should be more than the time period taken for ADC sample-and-conversion
//  and ADC interrupt service routine of each channel, which is about 57us in this code
//  
//
//                MSP430FR4133
//             -----------------
//         /|\|                 |
//          | |                 |
//          --|RST              |
//            |                 |
//        >---|P1.2/A2          |
//        >---|P1.1/A1          |
//        >---|P1.0/A0          |
//
//
//  Wei Zhao
//  Texas Instruments Inc.
//  July 2018
//  Built with IAR Embedded Workbench v7.11 & Code Composer Studio v7.4
//******************************************************************************
#include <msp430.h>

unsigned int ADC_Result[9];                                    // 8-bit ADC conversion result array
unsigned int i;

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;                                   // Stop WDT
    
    // Configure ADC A0~2 pins
    SYSCFG2 |= ADCPCTL0 | ADCPCTL5 | ADCPCTL8;
  
    // Disable the GPIO power-on default high-impedance mode to activate
    // previously configured port settings
    PM5CTL0 &= ~LOCKLPM5;

    // Configure ADC 
    ADCCTL0 |= ADCSHT_2 | ADCON;                                // 16ADCclks, ADC ON
    ADCCTL1 |= ADCSHP | ADCSHS_2 | ADCCONSEQ_3;                 // ADC clock MODCLK, sampling timer, TA1.1B trig.,repeat sequence
    ADCCTL2 |= ADCRES;                                         // 10-bit conversion results
    ADCMCTL0 |= ADCINCH_8 | ADCSREF_0;                          // A0~2(EoS); Vref=1.5V
    ADCIE |= ADCIE0;                                            // Enable ADC conv complete interrupt
    
    // Configure reference
    PMMCTL0_H = PMMPW_H;                                        // Unlock the PMM registers
    PMMCTL2 |= INTREFEN;                                        // Enable internal reference
    __delay_cycles(400);                                        // Delay for reference settling
    __no_operation();

    // Configure TA1.1B as ADC trigger signal
    // Note: The TA1.1B is configured for 200us 50% PWM, which will trigger ADC
    // sample-and-conversion every 200us. The period of TA1.1B trigger event
    // should be more than the time period taken for ADC sample-and-conversion
    // and ADC interrupt service routine of each channel, which is about 57us in this code
    TA1CCR0 = 200-1;                                            // PWM Period, 200us
    TA1CCTL1 = OUTMOD_7;                                        // CCR1 reset/set
    TA1CCR1 = 100;                                              // CCR1 PWM duty cycle, 50%
    TA1CTL = TASSEL__SMCLK | MC__UP | TACLR;                    // SMCLK, up mode, clear TAR

    while(1)                                
    {
        i = 9;

        ADCCTL0 |= ADCENC;                                      // Enable ADC
        TA1CTL |= TACLR;                                        // Clear TAR to start the ADC sample-and-conversion
        __bis_SR_register(LPM0_bits | GIE);                     // Enter LPM0 w/ interrupts
        __no_operation();                                       // Only for debugger

    }
}

// ADC interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=ADC_VECTOR
__interrupt void ADC_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC_VECTOR))) ADC_ISR (void)
#else
#error Compiler not supported!
#endif
{
    switch(__even_in_range(ADCIV,ADCIV_ADCIFG))
    {
        case ADCIV_NONE: 
            break;                              
        case ADCIV_ADCOVIFG: 
            break;             
        case ADCIV_ADCTOVIFG: 
            break;            
        case ADCIV_ADCHIIFG: 
            break;             
        case ADCIV_ADCLOIFG: 
            break;             
        case ADCIV_ADCINIFG: 
            break;             
        case ADCIV_ADCIFG:
            ADC_Result[i] = ADCMEM0;
            if(i == 0)
            {
                __no_operation();                               // Only for debugger
                i = 9;
            }
            else
            {
                i--;
            }
            break;                                             
        default: 
            break; 
    }  
}