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器件型号：MSP430FR4131 工具与软件：
你好。
我正在使用 CCS V12.6.0.00008 和 msp430fr4131。 我 在此代码中有一个怪异的 FRAM 用法：
// Built with Code Composer Studio v12
//******************************************************************************
#include <msp430fr4131.h>
#define us 16 // define the the value of uSec to be used in delay & _delay_cycles functions
#define ms 16000 // define the the value of mSec to be used in delay & _delay_cycles functions
#define _5ms 80000 // define the the value of 5mSec to be used in delay & _delay_cycles functions
#define _10ms 160000 // define the the value of 10mSec to be used in delay & _delay_cycles functions
#define _50ms 800000 // define the the value of 50mSec to be used in delay & _delay_cycles functions
#define _100ms 1600000 // define the the value of 100mSec to be used in delay & _delay_cycles functions
#define _sec 16000000 // define the the value of Sec to be used in delay & _delay_cycles functions
//******************************************************************************
void initGPIO()
{
// make all inputs
P1DIR = 0x00; P2DIR = 0x00; P3DIR = 0x00; P4DIR = 0x00;
P5DIR = 0x00; P6DIR = 0x00; P7DIR = 0x00; P8DIR = 0x00;
// Enable Pull up/down R
P1REN = 0xFF; P2REN = 0xFF; P3REN = 0xFF; P4REN = 0xFF;
P5REN = 0xFF; P6REN = 0xFF; P7REN = 0xFF; P8REN = 0xFF;
// Make all inputs pulled up
P1OUT = 0xFF; P2OUT = 0xFF; P3OUT = 0xFF; P4OUT = 0xFF;
P5OUT = 0xFF; P6OUT = 0xFF; P7OUT = 0xFF; P8OUT = 0xFF;
// Disable the GPIO power-on default high-impedance mode
// to activate previously configured port settings
PM5CTL0 &= ~LOCKLPM5;
}
//******************************************************************************
void initClock()
{
// Configure one FRAM wait state as required by the device data sheet for MCLK
// operation beyond 8MHz _before_ configuring the clock system.
FRCTL0 = FRCTLPW | NWAITS_1;
__bis_SR_register(SCG0); // disable FLL
CSCTL3 |= SELREF__REFOCLK; // Set REFO as FLL reference source
CSCTL0 = 0; // clear DCO and MOD registers
CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first
CSCTL1 |= DCORSEL_5; // Set DCO = 16MHz
CSCTL2 = FLLD_0 + 487; // set to fDCOCLKDIV = (FLLN + 1)*(fFLLREFCLK/n)
// = (487 + 1)*(32.768 kHz/1)
// = ~16 MHz (= 15990784 Hz)
__delay_cycles(3);
__bic_SR_register(SCG0); // enable FLL
while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // FLL locked
CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK;
}
//********************************************************
// main program variables
//********************************************************
char batt_body1 = 0; // will represent the outer body
char batt_body2 = 0; // will represent the outer body
char batt_body3 = 0; // will represent the outer body
char batt_body4 = 0; // will represent the outer body
char batt_top1 = 0; // will represent the top part
char batt_top2 = 0; // will represent the top part
char batt_top3 = 0; // will represent the top part
char batt_top4 = 0; // will represent the top part
void main( void )
{
WDTCTL = WDTPW | WDTHOLD; // Stop watch dog timer
initGPIO(); // setup digital IO pins
initClock(); // setup Clock = 16MHz
_delay_cycles(_sec); // delay 1
batt_body1 = 1;
batt_body2 = 1;
batt_body3 = 1;
batt_body4 = 1;
batt_top1 = 1;
batt_top2 = 1;
batt_top3 = 1;
batt_top4 = 1;
while (1)
{
_delay_cycles(_sec); // delay 2
}//END OF while (1)
}// END OF MAIN
按原样代码可得出 FRAM 使用量为798、共3968 20%。
如果移除"delay 1"线路、则 FRAM 将达到 3968 19%中776的 FRAM 用量。
但是、如果移除"delay 2"线路(保持"delay 1")、 则 在3968 6%的情况下、FRAM 使用量将为242。
还有一个问题、如果我保留两个延迟并删除所有八个 batt_XXX 变量分配、 3968 6%的 FRAM 使用量将为264。
那么、具体情况是什么。
谢谢
