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器件型号:MSP430FR2475 工具与软件:
你(们)好
我有一个产品,在低温下串行通信失败(<5摄氏度)。
我将使用 DCO (16MHz)来生成我的115200 Buadrate
我正在使用频率为32768Hz 的外部 XTAL。
这是我的初始化例程:
const uint16_t u16Ratio = 488U;
/* setup pins for XCLK */
P2SEL0 |= XOUT | XIN;
/* use XCLK as ACLK */
CSCTL6 &= ( uint16_t ) ~ ( ( uint16_t ) DIVA );
CSCTL4 &= ( uint16_t ) ~ ( ( uint16_t ) SELA );
/* set FRAM wait states to 1 */
/*lint -save -e960 */
FRCTL0 = FRCTLPW | NWAITS_1;
/*lint -restore */
/* set ACLK to X Inputs */
CSCTL3 &= ( uint16_t ) ~ ( ( uint16_t ) SELREF_3 );
CSCTL3 |= ( uint16_t ) REFOLP_1;
__bis_SR_register( SCG0 ); /* disable FLL */
/* Set DCO FLL reference = REFO */
CSCTL0 = 0U; /* clear DCO and MOD registers */
CSCTL1 &= ( uint16_t ) ~ ( ( uint16_t ) DCORSEL_7 ); /* Clear DCO frequency select bits first */
CSCTL1 |= ( uint16_t ) DCORSEL_5; /* Set DCO frequency range. DCO Range = 16MHz */
CSCTL2 = ( u16Ratio - 1U ); /* f(DCOCLKDIV) = 16MHz */
CSCTL0 = __data20_read_short( TLV_16MHz_ADDR ); /* load DCO TLV trim vale to DCO Tap */
__delay_cycles( 3U );
__bic_SR_register( SCG0 ); /* enable FLL */
CSCTL4 |= ( uint16_t ) SELMS__REFOCLK; /* set REFO(~32768Hz) as MCLK -- This delay may cause fake lock when DCOTAP=0 */
__delay_cycles( 10U ); /* delay 10 FLL reference clock cycles */
while( ( CSCTL7 & ( ( uint16_t ) FLLUNLOCK0 | ( uint16_t ) FLLUNLOCK1 ) ) > 0U )
{
/* Check if FLL locked */
}
/* set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz */
/* default DCOCLKDIV as MCLK and SMCLK source */
CSCTL4 &= ( uint16_t ) ~ ( ( uint16_t ) SELMS | ( uint16_t ) SELA );