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https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/913817/ucc27511-ucc27511-vdd
假设 UCC27511 IN+始终保持高电平、VDD 电源稍后启动、即 VDD=4.2V (UVLO 开启阈值典型值)之间的延迟时间 输出上拉至高电平(TD)、如下图所示？
您好、John、
感谢您的联系。
我将深入研究这一点、并在您重新附加图像时尽早回复您。
此致、
-Mamadou
John、
由于我们正在离线讨论此线程、我将该线程标记为"已解析"并"关闭"。
