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器件型号：AM69 工具与软件：
您好、TI 专家：
我们有基于 AM69 SoC 的定制硬件、打算使用 PCIe_SOC_REFCLK0_OUT、PCIE_SOC_REFCLK1_OUT、PCIE_SOC_REFCLK2_OUT 和 PCIE_SOC_REFCLK3_OUT 引脚为 PCIe 器件提供基准时钟。
根据 AM69 TRM 和来自 J784S4 EVM 板的补丁、我确定需要在器件树中启用 ACSPCIE0和 ACSPCIE1模块(下面的补丁)。
我有以下问题：
- 对于 PCIe3_RC (PCIe@2930000)节点、PCIe 参考时钟仅在 ti、syscon-acspcie-proxy-ctrl =<&acspcie0_proxy_ctrl 0x3>时起作用。 同样、PCIe2_RC (PCIe@2920000)节点是否应该具有 ti、syscon-acspcie-proxy-ctrl =<&acspcie1_proxy_ctrl 0x3>？ 当 bit-mask 为0x2或0x1而不是0x3时、PCIe 参考时钟不起作用。
此配置是否正确？ 另外、如何为每个 SERDES 映射 ACSPCIE 时钟缓冲器？ - 尽管在实际硬件上 PCIe 参考时钟在100MHz 上运行、k3conf 转储时钟命令会将所有 DEV_BOARD0_PCIe_REFCLK*值显示为0。 您能解释一下为什么会发生这种情况吗？
From 889e4f447920cba44bc61a6fb4e9f3a4545bdc1d Mon Sep 17 00:00:00 2001
From: Parth Pancholi <parth.pancholi@toradex.com>
Date: Fri, 7 Mar 2025 11:02:20 +0100
Subject: [PATCH 1/2] arm64: dts: ti: k3-j784s4-main: Enable ACSPCIE0 output
for PCIe3
The PCIe reference clock required by the PCIe Endpoints corresponding to the
PCIe3 instance could be driven by the ACSPCIE0 module. Add the device-tree
support for enabling the same.
TODO: bitmask 0x3 for '<&acspcie0_proxy_ctrl 0x3>' is not clear.
Upstream-Status: Pending
Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index ab4a8c4444bb..f7557d2341e6 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -1205,11 +1205,12 @@ pcie3_rc: pcie@2930000 {
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
+ ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 335 0>;
- clock-names = "fck";
+ clocks = <&k3_clks 335 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
--
2.34.1From 30642b45b151a52c4ad08a73177db0ddd4962112 Mon Sep 17 00:00:00 2001
From: Parth Pancholi <parth.pancholi@toradex.com>
Date: Fri, 7 Mar 2025 11:14:34 +0100
Subject: [PATCH 2/2] arm64: dts: ti: k3-j784s4-main: Enable ACSPCIE1 output
for PCIe0 and PCIe2
The PCIe reference clock required by the PCIe Endpoints corresponding to the
PCIe0 and PCIe2 instances could be driven by the ACSPCIE1 module. Add the
device-tree support for enabling the same.
TODO: bitmask 0x3 for '<&acspcie1_proxy_ctrl 0x3>' is not clear.
Upstream-Status: Pending
Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index f7557d2341e6..46ea13f049b7 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -147,6 +147,11 @@ acspcie0_proxy_ctrl: acspcie0-ctrl@1a090 {
reg = <0x1a090 0x4>;
};
+ acspcie1_proxy_ctrl: acspcie1-ctrl@1a094 {
+ compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon";
+ reg = <0x1a094 0x4>;
+ };
+
serdes_ln_ctrl: mux-controller@4080 {
compatible = "reg-mux";
reg = <0x00004080 0x30>;
@@ -1117,11 +1122,12 @@ pcie0_rc: pcie@2900000 {
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+ ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x1>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 332 0>;
- clock-names = "fck";
+ clocks = <&k3_clks 332 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
@@ -1176,11 +1182,12 @@ pcie2_rc: pcie@2920000 {
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;
+ ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 334 0>;
- clock-names = "fck";
+ clocks = <&k3_clks 334 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
--
2.34.1谢谢你。
此致、
Parth P
