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[参考译文] TMS320C6726B:Dmax 不会将 SPIBUF 传输到缓冲区

Guru**** 2364370 points
请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1507473/tms320c6726b-dmax-is-not-transfer-spibuf-to-my-buffer

部件号:TMS320C6726B

工具/软件:

我正在测试我上面分享的配置以及一些不同的组合。
我可以成功接收从 SPI 主器件发送的数据。我通过检查 SPIFLG 标志并直接从 SPIBUF 寄存器读取接收到的数据来验证这一点。
但是、DMAX 事件似乎不会触发、或者 DMAX 不会向我提供地址的缓冲区中执行传输。

由于我可以确认 SPI 从器件正在正确接收数据、因此我假设 SPI 和 DMAX 配置正确。
我怀疑问题可能与我的中断设置有关。 有时、我的代码会崩溃、这使我认为配置中断的方式可能存在错误。

您能帮助我了解一下我在中断配置中可能犯的错误吗?
如果您能提供任何指导或建议、我将不胜感激。

提前感谢您的支持!

    /*1- dMAX event High priority*/
    dMax_ptr[DEHPR]= 0x2000; // event 13  set a High priority
    /*2- dMAX Event polarity */
    dMax_ptr[DEPR] = 0x2000; // event flag is set on falling(0) edge
    
    /* PaRAM SPI Slave Transfer
     *
     * bit 4-0 =ETYPE = 0b00010 // event type: SPI slave data transfer
     * bit 5 =RLOAD = 0b1 // Reload Active counter
     * bit 7-6 =ESIZE = 0b10 // 16-bit Element
     * bit 23-8 =PTE = 0x1d4 // pointer to transfer entry // transfer entry-7
     * bit 27-24 =TCC = 15-0 // Transfer Complete Code.
     * bit 28 =TCINT = 0b1 // After completing a whole transfer, the dMAX controller sets a TCC pending bit and triggers an interrupt to the CPU.
     * bit 29 =SPI = 0b0 // SPI0 Selection
     * bit 31-30 =reserved
     *
     *      = 0x1001D4A2
     * */
    dMaxEvent_ptr[13]= 0x1001D4A2; // event entry 13

    /*
     * dmax transfer entry for spi slave transfer
     * fixed 11 word
     *
     * word 0 = bit 31-0 = SRC Address(active) = Source address
     * word 1 = bit 31-0 = DST Address(active) = Destination address
     * word 2 = bit 31 = PP = Referance bit
     *          bit 30-16 =reserved
     *          bit 15-0 = COUNT(active) = Count in unit of elements - updated by the dMAX controller during course of transfer
     * word 3 = bit 31-16 reserved
     *          bit 15-0 = COUNT (referance) =Reference Count in unit of elements.
     * word 4 = bit 31-0 = SRC RELOAD ADDRESS0 = Source Address Reload 0
     * word 5 = bit 31-0 = DST RELOAD ADDRESS0 = Destination Address Reload 0
     * word 6 = bit 31-0 = SRC RELOAD ADDRESS1 = Source Address Reload 1
     * word 7 = bit 31-0 = DST RELOAD ADDRESS1 = Destination Address Reload 1
     * word 8-10 = reserved
     *
     *
     * */

    /*4- Transfer entry configured  */

    dMaxTransfer_ptr[0] = (unsigned int)dmaxTxData; // transfer entry 7 word0
    dMaxTransfer_ptr[1] = (unsigned int)dmaxRxData; // transfer entry 7 word1
    dMaxTransfer_ptr[2] = (unsigned int)0x0f; // transfer entry 7 word2 // 16 uzunluk
    dMaxTransfer_ptr[3] = (unsigned int)0x0f; // transfer entry 7 word3
    dMaxTransfer_ptr[4] = (unsigned int)dmaxTxData2; // transfer entry 7 word4
    dMaxTransfer_ptr[5] = (unsigned int)dmaxRxData2; // transfer entry 7 word5
    dMaxTransfer_ptr[6] = (unsigned int)dmaxTxData; // transfer entry 7 word6
    dMaxTransfer_ptr[7] = (unsigned int)dmaxRxData; // transfer entry 7 word7
    
            /* Setting up the DMAX Interrupts */
            
                /* Interrupt Initialization */
                status_int = CSL_intcInit (&intcContext);
                if (status_int != CSL_SOK) {
                    dmax_error_exit ();
                    return status_int;
                }
            
                status_int = CSL_intcDispatcherInit (&intcDispatcherContext);
                if (status_int != CSL_SOK) {
                    dmax_error_exit ();
                    return status_int;
                }
            
            
                /* Install handler for DMAX INT8 Interrupt */
                hIntc = CSL_intcOpen (&intcObj,
                    CSL_INTC_EVENTID_DMAXEVTOUT1, NULL, &status_int);
            
                if ((hIntc == NULL) || (status_int != CSL_SOK)) {
                    status_int = CSL_ESYS_BADHANDLE;
                    dmax_error_exit();
                    return status_int ;
                }
            
            
                isrRec.handler = intr08;
                /* As no arguments assigning zero(0) value */
                isrRec.arg = (void *) 0x0;
                /*Plugging ISR in Event Handler */
                CSL_intcPlugEventHandler (hIntc, &isrRec);
                /* Enabling DMAXEVTSPI Event */
                status_int = CSL_intcEventEnable (CSL_INTC_EVENTID_DMAXEVTOUT1, &eventStat); // SPI ayarlandı
                if (status_int != CSL_SOK) {
                    dmax_error_exit ();
                    return status_int;
                }
                    /* Enabling Non-Maskable Interrupt */
                status_int = CSL_intcEventEnable (CSL_INTC_EVENTID_NMI, &eventStat);
                if (status_int != CSL_SOK) {
                    dmax_error_exit ();
                    return status_int;
                }
            
                /* Enabling Global Enable bit in Control Status Register (CSR) */
                status_int = CSL_intcGlobalEnable (&state);
                if (status_int != CSL_SOK) {
                    dmax_error_exit ();
                    return status_int;
                }
            
                /* Closing INTC Handle */
                status_int = CSL_intcClose (hIntc);
                if (status_int != CSL_SOK) {
                    dmax_error_exit ();
                    return status_int;
                }
            /* Setting up the DMAX Interrupts */
            
            
    /*5- dMAX event enable*/
    dMax_ptr[DEER]= 0x2000; // event 13
    
    
    
    pinmsk = 0x0E01; /* SPI 4-pin with chip select mode */    

    /* 1. Take the SPI0 out of reset */
    spi0_ptr[SPIGCR0] = 0x01;
    /* 2. Configure SPI0 for slave */
    spi0_ptr[SPIGCR1] = 0x00;
    /* 3. Configure SPI0 mode */
    spi0_ptr[SPIPC0] = pinmsk;
    /* 4. Chose SPI0SPIFMT0 */
    spi0_ptr[SPIDAT1] = 0x00000000;
    /* 5. Configure SPI0 for SHIFTDIR=0,POLARITY=1,PHASE=0,
     CHARLEN=16 */
    spi0_ptr[SPIFMT0] = 0x00001410;
    /* 6. SPIDELAY for SPI0 not relevant in slave mode */
    spi0_ptr[SPIDELAY] = 0x00;
    /* 7. Configure SPI0 for error notifications for OVR,BITERR and DESEL */
    //spi0_ptr[SPIINT0] = 0x00000054;
    spi0_ptr[SPIINT0] = 0x00000000;
    spi0_ptr[SPILVL] = 0x00;
    /* 8. Enable SPI0 communication */
    spi0_ptr[SPIGCR1] |= 0x01000000;
    /* 9. Configure SPI0 for dmax servicing of spi events*/
    spi0_ptr[SPIINT0] |= 0x00010000;    
    

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、Akif、

    很遗憾、我们无法再回答有关 C6726的硬件或软件设计问题(根据产品页面上的"有限设计支持"横幅而定):
    https://www.ti.com/product/TMS320C6726B。如果您在 TI 论坛上进行搜索、可能会发现以前客户提交的问题解答会提供一些有用的提示。

    此致、

    Nick