[参考译文] TDA4VM：TDA4VM：PC 上 net.bin 文件的推理结果与板上的结果不一致。

你好、Jin；

感谢您问这个问题。 为了调试问题、我们需要完全复制您所做的操作。 您能否提供以下信息？   

1.您使用的是哪块板?  SK-TDA4VM 或 J721EXSOMXEVM + J721EXCPXEVM

2.您是如何将 onnx 文件导入 bin 文件的,您使用的是哪个软件?

3.您是如何与 PC 程序一起运行.bin 文件的? 哪个软件和哪个版本？

4.您是如何在电路板上运行 net.bin 和 io.bin 的? 我假设您首先构建 RTOS SDK、然后从 SD 卡引导。 SDK 版本为 09_01_00_06、对吗？

谢谢。此致

Wen Li

嗨、Jin

我无法重现您的问题、但出现以下错误：

/home/ht/SDKs/j721e/09_01/ti-processor-sdk-rtos-j721e-evm-09_01_00_06/c7x-mma-tidl/ti_dl/test/PC_dsp_test_dl_algo.out s:infer_config.txt 

Processing config file #0 : infer_config.txt 
Input : dataId=1, name=images_original, elementType 0, scale=1.000000, zero point=0, layout=0
Ouput : dataId=47, name=/model.9/linear/Gemm_output_0, elementType 1, scale=8.864737, zero point=0, layout=0 
      4480644,      4.273 0x7b72d3e00010
worstCaseDelay for Pre-emption is 0.1996270 
Network File Read done
Calling algAlloc
TIDL_initDebugTraceParams Done 

--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum   , Space               , Attribute   , Alignment   , Size(KBytes), BasePtr     
0           , DDR Cacheable       , Persistent  ,  128, 15.25   , 0x00000000
1           , DDR Cacheable       , Persistent  ,  128, 0.64    , 0x00000000
2           , DDR Cacheable       , Scratch     ,  128, 16.00   , 0x00000000
3           , DDR Cacheable       , Scratch     ,  128, 448.00  , 0x00000000
4           , DDR Cacheable       , Scratch     ,  128, 2944.00 , 0x00000000
5           , DDR Cacheable       , Persistent  ,  128, 1714.27 , 0x00000000
6           , DDR Cacheable       , Scratch     ,  128, 11.88   , 0x00000000
7           , DDR Cacheable       , Scratch     ,  128, 961.25  , 0x00000000
8           , DDR Cacheable       , Scratch     ,  128, 7686.12 , 0x00000000
9           , DDR Cacheable       , Scratch     ,  128, 2565.00 , 0x00000000
10          , DDR Cacheable       , Persistent  ,  128, 608.05  , 0x00000000
11          , DDR Cacheable       , Scratch     ,  128, 512.25  , 0x00000000
12          , DDR Cacheable       , Persistent  ,  128, 0.12    , 0x00000000
13          , DDR Cacheable       , Persistent  ,  128, 4375.75 , 0x00000000
14          , DDR Cacheable       , Persistent  ,  128, 0.05    , 0x00000000
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 21858.64
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
      To get the actual TIDL memory requirement make sure to run on EVM with 
      debugTraceLevel = 2

--------------------------------------------
Num,    Space,     SizeinBytes,   SineInMB
   0,    17,        15616,      0.015 0x58bf68684980
   1,    17,          656,      0.001 0x58bf68683980
   2,    17,        16384,      0.016 0x7b72d4400080
   3,    17,       458752,      0.438 0x7b72d4404080
   4,    17,      3014656,      2.875 0x7b72d4474080
   5,    17,      1755412,      1.674 0x7b72d4253080
   6,    17,        12160,      0.012 0x7b72d4754080
   7,    17,       984320,      0.939 0x7b72d4757000
   8,    17,      7870592,      7.506 0x7b72d4847500
   9,    17,      2626560,      2.505 0x7b72d4fc8d80
  10,    17,       622648,      0.594 0x7b7368e41080
  11,    17,       524544,      0.500 0x7b72d524a180
  12,    17,          128,      0.000 0x58bf68688700
  13,    17,      4480772,      4.273 0x7b72d3800080
  14,    17,           50,      0.000 0x58bf68688880
Total External Memory (DDR) Size =     22383250,     21.346 
TIDL init call from ivision API 

--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum   , Space               , Attribute   , Alignment   , Size(KBytes), BasePtr     
0           , DDR Cacheable       , Persistent  ,  128, 15.25   , 0x68684980
1           , DDR Cacheable       , Persistent  ,  128, 0.64    , 0x68683980
2           , DDR Cacheable       , Scratch     ,  128, 16.00   , 0xd4400080
3           , DDR Cacheable       , Scratch     ,  128, 448.00  , 0xd4404080
4           , DDR Cacheable       , Scratch     ,  128, 2944.00 , 0xd4474080
5           , DDR Cacheable       , Persistent  ,  128, 1714.27 , 0xd4253080
6           , DDR Cacheable       , Scratch     ,  128, 11.88   , 0xd4754080
7           , DDR Cacheable       , Scratch     ,  128, 961.25  , 0xd4757000
8           , DDR Cacheable       , Scratch     ,  128, 7686.12 , 0xd4847500
9           , DDR Cacheable       , Scratch     ,  128, 2565.00 , 0xd4fc8d80
10          , DDR Cacheable       , Persistent  ,  128, 608.05  , 0x68e41080
11          , DDR Cacheable       , Scratch     ,  128, 512.25  , 0xd524a180
12          , DDR Cacheable       , Persistent  ,  128, 0.12    , 0x68688700
13          , DDR Cacheable       , Persistent  ,  128, 4375.75 , 0xd3800080
14          , DDR Cacheable       , Persistent  ,  128, 0.05    , 0x68688880
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 21858.64
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
      To get the actual TIDL memory requirement make sure to run on EVM with 
      debugTraceLevel = 2

--------------------------------------------
Algorithm Init failed with error number: -1130
Error at line:   527 : in file /home/dockeruser/psdk_installer_build_top_workarea/scratch_workarea/ti-processor-sdk-rtos-j721e-evm-09_01_00_06/c7x-mma-tidl/ti_dl/test/src/pc_linux/../tidl_tb.c, of function : tidlMultiInstanceTest 
Invalid Error Type!

请确保文件和配置正确。  

此致、

Adam

你(们)好  

来清楚地说明这一点。 好了 控制 与客户沟通时不是 j721e。