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器件型号：PROCESSOR-SDK-AM62X主题中讨论的其他器件：SK-AM62
工具/软件：
MCU SDK 版本：mcu_plus_sdk_am62x_10_01_00_33
测试 EVM：SK-AM62
CCS 版本：12.8.1
我从 C：\ti\mcu_plus_sdk_am62x_10_01_00_33\examples\sdl\dcc\dcc_modes\am62x-sk\r5fss0-0_freertos\导入了示例
然后、我编译了 R5 工程并将生成的 appimage.hs_fs 复制到以下路径中。
--file=sbl_prebuilt/am62x-sk/WZ_Debug/dcc_am62x-sk_r5fss0-0_freertos_ti-arm-clang.appimage.hs_fs -operation=flash -flash-offset=0xA00000
我使用下面的文件刷写测试示例。
e2e.ti.com/.../default_5F00_sbl_5F00_ospi_5F00_hs_5F00_fs_2D00_r5.cfg
下面是来自 SBL UART 的 UART 日志
SYSFW Firmware Version 10.1.8--v10.01.08 (Fiery Fox) SYSFW Firmware revision 0xa SYSFW ABI revision 4.0 [BOOTLOADER_PROFILE] Boot Media : FLASH [BOOTLOADER_PROFILE] Boot Media Clock : 166.667 MHz [BOOTLOADER_PROFILE] Boot Image Size : 175 KB [BOOTLOADER_PROFILE] Cores present : m4f0-0 r5f0-0 [BOOTLOADER PROFILE] System_init : 5491us [BOOTLOADER PROFILE] Board_init : 0us [BOOTLOADER PROFILE] Drivers_open : 301us [BOOTLOADER PROFILE] Board_driversOpen : 1260us [BOOTLOADER PROFILE] Sciclient Get Version : 10202us [BOOTLOADER PROFILE] App_waitForMcuPbist : 8663us [BOOTLOADER PROFILE] App_waitForMcuLbist : 7689us [BOOTLOADER PROFILE] App_loadImages : 3327us [BOOTLOADER PROFILE] App_loadSelfcoreImage : 4041us [BOOTLOADER_PROFILE] SBL Total Time Taken : 40979us Image loading done, switching to application ... Starting MCU-m4f and 2nd stage bootloader SYSFW Firmware Version 10.1.8--v10.01.08 (Fiery Fox) SYSFW Firmware revision 0xa SYSFW ABI revision 4.0 [BOOTLOADER_PROFILE] Boot Media : FLASH [BOOTLOADER_PROFILE] Boot Media Clock : 166.667 MHz [BOOTLOADER_PROFILE] Boot Image Size : 408 KB [BOOTLOADER_PROFILE] Cores present : hsm-m4f0-0 r5f0-0 a530-0 [BOOTLOADER PROFILE] System_init : 2789us [BOOTLOADER PROFILE] Board_init : 1us [BOOTLOADER PROFILE] Drivers_open : 386us [BOOTLOADER PROFILE] Board_driversOpen : 139us [BOOTLOADER PROFILE] Sciclient Get Version : 10225us [BOOTLOADER PROFILE] App_loadImages : 2690us [BOOTLOADER PROFILE] App_loadSelfcoreImage : 5349us [BOOTLOADER PROFILE] App_loadA53Images : 4116us [BOOTLOADER_PROFILE] SBL Total Time Taken : 25698us Image loading done, switching to application ... Starting RTOS/Baremetal applications NOTICE: BL31: v2.11.0(release):REL.MCUSDK.K3.10.01.00.33 NOTICE: BL31: Built : 04:57:09, Dec 19 2024
下面是来自 DM UART 的 UART 日志
[15:15:23.569]收←◆Sciserver Testapp Built On: Dec 19 2024 04:51:59 Sciserver Version: v2024.12.0.0-REL.MCUSDK.K3.10.01.00.33+ RM_PM_HAL Version: v10.01.08 Starting Sciserver..... PASSED DCC Example Test Application DCC_Test_init: Init WKUP ESM complete USECASE: 0 Source clock: HFOSC0 Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
问题：如何运行此 DCC R5 示例？
我可以成功运行 DCC M4F C：\ti\mcu_plus_sdk_am62x_10_01_00_33\examples\sdl\dcc\dcc_modes\am62x-sk\m4fss0-0_nortos\
下面是日志。
但它无法在 DM 内核中成功运行
[BLAZAR_Cortex_M4F_0] DCC Example Test Application DCC_Test_init: Init WKUP ESM complete USECASE: 0 Source clock: HFOSC0 Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt SDL DCC EXAMPLE TEST: DCC Generated Error interrupt SDL DCC EXAMPLE TEST: Indicating clock drift/change UC-0 Completed Successfully USECASE: 1 Source clock: HFOSC0 Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: DCC Generated completion interrupt SDL DCC EXAMPLE TEST: No Clock Drift was observed UC-1 Completed Successfully USECASE: 2 Source clock: HFOSC0 Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and running for some time UC-2 Completed Successfully USECASE: 3 Source clock: RC OSC Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: DCC Generated completion interrupt SDL DCC EXAMPLE TEST: No Clock Drift was observed UC-3 Completed Successfully USECASE: 4 Source clock: RC OSC Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt SDL DCC EXAMPLE TEST: DCC Generated Error interrupt SDL DCC EXAMPLE TEST: Indicating clock drift/change UC-4 Completed Successfully USECASE: 5 Source clock: RC OSC Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt SDL DCC EXAMPLE TEST: DCC Generated Error interrupt SDL DCC EXAMPLE TEST: Indicating clock drift/change UC-5 Completed Successfully USECASE: 6 Source clock: RC OSC Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt SDL DCC EXAMPLE TEST: DCC Generated Error interrupt SDL DCC EXAMPLE TEST: Indicating clock drift/change UC-6 Completed Successfully USECASE: 7 Source clock: HFOSC0 Test clock: MAIN_SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt SDL DCC EXAMPLE TEST: DCC Generated Error interrupt SDL DCC EXAMPLE TEST: Indicating clock drift/change UC-7 Completed Successfully USECASE: 8 Source clock: RC OSC Test clock: MAIN_SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and running for some time UC-8 Completed Successfully USECASE: 9 Source clock: HFOSC0 Test clock: FICLK SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and running for some time UC-9 Completed Successfully USECASE: 10 Source clock: FICLK Test clock: MAIN_SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and running for some time UC-10 Completed Successfully All tests have passed.
