[参考译文] AM6442：AM243x：PRU IEP SYNC0 信号

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Other Parts Discussed in Thread: SK-AM64B

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https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1567136/am6442-am243x-pru-iep-sync0-signal

器件型号：AM6442
Thread 中讨论的其他器件：SK-AM64B

工具/软件：MCU+ SDK

我想使用 IEP 计时器向 TSR（时序同步路由器）提供同步脉冲。 CMP0 用于复位计数器、CMP4 用于调试目的、CMP1 配置为在 Sync0 输出端生成脉冲。我已配置 TSR 将时序信号路由到 SK-AM64B 上的引脚接头、从而允许我在示波器上观察它。该配置是使用 R5F 内核设置的。

但是、我没有收到任何信号。任务由 CMP4 事件触发、因此我相信 IEP 正在运行。可能缺少配置？是否需要手动复位 CMP1 状态？

// output: 24: PINFUNCTION_SYNC0_OUTout_SYNC0_OUT_IN_0
// input: 25: PRU_ICSSG0_PR1_EDC0_SYNC0_OUT_0
CSL_REG32_WR(CSL_TIMESYNC_EVENT_INTROUTER0_CFG_BASE + ((24 * 4) + 4), (1 << 16) + 25);

; CCS/makefile specific settings
    .retain     ; Required for building .out with assembly file
    .retainrefs ; Required for building .out with assembly file

    .global     main
    .sect       ".text"

;************************************* includes *************************************
; icss_constant_defines.inc: Defines symbols corresponding to Constant Table Entries
    .include "icss_constant_defines.inc"
    .include "icss_tm_macros.inc"
    .include "icss_iep_regs.inc"

    .include "pru.h"

;********************************************* defines ******************************************
;SPAD Bank for context storage
BANK_TRG            .set BANK1

;********
;* MAIN *
;********

main:

init:
;----------------------------------------------------------------------------
;   Clear the register space
;   Before beginning with the application, make sure all the registers are set
;   to 0. PRU has 32 - 4 byte registers: R0 to R31, with R30 and R31 being special
;   registers for output and input respectively.
;----------------------------------------------------------------------------

; Give the starting address and number of bytes to clear.
    zero	&r0, 120

    ; Disable Task Manager
    TSEN 0   
    ; Clear Task Manager status which is sticky after debug halt
    ; activates all tasks
    LDI     TEMP_REG0.w0, 0x0fff
    SBCO    &TEMP_REG0.w0, ICSS_TM_CFG_CONST, 0, 2
    XIN     TM_YIELD_XID, &R0.b3,1
    LDI     TEMP_REG0.w0, 0
    SBCO    &TEMP_REG0.w0, ICSS_TM_CFG_CONST, 0, 2

;----------------------------------------------------------------------------
;   Constant Table Entries Configuration
;   Sample code to configure Constant Table Entries.
;----------------------------------------------------------------------------

; Configure the Constant Table entry C28 to point to start of shared memory
; PRU_ICSSG Shared RAM (local-C28) : 00nn_nn00h, nnnn = c28_pointer[15:0]
; By default it is set to 0000_0000h so it will point to DMEM0 address
    LDI     TEMP_REG0, 0x0100
    SBCO    &TEMP_REG0, ICSS_PRU_CTRL_CONST, 0x28, 2


INIT_PROGRAM:
    ; init Scratchpad
    JAL     RET_ADDR_REG, SPAD_INIT
    ;Initialize Task Manager
    JAL     RET_ADDR_REG, TM_INIT
    ;Initialize IEP0
    JAL     RET_ADDR_REG, IEP0_INIT

    ; Start IEP
    LBCO    &TEMP_REG0.b0, ICSS_IEP_CONST, ICSS_IEP_GLOBAL_CFG_REG, 1
    SET     TEMP_REG0, TEMP_REG0, CNT_ENABLE_BN ; ICSSG_IEP_GLOBAL_CFG_REG:CNT_ENABLE=1
    SBCO    &TEMP_REG0.b0, ICSS_IEP_CONST, ICSS_IEP_GLOBAL_CFG_REG, 1

    TSEN 1
    
    ...
    
    ;      
; Initialize IEP0.
;
IEP0_INIT:
    ; Disable IEP0 counter
    LBCO    &TEMP_REG0.b0, ICSS_IEP_CONST, ICSS_IEP_GLOBAL_CFG_REG, 1
    CLR     TEMP_REG0, TEMP_REG0, CNT_ENABLE_BN
    SBCO    &TEMP_REG0.b0, ICSS_IEP_CONST, ICSS_IEP_GLOBAL_CFG_REG, 1

    ; Set IEP0 counter to zero
    LDI     TEMP_REG0, 0
    SBCO    &TEMP_REG0, ICSS_IEP_CONST, ICSS_IEP_COUNT_REG, 4
    SBCO    &TEMP_REG0, ICSS_IEP_CONST, ICSS_IEP_COUNT_REG + 4, 4  

    ; Clear CMP4, CMP1 and CMP0 event
    LDI     TEMP_REG0.b0, 0x13
    SBCO    &TEMP_REG0.b0, ICSS_IEP_CONST, ICSS_IEP_CMP_STATUS_REG, 1
    
    ; Write IEP0 default increment
    LBCO    &TEMP_REG0.b0, ICSS_IEP_CONST, ICSS_IEP_GLOBAL_CFG_REG, 1
    AND     TEMP_REG0.b0, TEMP_REG0.b0, 0x0F
    OR      TEMP_REG0.b0, TEMP_REG0.b0, IEP_DEFAULT_INC<<DEFAULT_INC_BN
    SBCO    &TEMP_REG0.b0, ICSS_IEP_CONST, ICSS_IEP_GLOBAL_CFG_REG, 1
    
    ;
    ; set CMPs
    ;
    ; Set CMP0 to 100000 for 2kHz period
    LDI32   TEMP_REG0, 10000
    SBCO    &TEMP_REG0, ICSS_IEP_CONST, ICSS_IEP_CMP0_REG, 4
    LDI     TEMP_REG0, 0
    SBCO    &TEMP_REG0, ICSS_IEP_CONST, ICSS_IEP_CMP0_REG + 4, 4

    ; Enable CMP0 and CMP0_RST_CNT_EN
    LBCO    &TEMP_REG0.b0, ICSS_IEP_CONST, ICSS_IEP_CMP_CFG_REG, 1
    SET     TEMP_REG0, TEMP_REG0, 0      ; CMP0_RST_CNT_EN
    SET     TEMP_REG0, TEMP_REG0, 1      ; CMP_EN[1] => CMP1 enabled
    SBCO    &TEMP_REG0.b0, ICSS_IEP_CONST, ICSS_IEP_CMP_CFG_REG, 1
    
    ; Set CMP1 to 1
    LDI     TEMP_REG0, 1
    SBCO    &TEMP_REG0, ICSS_IEP_CONST, ICSS_IEP_CMP1_REG, 4
    LDI     TEMP_REG0, 0
    SBCO    &TEMP_REG0, ICSS_IEP_CONST, ICSS_IEP_CMP1_REG + 4, 4

    ; Enable CMP1
    LBCO    &TEMP_REG0.b0, ICSS_IEP_CONST, ICSS_IEP_CMP_CFG_REG, 1
    SET     TEMP_REG0, TEMP_REG0, 2  ; CMP_EN[2] => CMP1 enabled
    SBCO    &TEMP_REG0.b0, ICSS_IEP_CONST, ICSS_IEP_CMP_CFG_REG, 1

    ; Set CMP4 to 1
    LDI     TEMP_REG0, 1000
    SBCO    &TEMP_REG0, ICSS_IEP_CONST, ICSS_IEP_CMP4_REG, 4
    LDI     TEMP_REG0, 0
    SBCO    &TEMP_REG0, ICSS_IEP_CONST, ICSS_IEP_CMP4_REG + 4, 4

    ; Enable CMP4
    LBCO    &TEMP_REG0.b0, ICSS_IEP_CONST, ICSS_IEP_CMP_CFG_REG, 1  ; TR0 <- Byte0 ICSSG_CMP_CFG_REG
    SET     TEMP_REG0.t5    ; CMP_EN[5]=1 => CMP4 enabled
    SBCO    &TEMP_REG0.b0, ICSS_IEP_CONST, ICSS_IEP_CMP_CFG_REG, 1  ; TR0 -> ICSSG_CMP_CFG_REG Byte0

    ;
    ; Configure SYNC0
    ;
    ; Enable SYNC0, cyclic mode, no ACK
    LDI     TEMP_REG0, 3   ; Bit 1: SYNC0_EN and Bit 0: SYNC_EN
    SBCO    &TEMP_REG0, ICSS_IEP0_1_CONST, ICSS_IEP_SYNC_CTRL_REG - 0x100, 4

    ; Set SYNC0 start to 0
    LDI     TEMP_REG0, 0
    SBCO    &TEMP_REG0, ICSS_IEP0_1_CONST, ICSS_IEP_SYNC_START_REG - 0x100, 4

    ; Set SYNC0 pulse width to 1000 (5µs)
    LDI     TEMP_REG0, 1000
    SBCO    &TEMP_REG0, ICSS_IEP0_1_CONST, ICSS_IEP_SYNC_PWIDTH_REG - 0x100, 4

    JMP     RET_ADDR_REG

3 个月前