[参考译文] AM62A7-Q1：AM335x 将 Linux 控制台从 UART0 更改为 UART2

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https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1596785/am62a7-q1-am335x-change-linux-console-from-uart0-to-uart2

器件型号： AM62A7-Q1

我引入了一个定制电路板。我们将调试控制台从 UART0 移动到 UART2。我能够让 uboot 使用 UART2、但不知道如何设置 Linux 源以使用 UART2。有什么建议吗？

在我们基于 am62a 的定制硬件板中、我的调试 UART 与 soc 的 uart2 (U22 和 U21) 连接、我尝试通过 11.01 SDK 反映引导加载程序源代码内 k3-am62a7-sk.dts 文件中的更改。我附上 DTS 以供您参考。

@@ -21,7 +21,7 @@
 	aliases {
 		serial0 = &wkup_uart0;
 		serial1 = &mcu_uart0;
-		serial2 = &main_uart0;
+		serial2 = &main_uart2;
 		serial3 = &main_uart1;
 		mmc0 = &sdhci0;
 		mmc1 = &sdhci1;
@@ -317,6 +317,12 @@
 			AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */
 		>;
 	};
+	main_uart2_pins_default: main-uart1-default-pins {
+		pinctrl-single,pins = <
+			AM62AX_IOPAD(0x0b8, PIN_INPUT, 4) /* (U22) VOUT0_DATA0 @arjun*/
+			AM62AX_IOPAD(0x0bc, PIN_OUTPUT, 4) /* (U21) VOUT0_DATA1 */
+		>;
+	};
 
 	main_i2c0_pins_default: main-i2c0-default-pins {
 		pinctrl-single,pins = <
@@ -714,6 +720,13 @@
 	status = "reserved";
 };
 
+&main_uart2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart2_pins_default>;
+};
+
 /* main_timer2 is used by C7x DSP */
 &main_timer2 {
 	status = "reserved";

我也尝试过

diff --git a/arch/arm/mach-k3/r5/am62ax/dev-data.c b/arch/arm/mach-k3/r5/am62ax/dev-data.c
index 6cced9efd08a..55a9d24b6c43 100644
--- a/arch/arm/mach-k3/r5/am62ax/dev-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/dev-data.c
@@ -54,7 +54,7 @@ static struct ti_dev soc_dev_list[] = {
        PSC_DEV(75, &soc_lpsc_list[7]),
        PSC_DEV(36, &soc_lpsc_list[8]),
        PSC_DEV(102, &soc_lpsc_list[8]),
-       PSC_DEV(146, &soc_lpsc_list[8]),
+       PSC_DEV(153, &soc_lpsc_list[8]),
        PSC_DEV(166, &soc_lpsc_list[9]),
        PSC_DEV(135, &soc_lpsc_list[10]),
        PSC_DEV(170, &soc_lpsc_list[11]),

和

diff --git a/arch/arm/mach-k3/r5/am62ax/clk-data.c b/arch/arm/mach-k3/r5/am62ax/clk-data.c
index d950b35e..bddec537 100644
--- a/arch/arm/mach-k3/r5/am62ax/clk-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/clk-data.c
@@ -114,8 +114,8 @@ static const char * const wkup_clksel_out0_parents[] = {
        "hsdiv4_16fft_mcu_0_hsdivout0_clk",
 };

-static const char * const main_usart0_fclk_sel_out0_parents[] = {
-       "usart_programmable_clock_divider_out0",
+static const char * const main_usart2_fclk_sel_out0_parents[] = {
+       "usart_programmable_clock_divider_out2",
        "hsdiv4_16fft_main_1_hsdivout1_clk",
 };

@@ -195,7 +195,7 @@ static const struct clk_data clk_list[] = {
        CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
        CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0),
        CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
-       CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
+       CLK_MUX("main_usart2_fclk_sel_out0", main_usart2_fclk_sel_out0_parents, 2, 0x108288, 0, 1, 0),
        CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
        CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
        CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
@@ -266,10 +266,10 @@ static const struct dev_clk soc_dev_clk_data[] = {
        DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
        DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
        DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
-       DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
-       DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
-       DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
-       DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+       DEV_CLK(153, 0, "main_usart2_fclk_sel_out0"),
+       DEV_CLK(153, 1, "usart_programmable_clock_divider_out2"),
+       DEV_CLK(153, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
+       DEV_CLK(153, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(157, 20, "clkout0_ctrl_out0"),
        DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
        DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),

3 个月前