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[参考译文] PROCESSOR-SDK-J721E:SDK 7.00和 SDK 7.01之间的 board_PLL.c 差异

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https://e2e.ti.com/support/processors-group/processors/f/processors-forum/975616/processor-sdk-j721e-difference-in-board_pll-c-between-sdk-7-00-and-sdk-7-01

器件型号:PROCESSOR-SDK-J721E

您好!

我注意  到 SDK 7.00和 SDK 7.01在 pdk_jacinto_07_01_00_45/packages/ti/board/src/j721e_evm/board_pll.c 中的以下差异:

TISCI_DEV_MCU_ADC1_ADC_CLK_PART_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK -> TISCI_DEV_MCU_ADC12_16FFC0_ADC_CLK_PART_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK

TISCI_DEV_MCU_FSS0_HYPERBUS1P0_HPB_CLKX1_CLK -> TISCI_DEV_MCU_FSS0_HYPERBUS1P0_HPB_CLKX2_CLK

为什么这些时钟设置发生变化?

在 SDK 7.01中、删除了以下条目:

TISCI_DEV_PCIE0、TISCI_DEV_UFS0、TISCI_DEV_USB0、TISCI_DEV_PCIE0、TISCI_DEV_SERDES_16G0、 TISCI_DEV_ENCODER0、TISCI_DEV_DECODER0。

是不是因为我们不希望这些外设在启动后"打开"?