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[参考译文] TDA4VM:mcu1_0 (mcusw)和 MPU (vision_apps)之间的 Cdddipc

Guru**** 2531480 points
Other Parts Discussed in Thread: SYSBIOS

请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1012222/tda4vm-cddipc-between-mcu1_0-mcusw-and-mpu-vision_apps

器件型号:TDA4VM
Thread 中讨论的其他器件:SYSBIOS

软件 版本:  RTOS-07-03-00-07   QNX-07-03-00

引导模式:  SPL (SD 卡)

参考  

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1008492/faq-tda4vm-cddipc-between-mcu1_0-mcusw-and-mcu2_1-vision_apps-based-on-sdk-v7-3

MCU1_0 (运行 AUTOSAR)和 MCU2_1 (运行视觉应用)之间的 IPC 已实现。

我们的项目需要在 mcu1_0 (mcusw)和 MPU (vision_apps)之间实现 Cddipc,这是否可以实现?  

我们已根据  参考 示例实现修改了 mcu1_0 (mcusw)和 MPU (vision_apps)的代码。

但启动期间发生异常。 Blow 是完整的错误日志。

U-Boot SPL 2020.01-svn2648 (Jun 18 2021 - 13:47:28 +0800)
SYSFW ABI: 3.1 (firmware rev 0x0015 '21.1.1--v2021.01a (Terrific Lla')
Reading on-board EEPROM at 0x50 failed -1
Trying to boot from MMC2
Loading Environment from MMC... *** Warning - No MMC card found, using default environment

Starting ATF on ARM64 core...

NOTICE:  BL31: v2.4(release):07.03.00.005-dirty
NOTICE:  BL31: Built : 00:15:40, Apr 10 2021

U-Boot SPL 2020.01-svn2648 (Jun 18 2021 - 18:12:17 +0800)
SYSFW ABI: 3.1 (firmware rev 0x0015 '21.1.1--v2021.01a (Terrific Lla')
Reading on-board EEPROM at 0x50 failed -1
Trying to boot from MMC2
i2c_write: error waiting for data ACK (status=0x116)
Error reading output register


U-Boot 2020.01-svn2648 (Jun 18 2021 - 18:12:17 +0800)

SoC:   J721E SR2.0
Model: Texas Instruments K3 J721E SoC
Reading on-board EEPROM at 0x50 failed -1
Board: J721EX-PM1-SOM rev E2
DRAM:  4 GiB
not found for dev hbmc-mux
Flash: 0 Bytes
MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
Loading Environment from MMC... OK
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
Reading on-board EEPROM at 0x50 failed -1
Net:   Could not get PHY for ethernet@46000000: addr 0
phy_connect() failed
No ethernet found.

Hit any key to stop autoboot:  0
i2c_write: error waiting for data ACK (status=0x116)
Error reading output register
switch to partitions #0, OK
mmc1 is current device
i2c_write: error waiting for data ACK (status=0x116)
Error reading output register
SD/MMC found on device 1
526 bytes read in 4 ms (127.9 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc1 ...
Running uenvcmd ...
Core 1 is already in use. No rproc commands work
Core 2 is already in use. No rproc commands work
5339448 bytes read in 224 ms (22.7 MiB/s)
Load Remote Processor 2 with data@addr=0x82000000 5339448 bytes: Success!
1968096 bytes read in 84 ms (22.3 MiB/s)
Load Remote Processor 3 with data@addr=0x82000000 1968096 bytes: Success!
1579120 bytes read in 65 ms (23.2 MiB/s)
Load Remote Processor 6 with data@addr=0x82000000 1579120 bytes: Success!
1579120 bytes read in 64 ms (23.5 MiB/s)
Load Remote Processor 7 with data@addr=0x82000000 1579120 bytes: Success!
10268600 bytes read in 171 ms (57.3 MiB/s)
Load Remote Processor 8 with data@addr=0x82000000 10268600 bytes: Success!
8176932 bytes read in 342 ms (22.8 MiB/s)
## Starting application at 0x80080000 ...
MMU: 16-bit ASID 44-bit PA TCR_EL1=b5183519
cpu0: MPIDR=80000000
cpu0: MIDR=411fd080 Cortex-A72 r1p0
cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu0: L1 Icache 48K linesz=64 set/way=256/3
cpu0: L1 Dcache 32K linesz=64 set/way=256/2
cpu0: L2 Unified 1024K linesz=64 set/way=1024/16
Display set to R5
Loading IFS...decompressing...done
cpu1: MPIDR=80000001
cpu1: MIDR=411fd080 Cortex-A72 r1p0
cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu1: L1 Icache 48K linesz=64 set/way=256/3
cpu1: L1 Dcache 32K linesz=64 set/way=256/2
cpu1: L2 Unified 1024K linesz=64 set/way=1024/16

System page at phys:0000000080011000 user:ffffff8040254000 kern:ffffff8040251000
Starting next program at vffffff8060086e10
All ClockCycles offsets within tolerance
*******************************************************
*******************NRA ver0.51 base*********************
****RTOS-07-03-00-07 QNX-07-03-00 LINUX-07-03-00-05****
*******************************************************
Starting random service ...
start serial driver
Starting MMC/SD memory card driver... eMMC
Starting MMC/SD memory card driver... SD
Starting XHCI driver on USB3SS0 and USB3SS1
Path=0 - am65x
 target=0 lun=0     Direct-Access(0) - SDMMC: 032GB4 Rev: 0.4
Setting environment variables...
done..
Mounting the sd ..
Looking for user script to run: /ti_fs/scripts/user.sh
Running user script...
user.sh called...
Setting additional environment variables...
Starting tisci-mgr..
Starting shmemallocator..
Starting tiipc-mgr..
Mailbox_plugInterrupt: interrupt Number 489, arg 0x435ED018
Mailbox_plugInterrupt: interrupt Number 490, arg 0x435ED1B8
Mailbox_plugInterrupt: interrupt Number 491, arg 0x435ED358
Mailbox_plugInterrupt: interrupt Number 492, arg 0x435ED4F8
Mailbox_plugInterrupt: interrupt Number 493, arg 0x435ED698

Process 57360 (tiipc-mgr) terminated SIGSEGV code=1 fltno=11 ip=00000031435a310c(/ti_fs/tibin/tiipc-mgr@lose+0x0000000000004dac) mapaddr=000000000001ef=0000002400000184
Memory fault (core dumped)
Starting tiudma-mgr..
Start screen..
screen started with dss_on_r5 configuration..
done...
J7EVM@QNX:/#
 

正在启动 tiipc-mgr..
Mailbox_plugInterrupt:中断号489、ARG 0x435ED018
Mailbox_plugInterrupt:中断号490、ARG 0x435ED1B8
Mailbox_plugInterrupt:中断号491、ARG 0x435ED358
Mailbox_plugInterrupt:中断号492、ARG 0x435ED4F8
Mailbox_plugInterrupt:中断号493、ARG 0x435ED698

Process 57360 (tiipc-mgr) terminated SIGSEGV code=1 fltno=11 IP=00000031435a310c (/ti_fs/tibin/tiipc-mgr@lus+0x00000000000000004dac) mapaddr=00000001ef=0000002400000184
存储器故障(转储内核)

 mcu1_0 (mcusw)和 MPU (vision_apps)之间 cddipc 的 vring_base_address 设置为0xB0000000,对吗?

如何解决 核心转储问题?

我们的项目基于 TROS+QNX (版本7.3)。

谢谢!  

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    大家好、 :  

    可实现 MCU1_0 (cddipc)和 MPU (QNX、视觉应用)之间的 IPC。

    MPU (QNX)的 IPC 与 MPU (Linux)上实现的 IPC 不同、而 QNX 的 IPC 与其他主域内核(RTOS)上实现的 IPC 相似。

    我认为无需从 MPU (QNX 侧)进行许多更改。

    对于 MCU1_0、请参阅示例 CDD_IPC_PROFILE_APP ($mcusw/mcus_demos/profile/cddIpc)。

    为了更好地了解您的环境、请告诉我:

    1. IPC 是否在 MCU1_0 (mcusw、cddipc)和其他运行 TI-RTOS (视觉应用)的主域内核之间工作?
    2. IPC 是否在 A72 (QNX、VISION 应用程序)和其他运行 TI-RTOS (VISION 应用程序)的主域内核之间工作?  

    如果执行上述两项操作、那么在 A72 (QNX、VISION 应用程序)和 MCU1_0 (mcusw、cddipc)之间处理 IPC 将是一个良好的起点。

    谢谢。

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    尊敬的 Peter:

     Q1:IPC 是否在 MCU1_0 (mcusw、cddipc)和其他运行 TI-RTOS (视觉应用)的主域内核之间工作?

    A1:我不知道 IPC  IPC 是否在 MCU1_0 (mcusw、cddipc)和其他运行 TI-RTOS (VISION 应用)的主域内核之间工作。

    如何测试它?   

    Q2:IPC 是否在 A72 (QNX、VISION 应用程序)和其他运行 TI-RTOS (VISION 应用程序)的主域内核之间工作?  

    A2:IPC  在 A72 (QNX、VISION 应用程序)和其他主域内核之间运行良好。  

    这可以通过运行./vx_app_arm_ipc.out 来验证。  

     

    正如您所说、对于  MCU1_0、我们引用了示例 CDD_IPC_PROFILE_APP ($mcusw/mcus_demos/profile/cddIpc)。

    ,我们还提到 $mcusw/mcus_demos/inter_core_comm/ipc_remote、  代码移植到  MPU (QNX、VISION 应用程序)。

    编译、生成一个新的*。out 文件、如 vx_app_arm_ipc.out。

    通过执行此操作、我们认为 MCU1_0 (cddipc)和 MPU (QNX、视觉应用)可以使用 cddipc 相互通信。

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    大家好、 :  

    如上所述、MPU1_0 (A72、QNX)和其他主域内核之间的 IPC 正常工作。

    因此、我们不需要将 IPC_REMOTE 示例集成到 QNX 中。 QNX 侧的 IPC 已初始化。

    A72 (QNX)端需要为 MPU1_0启用 MCU1_0 IPC。

    基于上述内容、您是否会根据您的 QNX 环境进行一次实验:

    1.在$vision_apps/vision_apps_build_flags.mk 中启用 build_cpu_MCU1_0

    2.在 $vision_apps/apps/basic_demos/app_tirtos/common/app_cfg.h 中启用 ENABLE_IPC_MCU1_0

    在本实验中、除了上述更改之外、不要更改 SDK 中的其他文件。

    然后重建 vision_apps、并在 QNX 控制台中运行 vision_apps_init.sh。

    从控制台输出中、我们预计会看到一些 MCU1_0日志(IPC ECO 测试结果)。

    请共享控制台输出。

    谢谢。

      

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    1.在$vision_apps/vision_apps_build_flags.mk 中启用 build_cpu_MCU1_0

    2.在 $vision_apps/apps/basic_demos/app_tirtos/common/app_cfg.h 中启用 ENABLE_IPC_MCU1_0

    3.cd vision_apps,make SDK

    4.CP /mcusw/binary/base_project_mcu1/bin/j721e_evm/base_project_mcu1_mcu1_0_debug.xer5f 美元       $/vision_apps/out/J7/R5F/SYSBIOS/release/vx_app_tirtos_QNX_mcu1_0.out

    5.使 QNX_FS_CREATE _SD、使 QNX_FS_INSTALL_SD。

    6. cd vision_apps,实现 uboot。   

    7. CP $/PSDKLA/board-support/u-boot-2020.01 +gitAUTOINC+2781231a33-g2781231a33/j721e-ARM64-QNX/tispl.bin /media/($user)/boot/-f

    U-Boot SPL 2020.01-svn2210 (Apr 19 2021 - 14:47:42 +0800)
    SYSFW ABI: 3.1 (firmware rev 0x0015 '21.1.1--v2021.01a (Terrific Lla')
    Reading on-board EEPROM at 0x50 failed -1
    
     do_board_detect!
    Trying to boot from MMC2
    Loading Environment from MMC... *** Warning - No MMC card found, using default environment
    
    Starting ATF on ARM64 core...
    
    NOTICE:  BL31: v2.4(release):07.03.00.005-dirty
    NOTICE:  BL31: Built : 00:15:40, Apr 10 2021
    
    U-Boot SPL 2020.01-svn2648 (Jun 25 2021 - 10:24:59 +0800)
    SYSFW ABI: 3.1 (firmware rev 0x0015 '21.1.1--v2021.01a (Terrific Lla')
    Reading on-board EEPROM at 0x50 failed -1
    Trying to boot from MMC2
    i2c_write: error waiting for data ACK (status=0x116)
    Error reading output register
    
    
    U-Boot 2020.01-svn2648 (Jun 25 2021 - 10:24:59 +0800)
    
    SoC:   J721E SR2.0
    Model: Texas Instruments K3 J721E SoC
    Reading on-board EEPROM at 0x50 failed -1
    Board: J721EX-PM1-SOM rev E2
    DRAM:  4 GiB
    not found for dev hbmc-mux
    Flash: 0 Bytes
    MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
    Loading Environment from MMC... OK
    In:    serial@2800000
    Out:   serial@2800000
    Err:   serial@2800000
    Reading on-board EEPROM at 0x50 failed -1
    Net:   Could not get PHY for ethernet@46000000: addr 0
    phy_connect() failed
    No ethernet found.
    
    Hit any key to stop autoboot:  0
    i2c_write: error waiting for data ACK (status=0x116)
    Error reading output register
    switch to partitions #0, OK
    mmc1 is current device
    i2c_write: error waiting for data ACK (status=0x116)
    Error reading output register
    SD/MMC found on device 1
    526 bytes read in 3 ms (170.9 KiB/s)
    Loaded env from uEnv.txt
    Importing environment from mmc1 ...
    Running uenvcmd ...
    Core 1 is already in use. No rproc commands work
    Core 2 is already in use. No rproc commands work
    5339448 bytes read in 224 ms (22.7 MiB/s)
    Load Remote Processor 2 with data@addr=0x82000000 5339448 bytes: Success!
    1968096 bytes read in 85 ms (22.1 MiB/s)
    Load Remote Processor 3 with data@addr=0x82000000 1968096 bytes: Success!
    1579120 bytes read in 64 ms (23.5 MiB/s)
    Load Remote Processor 6 with data@addr=0x82000000 1579120 bytes: Success!
    1579120 bytes read in 65 ms (23.2 MiB/s)
    Load Remote Processor 7 with data@addr=0x82000000 1579120 bytes: Success!
    10268600 bytes read in 170 ms (57.6 MiB/s)
    Load Remote Processor 8 with data@addr=0x82000000 10268600 bytes: Success!
    8176932 bytes read in 342 ms (22.8 MiB/s)
    ## Starting application at 0x80080000 ...
    MMU: 16-bit ASID 44-bit PA TCR_EL1=b5183519
    cpu0: MPIDR=80000000
    cpu0: MIDR=411fd080 Cortex-A72 r1p0
    cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
    cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
    cpu0: L1 Icache 48K linesz=64 set/way=256/3
    cpu0: L1 Dcache 32K linesz=64 set/way=256/2
    cpu0: L2 Unified 1024K linesz=64 set/way=1024/16
    Display set to R5
    Loading IFS...decompressing...done
    cpu1: MPIDR=80000001
    cpu1: MIDR=411fd080 Cortex-A72 r1p0
    cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
    cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
    cpu1: L1 Icache 48K linesz=64 set/way=256/3
    cpu1: L1 Dcache 32K linesz=64 set/way=256/2
    cpu1: L2 Unified 1024K linesz=64 set/way=1024/16
    
    System page at phys:0000000080011000 user:ffffff8040254000 kern:ffffff8040251000
    Starting next program at vffffff8060086e10
    All ClockCycles offsets within tolerance
    *******************************************************
    *******************NRA ver0.51 base*********************
    ****RTOS-07-03-00-07 QNX-07-03-00 LINUX-07-03-00-05****
    *******************************************************
    Starting random service ...
    start serial driver
    Starting MMC/SD memory card driver... eMMC
    Starting MMC/SD memory card driver... SD
    Starting XHCI driver on USB3SS0 and USB3SS1
    Path=0 - am65x
     target=0 lun=0     Direct-Access(0) - SDMMC: 032GB4 Rev: 0.4
    Setting environment variables...
    done..
    Mounting the sd ..
    Looking for user script to run: /ti_fs/scripts/user.sh
    Running user script...
    user.sh called...
    Setting additional environment variables...
    Starting tisci-mgr..
    Starting shmemallocator..
    Starting tiipc-mgr..
    Mailbox_plugInterrupt: interrupt Number 489, arg 0xF19D3018
    Mailbox_plugInterrupt: interrupt Number 490, arg 0xF19D31B8
    Mailbox_plugInterrupt: interrupt Number 491, arg 0xF19D3358
    Mailbox_plugInterrupt: interrupt Number 492, arg 0xF19D34F8
    Mailbox_plugInterrupt: interrupt Number 493, arg 0xF19D3698
    Starting TI IPC Resmgr
    Starting tiudma-mgr..
    Start screen..
    screen started with dss_on_r5 configuration..
    done...
    J7EVM@QNX:/#
    Process 57360 (tiipc-mgr) terminated SIGSEGV code=1 fltno=11 ip=00000018f198915c(/ti_fs/tibin/tiipc-mgr@lose+0x0000000000004dfc) mapaddr=000000000001115c. ref=0000002e00000184
    
    J7EVM@QNX:/#
    J7EVM@QNX:/# cd ti_fs/vision_apps/
    J7EVM@QNX:/ti_fs/vision_apps# ls
    app_avp.cfg                            run_app_tidl_seg_cam.sh
    app_avp2.cfg                           run_app_tidl_vl.sh
    app_avp3.cfg                           run_ptk_demo.sh
    app_avp4.cfg                           uEnv.txt
    app_c7x.cfg                            vision_apps_init.sh
    app_dof.cfg                            vx_app_arm_fd_exchange_consumer.out
    app_encode.cfg                         vx_app_arm_fd_exchange_producer.out
    app_multi_cam.cfg                      vx_app_arm_ipc.out
    app_oc.cfg                             vx_app_arm_ipc_1.out
    app_oc_16bit.cfg                       vx_app_arm_mem.out
    app_od.cfg                             vx_app_arm_opengl_mosaic.out
    app_od_cam.cfg                         vx_app_arm_remote_log.out
    app_pcie_video_sink.cfg                vx_app_c7x_kernel.out
    app_pcie_video_source.cfg              vx_app_camera_switch.out
    app_seg.cfg                            vx_app_conformance.out
    app_seg_16bit.cfg                      vx_app_csitx.out
    app_seg_cam.cfg                        vx_app_dense_optical_flow.out
    app_sfm.cfg                            vx_app_dvt.out
    app_single_cam.cfg                     vx_app_encode.out
    app_srv.cfg                            vx_app_heap_stats.out
    app_srv_avp_cfg                        vx_app_load_test.out
    app_stereo.cfg                         vx_app_mcan.out
    app_tidl_cam.cfg                       vx_app_multi_cam.out
    app_vl.cfg                             vx_app_sfm.out
    run_app_arm_fd_exchange.sh             vx_app_single_cam.out
    run_app_c7x.sh                         vx_app_srv_calibration.out
    run_app_dof.sh                         vx_app_srv_camera.out
    run_app_encode.sh                      vx_app_srv_fileio.out
    run_app_multi_cam.sh                   vx_app_stereo_depth.out
    run_app_sfm.sh                         vx_app_test_framework.out
    run_app_single_cam.sh                  vx_app_tidl.out
    run_app_srv.sh                         vx_app_tidl_avp.out
    run_app_srv_avp.sh                     vx_app_tidl_avp2.out
    run_app_stereo.sh                      vx_app_tidl_avp3.out
    run_app_tidl.sh                        vx_app_tidl_avp4.out
    run_app_tidl_16bit.sh                  vx_app_tidl_cam.out
    run_app_tidl_avp.sh                    vx_app_tidl_od.out
    run_app_tidl_avp2.sh                   vx_app_tidl_od_cam.out
    run_app_tidl_avp3.sh                   vx_app_tidl_seg.out
    run_app_tidl_avp4.sh                   vx_app_tidl_seg_cam.out
    run_app_tidl_cam.sh                    vx_app_tidl_vl.out
    run_app_tidl_od.sh                     vx_app_tutorial.out
    run_app_tidl_od_cam.sh                 vx_app_viss.out
    run_app_tidl_seg.sh
    run_app_tidl_seg_16bit.sh
    J7EVM@QNX:/ti_fs/vision_apps# ./vision_apps_init.sh
    J7EVM@QNX:/ti_fs/vision_apps# [MCU2_0]      4.742710 s: CIO: Init ... Done !!!
    [MCU2_0]      4.742774 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
    [MCU2_0]      4.742814 s: APP: Init ... !!!
    [MCU2_0]      4.742836 s: SCICLIENT: Init ... !!!
    [MCU2_0]      4.768647 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla]
    [MCU2_0]      4.768691 s: SCICLIENT: DMSC FW revision 0x15
    [MCU2_0]      4.768718 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU2_0]      4.768743 s: SCICLIENT: Init ... Done !!!
    [MCU2_0]      4.768763 s: UDMA: Init ... !!!
    [MCU2_0]      5.055768 s: UDMA: Init ... Done !!!
    [MCU2_0]      5.055832 s: MEM: Init ... !!!
    [MCU2_0]      5.055868 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e1000000 of size 16777216 bytes !!!
    [MCU2_0]      5.055940 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 131072 bytes !!!
    [MCU2_0]      5.056001 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ d8000000 of size 16777216 bytes !!!
    [MCU2_0]      5.056048 s: MEM: Init ... Done !!!
    [MCU2_0]      5.056071 s: IPC: Init ... !!!
    [MCU2_0]      5.056135 s: IPC: 7 CPUs participating in IPC !!!
    [MCU2_0]      5.450052 s: IPC: ERROR: RPMessage_init failed !!!
    [MCU2_0]      5.450103 s: IPC: Init ... Done !!!
    [MCU2_1]      4.967704 s: CIO: Init ... Done !!!
    [MCU2_1]      4.967775 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
    [MCU2_1]      4.967818 s: APP: Init ... !!!
    [MCU2_1]      4.967835 s: SCICLIENT: Init ... !!!
    [MCU2_1]      5.018648 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla]
    [MCU2_1]      5.018698 s: SCICLIENT: DMSC FW revision 0x15
    [MCU2_1]      5.018723 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU2_1]      5.018746 s: SCICLIENT: Init ... Done !!!
    [MCU2_1]      5.018766 s: UDMA: Init ... !!!
    [MCU2_1]      5.975075 s: UDMA: Init ... Done !!!
    [MCU2_1]      5.975131 s: MEM: Init ... !!!
    [MCU2_1]      5.975165 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e2000000 of size 16777216 bytes !!!
    [MCU2_1]      5.975216 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3620000 of size 131072 bytes !!!
    [MCU2_1]      5.975261 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ d9000000 of size 117440512 bytes !!!
    [MCU2_1]      5.975303 s: MEM: Init ... Done !!!
    [MCU2_1]      5.975322 s: IPC: Init ... !!!
    [MCU2_1]      5.975349 s: IPC: 7 CPUs participating in IPC !!!
    [MCU2_1]      6.605112 s: IPC: ERROR: RPMessage_init failed !!!
    [MCU2_1]      6.605167 s: IPC: Init ... Done !!!
    [C6x_1 ]      5.167732 s: CIO: Init ... Done !!!
    [C6x_1 ]      5.167764 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
    [C6x_1 ]      5.167776 s: APP: Init ... !!!
    [C6x_1 ]      5.167784 s: SCICLIENT: Init ... !!!
    [C6x_1 ]      5.241527 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla]
    [C6x_1 ]      5.241539 s: SCICLIENT: DMSC FW revision 0x15
    [C6x_1 ]      5.241547 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C6x_1 ]      5.241557 s: SCICLIENT: Init ... Done !!!
    [C6x_1 ]      5.241566 s: UDMA: Init ... !!!
    [C6x_1 ]      6.717740 s: UDMA: Init ... Done !!!
    [C6x_1 ]      6.717763 s: MEM: Init ... !!!
    [C6x_1 ]      6.717775 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e4000000 of size 16777216 bytes !!!
    [C6x_1 ]      6.717791 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
    [C6x_1 ]      6.717806 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e5000000 of size 50331648 bytes !!!
    [C6x_1 ]      6.717822 s: MEM: Init ... Done !!!
    [C6x_1 ]      6.717830 s: IPC: Init ... !!!
    [C6x_1 ]      6.717843 s: IPC: 7 CPUs participating in IPC !!!
    [C6x_1 ]      7.589326 s: IPC: ERROR: RPMessage_init failed !!!
    [C6x_1 ]      7.589346 s: IPC: Init ... Done !!!
    [C6x_2 ]      5.360604 s: CIO: Init ... Done !!!
    [C6x_2 ]      5.360636 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
    [C6x_2 ]      5.360650 s: APP: Init ... !!!
    [C6x_2 ]      5.360658 s: SCICLIENT: Init ... !!!
    [C6x_2 ]      5.460530 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla]
    [C6x_2 ]      5.460541 s: SCICLIENT: DMSC FW revision 0x15
    [C6x_2 ]      5.460550 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C6x_2 ]      5.460560 s: SCICLIENT: Init ... Done !!!
    [C6x_2 ]      5.460568 s: UDMA: Init ... !!!
    [C6x_2 ]      6.891754 s: UDMA: Init ... Done !!!
    [C6x_2 ]      6.891778 s: MEM: Init ... !!!
    [C6x_2 ]      6.891790 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e8000000 of size 16777216 bytes !!!
    [C6x_2 ]      6.891807 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
    [C6x_2 ]      6.891822 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e9000000 of size 50331648 bytes !!!
    [C6x_2 ]      6.891837 s: MEM: Init ... Done !!!
    [C6x_2 ]      6.891845 s: IPC: Init ... !!!
    [C6x_2 ]      6.891859 s: IPC: 7 CPUs participating in IPC !!!
    [C6x_2 ]      7.652466 s: IPC: ERROR: RPMessage_init failed !!!
    [C6x_2 ]      7.652485 s: IPC: Init ... Done !!!
    [C7x_1 ]      5.661689 s: CIO: Init ... Done !!!
    [C7x_1 ]      5.661711 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
    [C7x_1 ]      5.661727 s: APP: Init ... !!!
    [C7x_1 ]      5.661735 s: SCICLIENT: Init ... !!!
    [C7x_1 ]      5.761549 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla]
    [C7x_1 ]      5.761564 s: SCICLIENT: DMSC FW revision 0x15
    [C7x_1 ]      5.761574 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C7x_1 ]      5.761585 s: SCICLIENT: Init ... Done !!!
    [C7x_1 ]      5.761593 s: UDMA: Init ... !!!
    [C7x_1 ]      6.997908 s: UDMA: Init ... Done !!!
    [C7x_1 ]      6.997921 s: MEM: Init ... !!!
    [C7x_1 ]      6.997933 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ 100000000 of size 1073741824 bytes !!!
    [C7x_1 ]      6.997955 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!
    [C7x_1 ]      6.997974 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!!
    [C7x_1 ]      6.997991 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
    [C7x_1 ]      6.998008 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 268435456 bytes !!!
    [C7x_1 ]      6.998026 s: MEM: Init ... Done !!!
    [C7x_1 ]      6.998033 s: IPC: Init ... !!!
    [C7x_1 ]      6.998043 s: IPC: 7 CPUs participating in IPC !!!
    [C7x_1 ]      7.376232 s: IPC: ERROR: RPMessage_init failed !!!
    [C7x_1 ]      7.376248 s: IPC: Init ... Done !!!
    
     

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    如果 mcusw mcu1_0不被使用。  

    1.在$vision_apps/vision_apps_build_flags.mk 中启用 build_cpu_MCU1_0

    2.在 $vision_apps/apps/basic_demos/app_tirtos/common/app_cfg.h 中启用 ENABLE_IPC_MCU1_0

    3.cd vision_apps,make SDK

    4.使 QNX_FS_CREATE _SD、使 QNX_FS_INSTALL_SD。

    U-Boot SPL 2020.01-svn2210 (May 11 2021 - 10:51:16 +0800)
    SYSFW ABI: 3.1 (firmware rev 0x0015 '21.1.1--v2021.01a (Terrific Lla')
    Reading on-board EEPROM at 0x50 failed -1
    Trying to boot from MMC2
    Loading Environment from MMC... *** Warning - No MMC card found, using default environment
    
    Starting ATF on ARM64 core...
    
    NOTICE:  BL31: v2.4(release):07.03.00.005-dirty
    NOTICE:  BL31: Built : 00:15:40, Apr 10 2021
    
    U-Boot SPL 2020.01-svn2210 (May 17 2021 - 11:26:41 +0800)
    SYSFW ABI: 3.1 (firmware rev 0x0015 '21.1.1--v2021.01a (Terrific Lla')
    Reading on-board EEPROM at 0x50 failed -1
    Trying to boot from MMC2
    i2c_write: error waiting for data ACK (status=0x116)
    Error reading output register
    
    
    U-Boot 2020.01-svn2210 (May 17 2021 - 11:26:41 +0800)
    
    SoC:   J721E SR2.0
    Model: Texas Instruments K3 J721E SoC
    Reading on-board EEPROM at 0x50 failed -1
    Board: J721EX-PM1-SOM rev E2
    DRAM:  4 GiB
    not found for dev hbmc-mux
    Flash: 0 Bytes
    MMC:   sdhci@4f80000: 0, sdhci@4fb0000: 1
    Loading Environment from MMC... OK
    In:    serial@2800000
    Out:   serial@2800000
    Err:   serial@2800000
    Reading on-board EEPROM at 0x50 failed -1
    Net:   Could not get PHY for ethernet@46000000: addr 0
    phy_connect() failed
    No ethernet found.
    
    Hit any key to stop autoboot:  0
    i2c_write: error waiting for data ACK (status=0x116)
    Error reading output register
    switch to partitions #0, OK
    mmc1 is current device
    i2c_write: error waiting for data ACK (status=0x116)
    Error reading output register
    SD/MMC found on device 1
    526 bytes read in 3 ms (170.9 KiB/s)
    Loaded env from uEnv.txt
    Importing environment from mmc1 ...
    Running uenvcmd ...
    Core 1 is already in use. No rproc commands work
    Core 2 is already in use. No rproc commands work
    4186156 bytes read in 175 ms (22.8 MiB/s)
    Load Remote Processor 2 with data@addr=0x82000000 4186156 bytes: Success!
    4186128 bytes read in 174 ms (22.9 MiB/s)
    Load Remote Processor 3 with data@addr=0x82000000 4186128 bytes: Success!
    5322900 bytes read in 222 ms (22.9 MiB/s)
    Load Remote Processor 6 with data@addr=0x82000000 5322900 bytes: Success!
    5322916 bytes read in 222 ms (22.9 MiB/s)
    Load Remote Processor 7 with data@addr=0x82000000 5322916 bytes: Success!
    11475424 bytes read in 65 ms (168.4 MiB/s)
    Load Remote Processor 8 with data@addr=0x82000000 11475424 bytes: Success!
    8176948 bytes read in 342 ms (22.8 MiB/s)
    ## Starting application at 0x80080000 ...
    MMU: 16-bit ASID 44-bit PA TCR_EL1=b5183519
    cpu0: MPIDR=80000000
    cpu0: MIDR=411fd080 Cortex-A72 r1p0
    cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
    cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
    cpu0: L1 Icache 48K linesz=64 set/way=256/3
    cpu0: L1 Dcache 32K linesz=64 set/way=256/2
    cpu0: L2 Unified 1024K linesz=64 set/way=1024/16
    Display set to R5
    Loading IFS...decompressing...done
    cpu1: MPIDR=80000001
    cpu1: MIDR=411fd080 Cortex-A72 r1p0
    cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
    cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
    cpu1: L1 Icache 48K linesz=64 set/way=256/3
    cpu1: L1 Dcache 32K linesz=64 set/way=256/2
    cpu1: L2 Unified 1024K linesz=64 set/way=1024/16
    
    System page at phys:0000000080011000 user:ffffff8040254000 kern:ffffff8040251000
    Starting next program at vffffff8060086e10
    All ClockCycles offsets within tolerance
    *******************************************************
    *******************NRA ver0.51 base*********************
    ****RTOS-07-03-00-07 QNX-07-03-00 LINUX-07-03-00-05****
    *******************************************************
    Starting random service ...
    start serial driver
    Starting MMC/SD memory card driver... eMMC
    Starting MMC/SD memory card driver... SD
    Starting XHCI driver on USB3SS0 and USB3SS1
    Path=0 - am65x
     target=0 lun=0     Direct-Access(0) - SDMMC: 032GB4 Rev: 0.4
    Setting environment variables...
    done..
    Mounting the sd ..
    Looking for user script to run: /ti_fs/scripts/user.sh
    Running user script...
    user.sh called...
    Setting additional environment variables...
    Starting tisci-mgr..
    Starting shmemallocator..
    Starting tiipc-mgr..
    Mailbox_plugInterrupt: interrupt Number 489, arg 0x718F1018
    Mailbox_plugInterrupt: interrupt Number 490, arg 0x718F11B8
    Mailbox_plugInterrupt: interrupt Number 491, arg 0x718F1358
    Mailbox_plugInterrupt: interrupt Number 492, arg 0x718F14F8
    Mailbox_plugInterrupt: interrupt Number 493, arg 0x718F1698
    
    Process 57360 (tiipc-mgr) terminated SIGSEGV code=1 fltno=11 ip=00000054718a5798(/ti_fs/tibin/tiipc-mgr@lose+0x0000000000003438) mapaddr=000000000000f798. ref=00000020316d1ff0
    Memory fault (core dumped)
    Starting tiudma-mgr..
    Start screen..
    screen started with dss_on_r5 configuration..
    done...
    
    

    [MCU1_0]      0.038299 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
    [MCU1_0]      0.038345 s: APP: Init ... !!!
    [MCU1_0]      0.038367 s: MEM: Init ... !!!
    [MCU1_0]      0.038397 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e0000000 of size 8388608 bytes !!!
    [MCU1_0]      0.038452 s: MEM: Init ... Done !!!
    [MCU1_0]      0.038472 s: IPC: Init ... !!!
    [MCU1_0]      0.038501 s: IPC: 7 CPUs participating in IPC !!!
    [MCU1_0]      0.045337 s: IPC: Init ... Done !!!
    [MCU1_0]      0.045398 s: APP: Syncing with 6 CPUs ... !!!
    [MCU1_0]      4.468090 s: APP: Syncing with 6 CPUs ... Done !!!
    [MCU1_0]      4.468349 s: REMOTE_SERVICE: Init ... !!!
    [MCU1_0]      4.469989 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU1_0]      4.475082 s: APP: Init ... Done !!!
    [MCU1_0]      4.476682 s: APP: Run ... !!!
    [MCU1_0]      4.478758 s: IPC: Starting echo test ...
    [MCU1_0]      4.483789 s: APP: Run ... Done !!!
    [MCU1_0]      4.484964 s: IPC: Echo status: mpu1_0[x] mcu1_0[s] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[.] C7X_1[.]
    [MCU1_0]      4.485070 s: IPC: Echo status: mpu1_0[x] mcu1_0[s] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[P] C7X_1[.]
    [MCU1_0]      4.485154 s: IPC: Echo status: mpu1_0[x] mcu1_0[s] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[P] C7X_1[P]
    [MCU1_0]      4.542821 s: IPC: Echo status: mpu1_0[x] mcu1_0[s] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
    [MCU1_0]      4.697467 s: IPC: Echo status: mpu1_0[x] mcu1_0[s] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
    [MCU2_0]      3.718521 s: CIO: Init ... Done !!!
    [MCU2_0]      3.718585 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
    [MCU2_0]      3.718626 s: APP: Init ... !!!
    [MCU2_0]      3.718644 s: SCICLIENT: Init ... !!!
    [MCU2_0]      3.718854 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla]
    [MCU2_0]      3.718890 s: SCICLIENT: DMSC FW revision 0x15
    [MCU2_0]      3.718913 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU2_0]      3.718937 s: SCICLIENT: Init ... Done !!!
    [MCU2_0]      3.718958 s: UDMA: Init ... !!!
    [MCU2_0]      3.720101 s: UDMA: Init ... Done !!!
    [MCU2_0]      3.720147 s: MEM: Init ... !!!
    [MCU2_0]      3.720182 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e1000000 of size 16777216 bytes !!!
    [MCU2_0]      3.720237 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 131072 bytes !!!
    [MCU2_0]      3.720279 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ d8000000 of size 16777216 bytes !!!
    [MCU2_0]      3.720321 s: MEM: Init ... Done !!!
    [MCU2_0]      3.720339 s: IPC: Init ... !!!
    [MCU2_0]      3.720366 s: IPC: 7 CPUs participating in IPC !!!
    [MCU2_0]      3.726763 s: IPC: Init ... Done !!!
    [MCU2_0]      3.726821 s: APP: Syncing with 6 CPUs ... !!!
    [MCU2_0]      4.468089 s: APP: Syncing with 6 CPUs ... Done !!!
    [MCU2_0]      4.468124 s: REMOTE_SERVICE: Init ... !!!
    [MCU2_0]      4.469959 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU2_0]      4.470019 s: ETHFW: Init ... !!!
    [MCU2_0]      4.563106 s: CPSW_9G Test on MAIN NAVSS
    [MCU2_0]      4.575071 s: PHY 1 is alive
    [MCU2_0]      4.576812 s: ETHFW: Version   : 0.01.01
    [MCU2_0]      4.576865 s: ETHFW: Build Date: May 10, 2021
    [MCU2_0]      4.576889 s: ETHFW: Build Time: 10:20:30
    [MCU2_0]      4.576909 s: ETHFW: Commit SHA:
    [MCU2_0]      4.576931 s: ETHFW: Init ... DONE !!!
    [MCU2_0]      4.576954 s: ETHFW: Remove server Init ... !!!
    [MCU2_0]      4.578093 s: Remote demo device (core : mcu2_0) .....
    [MCU2_0]      4.578148 s: ETHFW: Remove server Init ... DONE !!!
    [MCU2_0]      4.584119 s: Host MAC address: 70:ff:76:1d:92:c2
    [MCU2_0]      4.627354 s: FVID2: Init ... !!!
    [MCU2_0]      4.627473 s: FVID2: Init ... Done !!!
    [MCU2_0]      4.627518 s: DSS: Init ... !!!
    [MCU2_0]      4.627541 s: DSS: Display type is eDP !!!
    [MCU2_0]      4.627562 s: DSS: SoC init ... !!!
    [MCU2_0]      4.627579 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
    [MCU2_0]      4.627757 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      4.627787 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state=2
    [MCU2_0]      4.627939 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      4.627964 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state=2
    [MCU2_0]      4.628080 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      4.628105 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11
    [MCU2_0]      4.628194 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
    [MCU2_0]      4.628220 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=13 parent=18
    [MCU2_0]      4.628291 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
    [MCU2_0]      4.628315 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=1 parent=2
    [MCU2_0]      4.628413 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
    [MCU2_0]      4.628443 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=1 freq=148500000
    [MCU2_0]      4.629403 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
    [MCU2_0]      4.629433 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=1 state=2 flag=0
    [MCU2_0]      4.629554 s: SCICLIENT: Sciclient_pmModuleClkRequest success
    [MCU2_0]      4.629578 s: DSS: SoC init ... Done !!!
    [MCU2_0]      4.629597 s: DSS: Board init ... !!!
    [MCU2_0]      4.629615 s: DSS: Turning on DP_PWR pin for eDP adapters ... !!!
    [MCU2_0]      4.629919 s: DSS: Turning on DP_PWR pin for eDP adapters ... Done!!!
    [MCU2_0]      4.629951 s: DSS: Board init ... Done !!!
    [MCU2_0]      4.647903 s: DSS: Init ... Done !!!
    [MCU2_0]      4.647960 s: VHWA: VPAC Init ... !!!
    [MCU2_0]      4.647983 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
    [MCU2_0]      4.648150 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      4.648176 s: VHWA: LDC Init ... !!!
    [MCU2_0]      4.651275 s: VHWA: LDC Init ... Done !!!
    [MCU2_0]      4.651322 s: VHWA: MSC Init ... !!!
    [MCU2_0]      4.660471 s: VHWA: MSC Init ... Done !!!
    [MCU2_0]      4.660519 s: VHWA: NF Init ... !!!
    [MCU2_0]      4.662125 s: VHWA: NF Init ... Done !!!
    [MCU2_0]      4.662170 s: VHWA: VISS Init ... !!!
    [MCU2_0]      4.668708 s: VHWA: VISS Init ... Done !!!
    [MCU2_0]      4.668758 s: VHWA: VPAC Init ... Done !!!
    [MCU2_0]      4.668793 s:  VX_ZONE_INIT:Enabled
    [MCU2_0]      4.668815 s:  VX_ZONE_ERROR:Enabled
    [MCU2_0]      4.668834 s:  VX_ZONE_WARNING:Enabled
    [MCU2_0]      4.669865 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target IPU1-0
    [MCU2_0]      4.670123 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_NF
    [MCU2_0]      4.670416 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_LDC1
    [MCU2_0]      4.670679 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_MSC1
    [MCU2_0]      4.670922 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_MSC2
    [MCU2_0]      4.671184 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_VISS1
    [MCU2_0]      4.671511 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE1
    [MCU2_0]      4.671803 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE2
    [MCU2_0]      4.672070 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DISPLAY1
    [MCU2_0]      4.672397 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DISPLAY2
    [MCU2_0]      4.672679 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CSITX
    [MCU2_0]      4.672957 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE3
    [MCU2_0]      4.673222 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE4
    [MCU2_0]      4.673544 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE5
    [MCU2_0]      4.673824 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE6
    [MCU2_0]      4.674085 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE7
    [MCU2_0]      4.674339 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE8
    [MCU2_0]      4.674646 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target MCAN0
    [MCU2_0]      4.674900 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target MCAN3
    [MCU2_0]      4.675137 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target MCAN7
    [MCU2_0]      4.675404 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target MCAN9
    [MCU2_0]      4.675665 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAMERASWITCH
    [MCU2_0]      4.675711 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    [MCU2_0]      4.675737 s: APP: OpenVX Target kernel init ... !!!
    [MCU2_0]      4.687038 s: APP: tivxRegisterCameraSwitchTargetR5FKernels !!!
    [MCU2_0]      4.687092 s: Start to call tivxAddTargetKernelCameraSwitch
    [MCU2_0]      4.687117 s: Start to call tivxAddTargetKernelCameraSwitch 6
    [MCU2_0]      4.687145 s: Start to call tivxAddTargetKernelCameraSwitch CAMERASWITCH
    [MCU2_0]      4.687195 s: APP: OpenVX Target kernel init ... Done !!!
    [MCU2_0]      4.687219 s: CSI2RX: Init ... !!!
    [MCU2_0]      4.687236 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
    [MCU2_0]      4.687340 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      4.687405 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
    [MCU2_0]      4.687530 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      4.687557 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
    [MCU2_0]      4.687668 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      4.687693 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
    [MCU2_0]      4.687766 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      4.687789 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
    [MCU2_0]      4.687857 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      4.688554 s: CSI2RX: Init ... Done !!!
    [MCU2_0]      4.688600 s: CSI2TX: Init ... !!!
    [MCU2_0]      4.688621 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
    [MCU2_0]      4.688705 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      4.688731 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2
    [MCU2_0]      4.688835 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      4.688859 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
    [MCU2_0]      4.688951 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      4.689486 s: CSI2TX: Init ... Done !!!
    [MCU2_0]      4.689529 s: ISS: Init ... !!!
    [MCU2_0]      4.689559 s: IssSensor_Init ... Done !!!
    [MCU2_0]      4.689623 s: vissRemoteServer_Init ... Done !!!
    [MCU2_0]      4.689677 s: IttRemoteServer_Init ... Done !!!
    [MCU2_0]      4.689702 s: UDMA Copy: Init ... !!!
    [MCU2_0]      4.691245 s: UDMA Copy: Init ... Done !!!
    [MCU2_0]      4.691292 s: APP: Camera GPIO Set start !!!
    [MCU2_0]      4.691378 s: APP: Init ... Done !!!
    [MCU2_0]      4.691406 s: APP: Run ... !!!
    [MCU2_0]      4.691423 s: IPC: Starting echo test ...
    [MCU2_0]      4.693973 s: APP: Run ... Done !!!
    [MCU2_0]      4.694295 s: BOARD: GPIO CFG !!!
    [MCU2_0]      4.697699 s: IPC: Echo status: mpu1_0[x] mcu1_0[.] mcu2_0[s] mcu2_1[.] C66X_1[P] C66X_2[.] C7X_1[.]
    [MCU2_0]      4.697922 s: IPC: Echo status: mpu1_0[x] mcu1_0[.] mcu2_0[s] mcu2_1[.] C66X_1[P] C66X_2[P] C7X_1[.]
    [MCU2_0]      4.698052 s: IPC: Echo status: mpu1_0[x] mcu1_0[.] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[.]
    [MCU2_0]      4.698159 s: IPC: Echo status: mpu1_0[x] mcu1_0[.] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
    [MCU2_0]      4.698263 s: IPC: Echo status: mpu1_0[x] mcu1_0[P] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
    [MCU2_0]    172.695458 s: DHCP client timed out. Retrying.....
    [MCU2_0]    340.695455 s: DHCP client timed out. Retrying.....
    [MCU2_0]    508.695456 s: DHCP client timed out. Retrying.....
    [MCU2_0]    676.695458 s: DHCP client timed out. Retrying.....
    [MCU2_0]    844.695457 s: DHCP client timed out. Retrying.....
    [MCU2_0]   1012.695479 s: DHCP client timed out. Retrying.....
    [MCU2_0]   1180.695480 s: DHCP client timed out. Retrying.....
    [MCU2_0]   1348.695469 s: DHCP client timed out. Retrying.....
    [MCU2_0]   1516.695463 s: DHCP client timed out. Retrying.....
    [MCU2_0]   1684.695461 s: DHCP client timed out. Retrying.....
    [MCU2_0]   1852.695460 s: DHCP client timed out. Retrying.....
    [MCU2_0]   2020.695458 s: DHCP client timed out. Retrying.....
    [MCU2_0]   2188.695460 s: DHCP client timed out. Retrying.....
    [MCU2_0]   2356.695504 s: DHCP client timed out. Retrying.....
    [MCU2_0]   2524.695464 s: DHCP client timed out. Retrying.....
    [MCU2_0]   2692.695463 s: DHCP client timed out. Retrying.....
    [MCU2_0]   2860.695493 s: DHCP client timed out. Retrying.....
    [MCU2_0]   3028.695461 s: DHCP client timed out. Retrying.....
    [MCU2_0]   3196.695459 s: DHCP client timed out. Retrying.....
    [MCU2_0]   3364.695461 s: DHCP client timed out. Retrying.....
    [MCU2_0]   3532.695462 s: DHCP client timed out. Retrying.....
    [MCU2_0]   3700.695465 s: DHCP client timed out. Retrying.....
    [MCU2_1]      3.819271 s: CIO: Init ... Done !!!
    [MCU2_1]      3.819343 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
    [MCU2_1]      3.819385 s: APP: Init ... !!!
    [MCU2_1]      3.819406 s: SCICLIENT: Init ... !!!
    [MCU2_1]      3.819615 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla]
    [MCU2_1]      3.819653 s: SCICLIENT: DMSC FW revision 0x15
    [MCU2_1]      3.819677 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU2_1]      3.819701 s: SCICLIENT: Init ... Done !!!
    [MCU2_1]      3.819722 s: UDMA: Init ... !!!
    [MCU2_1]      3.820985 s: UDMA: Init ... Done !!!
    [MCU2_1]      3.821037 s: MEM: Init ... !!!
    [MCU2_1]      3.821070 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e2000000 of size 16777216 bytes !!!
    [MCU2_1]      3.821120 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3620000 of size 131072 bytes !!!
    [MCU2_1]      3.821166 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ d9000000 of size 117440512 bytes !!!
    [MCU2_1]      3.821210 s: MEM: Init ... Done !!!
    [MCU2_1]      3.821230 s: IPC: Init ... !!!
    [MCU2_1]      3.821259 s: IPC: 7 CPUs participating in IPC !!!
    [MCU2_1]      3.827514 s: IPC: Init ... Done !!!
    [MCU2_1]      3.827572 s: APP: Syncing with 6 CPUs ... !!!
    [MCU2_1]      4.468088 s: APP: Syncing with 6 CPUs ... Done !!!
    [MCU2_1]      4.468120 s: REMOTE_SERVICE: Init ... !!!
    [MCU2_1]      4.469820 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU2_1]      4.469879 s: FVID2: Init ... !!!
    [MCU2_1]      4.469944 s: FVID2: Init ... Done !!!
    [MCU2_1]      4.469975 s: VHWA: DMPAC: Init ... !!!
    [MCU2_1]      4.469994 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2
    [MCU2_1]      4.470226 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_1]      4.470257 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2
    [MCU2_1]      4.470754 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_1]      4.470788 s: VHWA: DOF Init ... !!!
    [MCU2_1]      4.478803 s: VHWA: DOF Init ... Done !!!
    [MCU2_1]      4.478856 s: VHWA: SDE Init ... !!!
    [MCU2_1]      4.481281 s: VHWA: SDE Init ... Done !!!
    [MCU2_1]      4.481328 s: VHWA: DMPAC: Init ... Done !!!
    [MCU2_1]      4.481375 s: VHWA: Codec: Init ... !!!
    [MCU2_1]      4.481402 s: VHWA: VDEC Init ... !!!
    [MCU2_1]      4.494464 s: VHWA: VDEC Init ... Done !!!
    [MCU2_1]      4.494513 s: VHWA: VENC Init ... !!!
    [MCU2_1]      4.494752 s: MM_ENC_Init: No OCM RAM pool available, fallback to DDR mode for above mp params
    [MCU2_1]      4.534801 s: VHWA: VENC Init ... Done !!!
    [MCU2_1]      4.534852 s: VHWA: Init ... Done !!!
    [MCU2_1]      4.534889 s:  VX_ZONE_INIT:Enabled
    [MCU2_1]      4.534912 s:  VX_ZONE_ERROR:Enabled
    [MCU2_1]      4.534932 s:  VX_ZONE_WARNING:Enabled
    [MCU2_1]      4.535902 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DMPAC_SDE
    [MCU2_1]      4.536122 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DMPAC_DOF
    [MCU2_1]      4.536333 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VDEC1
    [MCU2_1]      4.536593 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VDEC2
    [MCU2_1]      4.536800 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VENC1
    [MCU2_1]      4.537009 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VENC2
    [MCU2_1]      4.537060 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    [MCU2_1]      4.537088 s: APP: OpenVX Target kernel init ... !!!
    [MCU2_1]      4.537470 s: APP: OpenVX Target kernel init ... Done !!!
    [MCU2_1]      4.537511 s: UDMA Copy: Init ... !!!
    [MCU2_1]      4.539148 s: UDMA Copy: Init ... Done !!!
    [MCU2_1]      4.539200 s: APP: Init ... Done !!!
    [MCU2_1]      4.539224 s: APP: Run ... !!!
    [MCU2_1]      4.539245 s: IPC: Starting echo test ...
    [MCU2_1]      4.541632 s: APP: Run ... Done !!!
    [MCU2_1]      4.542980 s: IPC: Echo status: mpu1_0[x] mcu1_0[.] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[.] C7X_1[.]
    [MCU2_1]      4.543076 s: IPC: Echo status: mpu1_0[x] mcu1_0[.] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[.]
    [MCU2_1]      4.543144 s: IPC: Echo status: mpu1_0[x] mcu1_0[.] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P]
    [MCU2_1]      4.543213 s: IPC: Echo status: mpu1_0[x] mcu1_0[P] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P]
    [MCU2_1]      4.697395 s: IPC: Echo status: mpu1_0[x] mcu1_0[P] mcu2_0[P] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P]
    [C6x_1 ]      3.926752 s: CIO: Init ... Done !!!
    [C6x_1 ]      3.926786 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
    [C6x_1 ]      3.926799 s: APP: Init ... !!!
    [C6x_1 ]      3.926807 s: SCICLIENT: Init ... !!!
    [C6x_1 ]      3.927000 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla]
    [C6x_1 ]      3.927011 s: SCICLIENT: DMSC FW revision 0x15
    [C6x_1 ]      3.927020 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C6x_1 ]      3.927030 s: SCICLIENT: Init ... Done !!!
    [C6x_1 ]      3.927038 s: UDMA: Init ... !!!
    [C6x_1 ]      3.928369 s: UDMA: Init ... Done !!!
    [C6x_1 ]      3.928393 s: MEM: Init ... !!!
    [C6x_1 ]      3.928404 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e4000000 of size 16777216 bytes !!!
    [C6x_1 ]      3.928421 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
    [C6x_1 ]      3.928436 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e5000000 of size 50331648 bytes !!!
    [C6x_1 ]      3.928451 s: MEM: Init ... Done !!!
    [C6x_1 ]      3.928459 s: IPC: Init ... !!!
    [C6x_1 ]      3.928472 s: IPC: 7 CPUs participating in IPC !!!
    [C6x_1 ]      3.932035 s: IPC: Init ... Done !!!
    [C6x_1 ]      3.932065 s: APP: Syncing with 6 CPUs ... !!!
    [C6x_1 ]      4.468087 s: APP: Syncing with 6 CPUs ... Done !!!
    [C6x_1 ]      4.468098 s: REMOTE_SERVICE: Init ... !!!
    [C6x_1 ]      4.468877 s: REMOTE_SERVICE: Init ... Done !!!
    [C6x_1 ]      4.468917 s:  VX_ZONE_INIT:Enabled
    [C6x_1 ]      4.468927 s:  VX_ZONE_ERROR:Enabled
    [C6x_1 ]      4.468936 s:  VX_ZONE_WARNING:Enabled
    [C6x_1 ]      4.469821 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    [C6x_1 ]      4.469841 s: APP: OpenVX Target kernel init ... !!!
    [C6x_1 ]      4.470123 s: APP: OpenVX Target kernel init ... Done !!!
    [C6x_1 ]      4.470143 s: UDMA Copy: Init ... !!!
    [C6x_1 ]      4.473807 s: UDMA Copy: Init ... Done !!!
    [C6x_1 ]      4.473827 s: APP: Init ... Done !!!
    [C6x_1 ]      4.474572 s: APP: Run ... !!!
    [C6x_1 ]      4.474581 s: IPC: Starting echo test ...
    [C6x_1 ]      4.475967 s: APP: Run ... Done !!!
    [C6x_1 ]      4.476325 s: IPC: Echo status: mpu1_0[x] mcu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[P] C7X_1[.]
    [C6x_1 ]      4.476363 s: IPC: Echo status: mpu1_0[x] mcu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[P] C7X_1[P]
    [C6x_1 ]      4.484719 s: IPC: Echo status: mpu1_0[x] mcu1_0[P] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[P] C7X_1[P]
    [C6x_1 ]      4.542668 s: IPC: Echo status: mpu1_0[x] mcu1_0[P] mcu2_0[x] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P]
    [C6x_1 ]      4.697242 s: IPC: Echo status: mpu1_0[x] mcu1_0[P] mcu2_0[P] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P]
    [C6x_2 ]      4.011827 s: CIO: Init ... Done !!!
    [C6x_2 ]      4.011862 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
    [C6x_2 ]      4.011875 s: APP: Init ... !!!
    [C6x_2 ]      4.011882 s: SCICLIENT: Init ... !!!
    [C6x_2 ]      4.012081 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla]
    [C6x_2 ]      4.012092 s: SCICLIENT: DMSC FW revision 0x15
    [C6x_2 ]      4.012101 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C6x_2 ]      4.012110 s: SCICLIENT: Init ... Done !!!
    [C6x_2 ]      4.012119 s: UDMA: Init ... !!!
    [C6x_2 ]      4.013477 s: UDMA: Init ... Done !!!
    [C6x_2 ]      4.013502 s: MEM: Init ... !!!
    [C6x_2 ]      4.013514 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ e8000000 of size 16777216 bytes !!!
    [C6x_2 ]      4.013531 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
    [C6x_2 ]      4.013546 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e9000000 of size 50331648 bytes !!!
    [C6x_2 ]      4.013561 s: MEM: Init ... Done !!!
    [C6x_2 ]      4.013569 s: IPC: Init ... !!!
    [C6x_2 ]      4.013583 s: IPC: 7 CPUs participating in IPC !!!
    [C6x_2 ]      4.017184 s: IPC: Init ... Done !!!
    [C6x_2 ]      4.017213 s: APP: Syncing with 6 CPUs ... !!!
    [C6x_2 ]      4.468087 s: APP: Syncing with 6 CPUs ... Done !!!
    [C6x_2 ]      4.468098 s: REMOTE_SERVICE: Init ... !!!
    [C6x_2 ]      4.468872 s: REMOTE_SERVICE: Init ... Done !!!
    [C6x_2 ]      4.468910 s:  VX_ZONE_INIT:Enabled
    [C6x_2 ]      4.468920 s:  VX_ZONE_ERROR:Enabled
    [C6x_2 ]      4.468929 s:  VX_ZONE_WARNING:Enabled
    [C6x_2 ]      4.469801 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    [C6x_2 ]      4.469820 s: APP: OpenVX Target kernel init ... !!!
    [C6x_2 ]      4.470115 s: APP: OpenVX Target kernel init ... Done !!!
    [C6x_2 ]      4.470135 s: UDMA Copy: Init ... !!!
    [C6x_2 ]      4.473519 s: UDMA Copy: Init ... Done !!!
    [C6x_2 ]      4.473536 s: APP: Init ... Done !!!
    [C6x_2 ]      4.474262 s: APP: Run ... !!!
    [C6x_2 ]      4.474272 s: IPC: Starting echo test ...
    [C6x_2 ]      4.475544 s: APP: Run ... Done !!!
    [C6x_2 ]      4.475885 s: IPC: Echo status: mpu1_0[x] mcu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[x] C66X_2[s] C7X_1[P]
    [C6x_2 ]      4.476321 s: IPC: Echo status: mpu1_0[x] mcu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[P]
    [C6x_2 ]      4.484770 s: IPC: Echo status: mpu1_0[x] mcu1_0[P] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[P]
    [C6x_2 ]      4.542720 s: IPC: Echo status: mpu1_0[x] mcu1_0[P] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P]
    [C6x_2 ]      4.697310 s: IPC: Echo status: mpu1_0[x] mcu1_0[P] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P]
    [C7x_1 ]      4.464577 s: CIO: Init ... Done !!!
    [C7x_1 ]      4.464599 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
    [C7x_1 ]      4.464614 s: APP: Init ... !!!
    [C7x_1 ]      4.464622 s: SCICLIENT: Init ... !!!
    [C7x_1 ]      4.464805 s: SCICLIENT: DMSC FW version [21.1.1--v2021.01a (Terrific Lla]
    [C7x_1 ]      4.464819 s: SCICLIENT: DMSC FW revision 0x15
    [C7x_1 ]      4.464828 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C7x_1 ]      4.464839 s: SCICLIENT: Init ... Done !!!
    [C7x_1 ]      4.464848 s: UDMA: Init ... !!!
    [C7x_1 ]      4.465856 s: UDMA: Init ... Done !!!
    [C7x_1 ]      4.465869 s: MEM: Init ... !!!
    [C7x_1 ]      4.465881 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ 100000000 of size 1073741824 bytes !!!
    [C7x_1 ]      4.465904 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!
    [C7x_1 ]      4.465922 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!!
    [C7x_1 ]      4.465939 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
    [C7x_1 ]      4.465957 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 268435456 bytes !!!
    [C7x_1 ]      4.465975 s: MEM: Init ... Done !!!
    [C7x_1 ]      4.465983 s: IPC: Init ... !!!
    [C7x_1 ]      4.465994 s: IPC: 7 CPUs participating in IPC !!!
    [C7x_1 ]      4.468058 s: IPC: Init ... Done !!!
    [C7x_1 ]      4.468073 s: APP: Syncing with 6 CPUs ... !!!
    [C7x_1 ]      4.468087 s: APP: Syncing with 6 CPUs ... Done !!!
    [C7x_1 ]      4.468098 s: REMOTE_SERVICE: Init ... !!!
    [C7x_1 ]      4.468440 s: REMOTE_SERVICE: Init ... Done !!!
    [C7x_1 ]      4.468487 s:  VX_ZONE_INIT:Enabled
    [C7x_1 ]      4.468502 s:  VX_ZONE_ERROR:Enabled
    [C7x_1 ]      4.468515 s:  VX_ZONE_WARNING:Enabled
    [C7x_1 ]      4.468790 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    [C7x_1 ]      4.468804 s: APP: OpenVX Target kernel init ... !!!
    [C7x_1 ]      4.468900 s: APP: OpenVX Target kernel init ... Done !!!
    [C7x_1 ]      4.468916 s: APP: Init ... Done !!!
    [C7x_1 ]      4.468925 s: APP: Run ... !!!
    [C7x_1 ]      4.468933 s: IPC: Starting echo test ...
    [C7x_1 ]      4.469495 s: APP: Run ... Done !!!
    [C7x_1 ]      4.475867 s: IPC: Echo status: mpu1_0[x] mcu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[x] C66X_2[P] C7X_1[s]
    [C7x_1 ]      4.476320 s: IPC: Echo status: mpu1_0[x] mcu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[P] C7X_1[s]
    [C7x_1 ]      4.484794 s: IPC: Echo status: mpu1_0[x] mcu1_0[P] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[P] C7X_1[s]
    [C7x_1 ]      4.542744 s: IPC: Echo status: mpu1_0[x] mcu1_0[P] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s]
    [C7x_1 ]      4.697341 s: IPC: Echo status: mpu1_0[x] mcu1_0[P] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s]

    链接至  https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1001368/tda4vm-after-builded-mcu1_0-run-vision-apps-demos-for-display-ipc-error-occurs

    在我提交相关 IPC 问题之前。

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    大家好, :  

    很抱歉、您共享的主题中缺少信息。

    根据 VISION 应用程序中的 IPC 回波测试结果、MCU1_0 (VISION 应用程序)和 MPU (A72、QNX、VISION 应用程序)之间的 IPC 正常工作。  

    因此、IPC 已成功初始化。

    是否要删除 ti_fs/scripts/user.sh 中的 IPC 初始化?

    然后重新启动设备,再次检查 vision_apps_init 日志。 让我们看看视觉应用回波测试是否可以通过 MCU1_0成功。

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    尊敬的 Peter:  

    根据 VISION 应用程序中的 IPC 回波测试结果、MCU1_0 (VISION 应用程序)和 MPU (A72、QNX、VISION 应用程序)之间的 IPC 正常工作。  

    那么、您是如何得出这一结论的。?

    上面我给出了两个回复。  最后一个是 在 EVM 上运行 TI 软件。   MCU1_0 (VISION APP)和 MPU (A72、QNX、VISION APP)之间的 IPC 无法正常工作。  该链接 有相关说明。

    我们希望使用 cddipc、一个原因是 MCU1_0 (VISION 应用)和 MPU (A72、QNX、VISION 应用)之间的 IPC 无法正常工作。

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    大家好, :  

    很抱歉,这是我的误解。

    我将在内部进行讨论、稍后再与您讨论。

    谢谢。

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好 Peter:

    我有一些问题要问您。

    在有关 mcu1_0 (mcusw)和 MCU2_1 (vision_apps)之间 Cdddipc 的示例中。 在 cddipc_vision.diff 中、  

    --- a/apps/basic_demos/app_tirtos/common/app_init.c
    +++ b/apps/basic_demos/app_tirtos/common/app_init.c
    @@ -494,7 +494,8 @@ int32_t appInit()
    if((host_os_type == APP_HOST_TYPE_LINUX) || (host_os_type == APP_HOST_TYPE_QNX))
    {
    /* dont sync with MPU1 running linux/qnx since that is taken care by the kernel */
    - if(ipc_init_prm.enabled_cpu_id_list[i]!=APP_IPC_CPU_MPU1_0)
    + if((ipc_init_prm.enabled_cpu_id_list[i]!=APP_IPC_CPU_MPU1_0)
    + &&(ipc_init_prm.enabled_cpu_id_list[i]!=APP_IPC_CPU_MCU1_0))
    {
    sync_cpu_id_list[num_sync_cpus] = ipc_init_prm.enabled_cpu_id_list[i];
    num_sync_cpus++;

    我的理解是  ,用于 MultiProc 配置的 IPC_mpSetConfig()、mcu1_0 (mcusw)和 MCU2_1 (vision_apps)是一对一的。 如果我为    mcu1_0 (mcusw)和 MCU2_1 (vision_apps)执行另一个 RPMessage_create()。 应调用 IPC_mpSetConfig()。 对吗?

    2.下面显示 了在调用 IPC_initVirtIO()与 在线内核配对之前应使用 IPC_isRemoteReady()。  您认为应该为 IPC 初始化完成此操作吗?  在您的示例中、是否应用了此函数?

     

    3.在我的应用程序中关于 cddipc beteen mcu1_0 (mcusw)和 MPU (vision_apps),我认为我只需要调用 RPMessage_create()来创建新的,如用于 在 MPU 和 MCU 之间进行通信的'channel'或'task'。 对吗?

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    大家好、 :  

    请查看我的以下评论:

    1.你是对的。

    仅 Linux IPC 需要此功能。  

      RTOS/QNX IPC 不需要它。

    3.我同意你的意见。

      我没有 QNX 环境来验证这一点。

    谢谢。