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器件型号：TDA4VM 你(们)好
我们对自定义硼执行一些启动测试、发现某些 DDR 初始化在配置为4266Mhz 时失败。
SDK 版本为07_03。 DDR 芯片为 MT53E1G32D2FW-046 AAT：B
硬件符号：
引用 e2e.ti.com/.../4094570的 DDR reg 配置文件
e2e.ti.com/.../board_5F00_ddrRegInit.h
我们还在源文件中进行一些更改以分析失败的日志：
for(counter = 0; counter < DDRSS_PLL_FHS_CNT; counter++)
{
/* wait for freq change request */
regVal = HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR) & 0x80;
BOARD_DEBUG_LOG("Reg Value: %d \n", regVal);
while(regVal == 0x0)
{
regVal = HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR) & 0x80;
BOARD_DEBUG_LOG("Reg Value: %d \n", regVal);
}
reqType = HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR) & 0x03;
BOARD_DEBUG_LOG("Frequency Change type %d request from Controller \n", reqType);
if(reqType == 1)
{
Board_DDRSetPLLClock(DDRSS_PLL_FREQUENCY_1);
BOARD_DEBUG_LOG("#####Board_DDRSetPLLClock : %d \n", DDRSS_PLL_FREQUENCY_1);
}
else if(reqType == 2)
{
Board_DDRSetPLLClock(DDRSS_PLL_FREQUENCY_2);
BOARD_DEBUG_LOG("#####Board_DDRSetPLLClock : %d \n", DDRSS_PLL_FREQUENCY_2);
}
else if(reqType == 0)
{
#ifndef BOARD_DDR_ENABLE_PLL_BYPASS
Board_DDRSetPLLExtBypass();
// Board_DDRSetPLLClock(DDRSS_PLL_FREQUENCY_0);
BOARD_DEBUG_LOG("#####Board_DDRSetPLLExtBypass 0##########\n");
#else
Board_DDRSetPLLExtBypass();
BOARD_DEBUG_LOG("#####Board_DDRSetPLLExtBypass 0##########\n");
#endif
}
这是来自 MCU UART 的日志、发生频率几乎为0.5%
2022-10-09 22:55:35.191812 type 1 request from Controller ^M^M #####Board_DDRSetPLLClock : 106 2022-10-09 22:55:35.256068 6500000 ^M^M Reg Value: 0 ^M^M Reg Value: 128 ^M^M Frequency Change ty 2022-10-09 22:55:35.319700 pe 2 request from Controller ^M^M #####Board_DDRSetPLLClock : 10665 2022-10-09 22:55:35.383598 00000 ^M^M Reg Value: 0 ^M^M Reg Value: 0 ^M^M Reg Value: 0 ^M^M Reg Valu 2022-10-09 22:55:35.447636 e: 0 ^M^M Reg Value: 0 ^M^M Reg Value: 0 ^M^M Reg Value: 0 ^M^M Reg Valu 2022-10-09 22:55:35.511317 e: 0 ^M^M Reg Value: 0 ^M^M Reg Value: 0 ^M^M Reg Value: 0 ^M^M Reg Val 2022-10-09 22:55:35.575640 ue: 0 ^M^M Reg Value: 0 ^M^M Reg Value: 0 ^M^M Reg Value: 0 ^M^M Reg Val 2022-10-09 22:55:35.639197 ue: 0 ^M^M Reg Value: 0 ^M^M Reg Value: 0 ^M^M Reg Value: 0 ^M^M Reg Val 2022-10-09 22:55:35.703201 ue: 0 ^M^M Reg Value: 0 ^M^M Reg Value: 0 ^M^M Reg Value: 128 ^M^M Frequ 2022-10-09 22:55:35.767094 ency Change type 1 request from Controller ^M^M #####Board_DDRSetP 2022-10-09 22:55:35.830893 LLClock : 1066500000 ^M^M Reg Value: 0 ^M^M Reg Value: 128 ^M^M Frequen 2022-10-09 22:55:35.894816 cy Change type 2 request from Controller ^M^M #####Board_DDRSetPLLC 2022-10-09 22:55:35.958626 lock : 1066500000 ^M^M --->>> Frequency Change request handshake is 2022-10-09 22:55:36.094621 completed... <<<---^M^M 2022-10-09 22:56:21.706586 Board_DDRStart: FAIL^M^M
配置文件中是否需要进行任何更改？ 硬件信号发生了哪些变化？