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器件型号：SK-TDA4VM Thread 中讨论的其他器件：SYSBIOS
大家好、
我正在尝试在 mcusw 上运行我们的项目应用程序映像、同时使用 Linux 进行 CAN 性能评测。
我按照 [常见问题解答] TDA4VM：CAN 上的 MCUSW 演示以及 A72上的 Linux -处理器论坛-处理器- TI E2E 支持论坛 中的所有步骤进行了操作、并且能够与 Linux 一起成功运行演示 CAN_PROFILE-APP、但对于我们的项目应用、Linux 无法启动。
应用程序作为输出成功运行：
/
正在启动 Sciserver..... 通过
主 APPLICATIONVariant -正在使用预编译！
主应用程序已成功启用 CAN Trans！
主应用程序已成功启用 CAN Trans！
测试1.
(小部分 /
但 Linux 窗口会显示以下消息：
/
U-Boot SPL 2020.01脏污(2022年11月07日- 11：18：20 +)
SYSFW ABI：3.1 (固件版本0x0015 '21.1.1 --v2021)
在0x50处读取板载 EEPROM 失败-1
尝试从 MMC2引导
正在从 MMC 加载环境... ***警告-无 Mt.
在 ARM64内核上启动 ATF...
注意： BL31：v2.4 (发布)：07.03.00.005-脏
注意： BL31：建筑时间：2021年4月10日00:15:40
「香港 /
1] 以下是以下命令的 elf 输出： readelf -l adas padcing_fune_app_release_strip.xer5f
/
readelf -l ADAS_PADAS_PADK_FACK_APP_mcu1_0_release_strip.xer5f
ELF 文件类型为 EXEC (可执行文件)
入口点0x41010000
有11个程序头、从偏移量707296开始
程序标题：
键入 Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
加载 0x000038 0x41010000 0x41010000 0x00040 0x00040 R 0x8
加载 0x000080 0x41010100 0x41010100 0x00540 0x00540 R E 0x10
加载 0x000600 0xa0400000 0xa0400000 0x00000 0x42d410 RW 0x80
加载 0x000600 0xa082d410 0xa082d410 0x948b0 0x948b0 R E 0x10
加载 0x094eb0 0xa08c1cc0 0xa08c1cc0 0x04dc0 0x04dc0 RW 0x4
加载 0x099c70 0xa08c6a80 0xa08c6a80 0x05b4a 0x05b4a R E 0x4
加载 0x09f800 0xa08cc600 0xa08cc600 0x01700 0x01700 R 0x80
加载 0x0a0f00 0xa08cd00 0xa08cd00 0x00000 0x02798 RW 0x4
加载 0x0a0f00 0xa08d0498 0xa08d0498 0x00770 0x00770 R 0x4
加载 0x0a1670 0xa08d0c08 0xa08d0c08 0x00000 0x003ec RW 0x4
加载 0x0a1670 0xa08d0ff8 0xa08d0ff8 0x0af98 0x0af98 R 0x8
段到段映射：
段段段段...
00 .vecs .vecs
01 .init_text .text：xdc_runtime_Startup_reset__i .utilsCopyVecsToAtcm
02 .bss .data .stack .bss.devgroup.DMSC_INTERNAL __llvm_prf_cnts
03 .text .const
04 McalNoInitSection
05 .const.devgroup.MAIN .const.devgroup.DMSC_INTERNAL McalTextSection
06 .boardcfg_data
07 .bss.devgroup.MAIN McalConstSection UtilityNoInitSection
08 .const.devgroup.MCU_WAKEUP
09 .bss.devgroup.MCU_WAKEUP McalInitSection
10 .cinit
(二 /
2]我已经为 CAN_PROFILE_APP 建议的 Mcu1_0应用了所有补丁、如下所示：
From 8e0cd1de42b07c24c9347d2d8ae013b1043f61f3 Mon Sep 17 00:00:00 2001
From: Karan Saxena <karan@ti.com>
Date: Wed, 10 Feb 2021 15:47:46 -0500
Subject: [PATCH 2/2] mcu1_0: can_profile_app: make changes to load from R5 SPL
- Add utility to copy vecs to 0x0
- [PDK-6738]
- The latest sysbios expects the vecs to be present at address 0x0.
When the ipc_echo_testb starts from BTCM from SPL branch-only mode
for mcu1_0, the vecs at 0x0 are not matching the sysbios vecs.
- This patch adds a function to the sysbios reset functions to
copy the vecs to 0x0 during bios startup for the btcm images.
With this, the vecs are as expected for sysbios and the image
is able to run sucessfully and finish the echo test.
- Note that R5 boots from SPL, 0x0 is mapped to start of
OCMC RAM, so when vecs are copied, it is reflected in
start of OCMC RAM. Care should be taken that this does not conflict
with any other images.
- Add an alternative method to bios hook function mcuCopyVecs2Exc
- An alternative to doing a copy of vecs using a bios hook function is to
do a memcpy().
- Align memory map with Linux reserved memory for MCU1_0
- Disable transceiver enable code to avoid conflict with Linux on A72
Signed-off-by: Karan Saxena <karan@ti.com>
---
.../examples/utils/src/mcuCopyVecs2Exc.asm | 59 +++++++++++++
mcuss_demos/profiling/can/main_tirtos.c | 44 +++++++---
mcuss_demos/profiling/can/makefile | 2 +-
.../j721e/mcu1_0/linker_r5_sysbios.lds | 84 ++++++++++---------
.../overrides/j721e/mcu1_0/sysbios_r5f.cfg | 2 +-
5 files changed, 137 insertions(+), 54 deletions(-)
create mode 100755 mcal_drv/mcal/examples/utils/src/mcuCopyVecs2Exc.asm
diff --git a/mcal_drv/mcal/examples/utils/src/mcuCopyVecs2Exc.asm b/mcal_drv/mcal/examples/utils/src/mcuCopyVecs2Exc.asm
new file mode 100755
index 0000000..ede6bc8
--- /dev/null
+++ b/mcal_drv/mcal/examples/utils/src/mcuCopyVecs2Exc.asm
@@ -0,0 +1,59 @@
+;
+; Copyright (c) 2020, Texas Instruments Incorporated
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions
+; are met:
+;
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+;
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+;
+; * Neither the name of Texas Instruments Incorporated nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;
+; ======== mcuCopyVecs2Exc.asm ========
+; Copies sysbios defined vector to Exception Handler area
+;
+ .text
+ .sect ".mcuCopyVecsToExc"
+;==============================================================================
+; void mcuCopyVecs2Exc( void )
+;==============================================================================
+ .global ti_sysbios_family_arm_v7r_keystone3_Hwi_vectors
+
+ .global mcuCopyVecs2Exc
+mcuCopyVecs2Exc:
+ .asmfunc
+ movw r0, ti_sysbios_family_arm_v7r_keystone3_Hwi_vectors
+ movt r0, ti_sysbios_family_arm_v7r_keystone3_Hwi_vectors
+ mov r1, #0 ; Exeception Handler address
+ mov r2, #64 ; 64 bytes
+loop:
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ subs r2, r2, #4
+ bgt loop
+exit:
+ bx lr
+ .endasmfunc
+
+ .end
diff --git a/mcuss_demos/profiling/can/main_tirtos.c b/mcuss_demos/profiling/can/main_tirtos.c
index f35efee..6d0fb8e 100755
--- a/mcuss_demos/profiling/can/main_tirtos.c
+++ b/mcuss_demos/profiling/can/main_tirtos.c
@@ -184,9 +184,24 @@ int32_t local_moduleClockEnable(uint32_t moduleId)
return retVal;
}
-volatile uint32_t qwerty = 0x0;
+#if defined NO_BIOS_HOOK_FUNCTION
+#define MCU_ATCM_BASE (0x0U)
+extern const uint32_t ti_sysbios_family_arm_v7r_keystone3_Hwi_vectors[];
+#endif
+
+volatile uint32_t ccs_halt_flag = 0x0;
int main(void)
{
+#if defined NO_BIOS_HOOK_FUNCTION
+ /* In case we do not have a bios hook function to copy vectors to 0x0 like
+ mcuCopyVecs2Exc, then we can use a simple memcpy operation like below to
+ copy vecs from the linker specified location i.e
+ ti_sysbios_family_arm_v7r_keystone3_Hwi_vectors which is in ATCM to
+ 0x0 where R5F expects it to be. */
+ memcpy((void *)MCU_ATCM_BASE, (void *)&ti_sysbios_family_arm_v7r_keystone3_Hwi_vectors, 0x40);
+#endif
+
+ while(ccs_halt_flag);
/* Enable MCAN clocks. This is needed if the application is being loaded by
u-boot, as u-boot by default doesn't enable the MCAN modules.
@@ -215,8 +230,6 @@ int main(void)
BIOS_exit(0);
}
- while(qwerty);
-
CanApp_Startup();
CanApp_PowerAndClkSrc();
@@ -240,6 +253,7 @@ int main(void)
{
BIOS_exit(0);
}
+
BIOS_start(); /* does not return */
}
else
@@ -302,6 +316,7 @@ static void CanApp_Shutdown(void)
return;
}
+#define SCISERVER_COMMON_X509_HEADER_ADDR (0x41cffb00)
sint32 SetupSciServer(void)
{
@@ -310,31 +325,34 @@ sint32 SetupSciServer(void)
Sciserver_TirtosCfgPrms_t appPrms;
Sciclient_ConfigPrms_t clientPrms;
- appPrms.taskPriority[SCISERVER_TASK_USER_LO] = 1;
- appPrms.taskPriority[SCISERVER_TASK_USER_HI] = 4;
-
/* Sciclient needs to be initialized before Sciserver. Sciserver depends on
* Sciclient API to execute message forwarding */
- ret = Sciclient_configPrmsInit(&clientPrms);
if (ret == CSL_PASS)
{
- ret = Sciclient_init(&clientPrms);
+ ret = Sciclient_configPrmsInit(&clientPrms);
}
if (ret == CSL_PASS)
{
- ret = Sciserver_tirtosInit(&appPrms);
+ ret = Sciclient_boardCfgParseHeader(
+ (uint8_t *)SCISERVER_COMMON_X509_HEADER_ADDR,
+ &clientPrms.inPmPrms, &clientPrms.inRmPrms);
}
if (ret == CSL_PASS)
{
- AppUtils_Printf(MSG_NORMAL, "Starting Sciserver..... PASSED\n");
+ ret = Sciclient_init(&clientPrms);
}
- else
+
+ ret = Sciserver_tirtosInitPrms_Init(&appPrms);
+
+ appPrms.taskPriority[SCISERVER_TASK_USER_LO] = 4;
+ appPrms.taskPriority[SCISERVER_TASK_USER_HI] = 5;
+
+ if (ret == CSL_PASS)
{
- AppUtils_Printf(MSG_NORMAL, "Starting Sciserver..... FAILED\n");
+ ret = Sciserver_tirtosInit(&appPrms);
}
-
#endif
return ret;
}
diff --git a/mcuss_demos/profiling/can/makefile b/mcuss_demos/profiling/can/makefile
index a3d59d7..d2bb32a 100755
--- a/mcuss_demos/profiling/can/makefile
+++ b/mcuss_demos/profiling/can/makefile
@@ -54,7 +54,7 @@ SRCS_COMMON += app_utils_can.c
# Enable copy of vectors
ifeq ($(ISA),$(filter $(ISA), r5f))
- SRCS_ASM_COMMON += utilsCopyVecs2ATcm.asm
+ SRCS_ASM_COMMON += utilsCopyVecs2ATcm.asm mcuCopyVecs2Exc.asm
endif
PACKAGE_SRCS_COMMON = .
diff --git a/mcuss_demos/profiling/can/overrides/j721e/mcu1_0/linker_r5_sysbios.lds b/mcuss_demos/profiling/can/overrides/j721e/mcu1_0/linker_r5_sysbios.lds
index 162689b..5ff92c9 100755
--- a/mcuss_demos/profiling/can/overrides/j721e/mcu1_0/linker_r5_sysbios.lds
+++ b/mcuss_demos/profiling/can/overrides/j721e/mcu1_0/linker_r5_sysbios.lds
@@ -17,7 +17,7 @@
--retain="*(.intvecs)"
--retain="*(.intc_text)"
--retain="*(.rstvectors)"
---retain="*(.utilsCopyVecsToAtcm)"
+--retain="*(.mcuCopyVecsToExc)"
--fill_value=0
-e __VECS_ENTRY_POINT
/*----------------------------------------------------------------------------*/
@@ -44,7 +44,8 @@ MEMORY
/* MCU0_R5F_0 SoC view */
MCU0_R5F0_ATCM (RWIX) : origin=0x41000000 length=0x8000
- MCU0_R5F0_BTCM (RWIX) : origin=0x41010000 length=0x8000
+ MCU0_R5F0_BTCM_VECS (RWIX) : origin=0x41010000 length=0x0100
+ MCU0_R5F0_BTCM (RWIX) : origin=0x41010100 length=0x7F00
/* MCU0_R5F_1 SoC view */
MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
@@ -59,7 +60,7 @@ MEMORY
DDR0 (RWIX) : origin=0x80000000 length=0x8000000 /* 2GB */
/* Used in this file */
- DDR0_MCU_1_0 (RWIX) : origin=0x97000000 length=0x1000000 /* 16MB */
+ DDR0_MCU_1_0 (RWIX) : origin=0xA0100000 length=0xF00000 /* 16MB */
/* Refer the user guide for details on persistence of these sections */
@@ -79,36 +80,41 @@ SECTIONS
{
.vecs : {
__VECS_ENTRY_POINT = .;
- } palign(8) > MCU0_R5F0_BTCM
- .intvecs : {} palign(8) > RESET_VECTORS
- .intc_text : {} palign(8) > RESET_VECTORS
- .rstvectors : {} palign(8) > RESET_VECTORS
- .text : {} palign(8) > OCMC_RAM_SCISERVER
- .const : {} palign(8) > MSMC3
- .cinit : {} palign(8) > OCMC_RAM
- .pinit : {} palign(8) > OCMC_RAM
-
- /* For NDK packet memory, we need to map this sections before .bss*/
- .bss:NDK_MMBUFFER (NOLOAD) {} ALIGN (128) > OCMC_RAM_SCISERVER
- .bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > OCMC_RAM_SCISERVER
-
- .bss : {} align(4) > MSMC3
- .far : {} align(4) > MSMC3
- .data : {} palign(128) > MSMC3
- .data_buffer: {} palign(128) > MSMC3
- .sysmem : {} > MSMC3
- .stack : {} align(4) > MSMC3 (HIGH) fill=FILL_PATTERN
- .utilsCopyVecsToAtcm : {} palign(8) > MCU0_R5F0_BTCM
- .bss.devgroup* : {} align(4) > MSMC3
- .const.devgroup*: {} align(4) > MSMC3
- .data_user : {} align(4) > OCMC_RAM_SCISERVER
- .boardcfg_data : {} align(4) > OCMC_RAM_SCISERVER
+ } palign(8) > MCU0_R5F0_BTCM_VECS
+
+ .text_boot {
+ *boot.aer5f*<*boot.o*>(.text)
+ } palign(8) > MCU0_R5F0_BTCM
+ .text:xdc_runtime_Startup_reset__I : {} palign(8) > MCU0_R5F0_BTCM
+ .text:ti_sysbios_family_arm_v7r_Cache* : {} palign(8) > MCU0_R5F0_BTCM
+ .text:ti_sysbios_family_arm_MPU* : {} palign(8) > MCU0_R5F0_BTCM
+
+ .intvecs : {} palign(8) > MCU0_R5F0_BTCM
+ .intc_text : {} palign(8) > MCU0_R5F0_BTCM
+ .rstvectors : {} palign(8) > MCU0_R5F0_BTCM
+ .text : {} palign(8) > DDR0_MCU_1_0
+ .const : {} palign(8) > DDR0_MCU_1_0
+ .cinit : {} palign(8) > DDR0_MCU_1_0
+ .pinit : {} palign(8) > DDR0_MCU_1_0
+
+ .bss : {} align(4) > DDR0_MCU_1_0
+ .far : {} align(4) > DDR0_MCU_1_0
+ .data : {} palign(128) > DDR0_MCU_1_0
+ .data_buffer: {} palign(128) > DDR0_MCU_1_0
+ .sysmem : {} > DDR0_MCU_1_0
+ .stack : {} align(4) > DDR0_MCU_1_0 (HIGH) fill=FILL_PATTERN
+ //.utilsCopyVecsToAtcm : {} palign(8) > MCU0_R5F0_BTCM
+ .mcuCopyVecsToExc : {} palign(8) > MCU0_R5F0_BTCM
+ .bss.devgroup* : {} align(4) > DDR0_MCU_1_0
+ .const.devgroup*: {} align(4) > DDR0_MCU_1_0
+ .data_user : {} align(4) > DDR0_MCU_1_0
+ .boardcfg_data : {} align(4) > DDR0_MCU_1_0
/* USB or any other LLD buffer for benchmarking */
- .benchmark_buffer (NOLOAD) {} ALIGN (8) > OCMC_RAM_SCISERVER
+ .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0_MCU_1_0
/* Additional sections settings */
- McalTextSection : fill=FILL_PATTERN, align=4, load > OCMC_RAM_SCISERVER
+ McalTextSection : fill=FILL_PATTERN, align=4, load > DDR0_MCU_1_0
{
.=align(4);
__linker_spi_text_start = .;
@@ -198,7 +204,7 @@ SECTIONS
__linker_cdd_ipc_text_end = .;
}
- McalConstSection : fill=FILL_PATTERN, align=4, load > OCMC_RAM_SCISERVER
+ McalConstSection : fill=FILL_PATTERN, align=4, load > DDR0_MCU_1_0
{
.=align(4);
__linker_spi_const_start = .;
@@ -293,7 +299,7 @@ SECTIONS
__linker_cdd_ipc_const_end = .;
}
- McalInitSection : fill=FILL_PATTERN, align=4, load > OCMC_RAM_SCISERVER
+ McalInitSection : fill=FILL_PATTERN, align=4, load > DDR0_MCU_1_0
{
.=align(4);
__linker_spi_init_start = .;
@@ -379,7 +385,7 @@ SECTIONS
. += FILL_LENGTH;
__linker_cdd_ipc_init_end = .;
}
- McalNoInitSection : fill=FILL_PATTERN, align=4, load > OCMC_RAM_SCISERVER, type = NOINIT
+ McalNoInitSection : fill=FILL_PATTERN, align=4, load > DDR0_MCU_1_0, type = NOINIT
{
.=align(4);
__linker_spi_no_init_start = .;
@@ -464,7 +470,7 @@ SECTIONS
}
/* Example Utility specifics */
- VariablesAlignedNoInitSection : align=8, load > OCMC_RAM_SCISERVER, type = NOINIT
+ VariablesAlignedNoInitSection : align=8, load > DDR0_MCU_1_0, type = NOINIT
{
.=align(8);
__linker_cdd_ipc_no_init_align_8b_start = .;
@@ -475,7 +481,7 @@ SECTIONS
__linker_cdd_ipc_no_init_align_8b_end = .;
}
/* Example Utility specifics */
- UtilityNoInitSection : align=4, load > OCMC_RAM, type = NOINIT
+ UtilityNoInitSection : align=4, load > DDR0_MCU_1_0, type = NOINIT
{
.=align(4);
__linker_utility_no_init_start = .;
@@ -485,7 +491,7 @@ SECTIONS
. += FILL_LENGTH;
__linker_utility_no_init_end = .;
}
- SciClientBoardCfgSection : align=128, load > OCMC_RAM_SCISERVER, type = NOINIT
+ SciClientBoardCfgSection : align=128, load > DDR0_MCU_1_0, type = NOINIT
{
.=align(128);
__linker_boardcfg_data_start = .;
@@ -496,8 +502,8 @@ SECTIONS
__linker_boardcfg_data_end = .;
}
/* This section is used for descs and ring mems. It's best to have
- * it in OCMRAM or OCMC_RAM_SCISERVER */
- McalUdmaSection : fill=FILL_PATTERN, align=128, load > OCMC_RAM_SCISERVER
+ * it in OCMRAM or DDR0_MCU_1_0 */
+ McalUdmaSection : fill=FILL_PATTERN, align=128, load > DDR0_MCU_1_0
{
.=align(128);
__linker_eth_udma_start = .;
@@ -507,7 +513,7 @@ SECTIONS
. += FILL_LENGTH;
__linker_eth_udma_end = .;
}
- McalTxDataSection : fill=FILL_PATTERN, align=128, load > OCMC_RAM_SCISERVER, type = NOINIT
+ McalTxDataSection : fill=FILL_PATTERN, align=128, load > DDR0_MCU_1_0, type = NOINIT
{
.=align(128);
__linker_eth_tx_data_start = .;
@@ -517,7 +523,7 @@ SECTIONS
. += FILL_LENGTH;
__linker_eth_tx_data_end = .;
}
- McalRxDataSection : fill=FILL_PATTERN, align=128, load > OCMC_RAM_SCISERVER, type = NOINIT
+ McalRxDataSection : fill=FILL_PATTERN, align=128, load > DDR0_MCU_1_0, type = NOINIT
{
.=align(128);
__linker_eth_rx_data_start = .;
diff --git a/mcuss_demos/profiling/can/overrides/j721e/mcu1_0/sysbios_r5f.cfg b/mcuss_demos/profiling/can/overrides/j721e/mcu1_0/sysbios_r5f.cfg
index 9d40cf5..8e69c6c 100755
--- a/mcuss_demos/profiling/can/overrides/j721e/mcu1_0/sysbios_r5f.cfg
+++ b/mcuss_demos/profiling/can/overrides/j721e/mcu1_0/sysbios_r5f.cfg
@@ -213,7 +213,7 @@ if((coreId=="mcu2_0") || (coreId=="mcu2_1") || (coreId=="mcu3_0") || (coreId=="m
}
var Reset = xdc.useModule("xdc.runtime.Reset");
-Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm";
+Reset.fxns[Reset.fxns.length++] = "&mcuCopyVecs2Exc";
/*
* Initialize MPU and enable it
--
2.17.1
我们不需要对 MCU2_1应用更改、对吧？ 因为顶部连接的线程中已经存在不同的补丁。我仅像上面一样应用了 mcu1_0。
3]根据建议的修补程序附加了我已进行更改的文件，同时还附加了 K3-j721e-common-proc-board.dts 中的更改
e2e.ti.com/.../MCU1_5F00_0_5F00_patch_5F00_applied.zip
需要优先执行此任务。 请提供帮助，告诉我哪里出错了。
如果您需要，我还会补充更多的输入。
此致、
Ketaki
