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[参考译文] AM6442：在 AM6442 R5 spl 初始 DDR 之后、测试 memcpy 失败

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Other Parts Discussed in Thread: SYSCONFIG, AM2434, AM6442

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail

器件型号：AM6442
Thread 中讨论的其他器件：SysConfig、 AM2434、

大家好、

我们在定制板上遇到了随机现象、即在 R5 spl 初始 DDR 之后、DDR 测试 memcpy 失败。

我们将 memcpy 10 8位数｛0x12、0x34、0x56、0x78、0x9a、0xbc、0xde、0x5a、0xa5、0xff｝更改为 DDR 范围0x8000000000-0x8000000009、然后从 DDR 范围 0x8000000000-0x8000000009进行读取。以下三个现象：

①奇数地址的值为 RIGHT，、但偶数地址的值为0x0。

DDR 测试失败！从 DDR 地址0x8000000读取值= 0x0、而写入值= 0x12
DDR 测试失败！当写入值= 0x56时、从 DDR 地址：0x800002，读取值= 0x0
DDR 测试失败！从 DDR addr：0x800004读取值= 0x0、而写入值= 0x9a
DDR 测试失败！从 DDR 地址0x800006读取值= 0x0、而写入值= 0xDE
DDR 测试失败！从 DDR 地址0x800008读取值= 0x0、而写入值= 0xA5

② 奇数和偶数地址的值错误为0x0。

DDR 测试失败！从 DDR 地址0x8000000读取值= 0x0、而写入值= 0x12
DDR 测试失败！从 DDR 地址0x80000001读取值= 0x0、而写入值= 0x34
DDR 测试失败！从 DDR 地址0x800002读取值= 0x0、而写入值= 0x56
DDR 测试失败！从 DDR 地址0x800003读取值= 0x0、而写入值= 0x78
DDR 测试失败！从 DDR addr：0x800004读取值= 0x0、而写入值= 0x9a
DDR 测试失败！从 DDR addr：0x800005读取值= 0x0、而写入值= 0xbc
DDR 测试失败！从 DDR 地址0x800006读取值= 0x0、而写入值= 0xDE
DDR 测试失败！从 DDR 地址：0x80000007读取值= 0x0、而写入值= 0x5a
DDR 测试失败！从 DDR 地址0x800008读取值= 0x0、而写入值= 0xA5
DDR 测试失败！从 DDR addr：0x800009读取值= 0x0、而写入值= 0xff

③ 奇数和偶数地址的值是正确的。

没有错误日志、可以成功引导。

硬件 SCH、如下所示

我们在定制板上使用 Linux 处理器 SDK 8.4、DDR 为 MT40A1G16KD-062E IT：E、与 AM64x EVM 板相同。

因此、我们不会在 SDK 源代码中更改 DDR 配置参数。

我们通过联机 SysConfig 工具配置 DDR 参数、如果我们要测试这些参数、应该怎么做？

对于这个问题、您有什么建议吗？

谢谢、

jimin.Li

0 admin 3 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

Jimin、从原理图中看不到任何明显的问题。您是否遵循了 https://www.ti.com/lit/pdf/spracu1中的布局规则？

您是否具有电路板的 JTAG 访问权限？如果是、您能否运行 GEL 脚本 AM64 DDRSS 内存调试-> AM64_DDRSS_CTL_PI_PHY_RegDump 并发布结果。

您如何运行这些测试？从 CCS？ U-boot？内核？

此致、

James

0 admin 3 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 JJD：

感谢您的回复！

是的、硬件团队在 DDR 布局之后通过了 SIT。

[引用 userid="1187" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4411987 #4411987"]您是否遵循了 https://www.ti.com/lit/pdf/spracu1中的布局规则？

是的、我可以通过 JTAG 访问我们的电路板。但我发现 AM64_DDRSS_CTL_PI_PHY_RegDump ()无法评估。运行 AM64 DDRSS AM64_DDRSS_RegDump.gel 时的详细信息如下所示

[引用 userid="1187" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4411987 #4411987">您是否具有电路板的 JTAG 访问权限？如果是这样、您能否运行 GEL 脚本 AM64 DDRSS 内存调试-> AM64_DDRSS_CTL_PI_PHY_RegDump 并发布结果。[/quot]

我们在 R5 spl 中执行这些 DDR 测试(DDR memcpy 测试代码添加在 uclass_get_device (UCLASS_RAM、0、&dev)之后； FUNC：board_init_f 文件： SDK 从 Linux 处理器安装路径/board-support/u-boot-2021.01+gitxxxx/arch/arm/mach-k3/am642_sdk)

[引用 userid="1187" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4411987 #4411987">您如何运行这些测试？从 CCS？ U-boot？内核？

谢谢、

jimin.Li

0 admin 3 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 JJD：

如果我运行 AM64x_GP_EVM.gel 脚本、则获取 AM64_DDRSS_CTL_PI_PHY_RegDump、如下所示：

MAIN_Cortex_R5_0_0：GEL 输出：从 R5运行
MAIN_Cortex_R5_0_0：GEL 输出：

通过 R5连接未初始化 DDR。

转至"Scripts -> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled"菜单以初始化 DDR。

===

MAIN_Cortex_R5_0_0：GEL 输出：0x0F308000 0x10460A01 //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308004 0x5D1AF3C3 //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308008 0x0171A610 //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30800C 0x40020A11 //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308010 0x00052006 //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308014 0x02050020 //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308018 0x03070101 //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30801C 0x000890B8 //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308020 0x00000000 //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308024 0x00000000 //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308028 0x00000000 //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30802C 0x000890B8 //DDRSS_CTL_11_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308030 0x00000000 //DDRSS_CTL_12_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308034 0x00000000 //DDRSS_CTL_13_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308038 0x00000000 //DDRSS_CTL_14_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30803C 0x000890B8 //DDRSS_CTL_15_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308040 0x00000000 //DDRSS_CTL_16_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308044 0x00000000 //DDRSS_CTL_17_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308048 0x00000000 //DDRSS_CTL_18_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30804C 0x01010100 //DDRSS_CTL_19_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308050 0x01000101 // DDRSS_CTL_20_data
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308054 0x01000110 //DDRSS_CTL_21_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308058 0x02010002 //DDRSS_CTL_22_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30805C 0x00027100 //DDRSS_CTL_23_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308060 0x00061A80 //DDRSS_CTL_24_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308064 0x02550255 //DDRSS_CTL_25_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308068 0x00000255 //DDRSS_CTL_26_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30806C 0x00000000 //DDRSS_CTL_27_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308070 0x00000000 //DDRSS_CTL_28_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308074 0x00000000 //DDRSS_CTL_29_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308078 0x00000000 //DDRSS_CTL_30_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30807C 0x00000000 //DDRSS_CTL_31_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308080 0x00000000 //DDRSS_CTL_32_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308084 0x00000000 //DDRSS_CTL_33_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308088 0x00000000 //DDRSS_CTL_34_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30808C 0x00000000 //DDRSS_CTL_35_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308090 0x00000000 //DDRSS_CTL_36_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308094 0x00000000 //DDRSS_CTL_37_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308098 0x0400091C //DDRSS_CTL_38_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30809C 0x1C1C1C1C //DDRSS_CTL_39_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080A0 0x0400091C //DDRSS_CTL_40_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080A4 0x1C1C1C1C //DDRSS_CTL_41_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080A8 0x0400091C //DDRSS_CTL_42_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080AC 0x1C1C1C1C //DDRSS_CTL_43_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080B0 0x050404 //DDRSS_CTL_44_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080B4 0x00002706 //DDRSS_CTL_45_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080B8 0x0602001D //DDRSS_CTL_46_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080BC 0x05001D0B //DDRSS_CTL_47_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080C0 0x00270605 //DDRSS_CTL_48_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080C4 0x0602001D //DDRSS_CTL_49_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080C8 0x05001D0B //DDRSS_CTL_50_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080CC 0x00270605 //DDRSS_CTL_51_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080D0 0x0602001D //DDRSS_CTL_52_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080D4 0x07001D0B //DDRSS_CTL_53_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080D8 0x00180807 //DDRSS_CTL_54_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080DC 0x0400DB60 //DDRSS_CTL_55_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080E0 0x07070009 //DDRSS_CTL_56_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080E4 0x00001808 //DDRSS_CTL_57_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080E8 0x0400DB60 //DDRSS_CTL_58_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080EC 0x07070009 //DDRSS_CTL_59_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080F0 0x00001808 //DDRSS_CTL_60_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080F4 0x0400DB60 //DDRSS_CTL_61_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080F8 0x03000009 //DDRSS_CTL_62_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3080FC 0x0D0C0002 //DDRSS_CTL_63_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308100 0x0D0C0D0C //DDRSS_CTL_64_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308104 0x01010000 // DDRSS_CTL_65_data
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308108 0x03191919 //DDRSS_CTL_66_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30810C 0x0B0B0B0B //DDRSS_CTL_67_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308110 0x00000B0B //DDRSS_CTL_68_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308114 0x00000101 //DDRSS_CTL_69_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308118 0x00000000 //DDRSS_CTL_70_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30811C 0x01000000 //DDRSS_CTL_71_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308120 0x01180803 //DDRSS_CTL_72_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308124 0x00001860 // DDRSS_CTL_73_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308128 0x00000118 //DDRSS_CTL_74_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30812C 0x00001860 // DDRSS_CTL_75_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308130 0x00000118 //DDRSS_CTL_76_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308134 0x00001860 //DDRSS_CTL_77_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308138 0x00000005 //DDRSS_CTL_78_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30813C 0x00000000 //DDRSS_CTL_79_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308140 0x00000000 //DDRSS_CTL_80_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308144 0x00000000 //DDRSS_CTL_81_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308148 0x00000000 //DDRSS_CTL_82_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30814C 0x00000000 //DDRSS_CTL_83_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308150 0x00000000 //DDRSS_CTL_84_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308154 0x00000000 //DDRSS_CTL_85_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308158 0x00000000 //DDRSS_CTL_86_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30815C 0x00090009 //DDRSS_CTL_87_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308160 0x00000009 //DDRSS_CTL_88_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308164 0x00000000 //DDRSS_CTL_89_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308168 0x00000000 //DDRSS_CTL_90_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30816C 0x00000000 //DDRSS_CTL_91_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308170 0x00000000 //DDRSS_CTL_92_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308174 0x00000000 //DDRSS_CTL_93_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308178 0x00010001 //DDRSS_CTL_94_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30817C 0x00025501 //DDRSS_CTL_95_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308180 0x02550120 //DDRSS_CTL_96_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308184 0x02550120 //DDRSS_CTL_97_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308188 0x01200120 //DDRSS_CTL_98_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30818C 0x01200120 //DDRSS_CTL_99_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308190 0x00000000 //DDRSS_CTL_100_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308194 0x00000000 //DDRSS_CTL_101_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308198 0x00000000 //DDRSS_CTL_102_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30819C 0x00000000 //DDRSS_CTL_103_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081A0 0x00000000 //DDRSS_CTL_104_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081A4 0x00000000 //DDRSS_CTL_105_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081A8 0x03010000 //DDRSS_CTL_106_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081AC 0x00010000 //DDRSS_CTL_107_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081B0 0x00000000 //DDRSS_CTL_108_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081B4 0x01000000 //DDRSS_CTL_109_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081B8 0x80104002 //DDRSS_CTL_110_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081BC 0x00040003 //DDRSS_CTL_111_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081C0 0x00040005 //DDRSS_CTL_112_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081C4 0x00030000 //DDRSS_CTL_113_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081C8 0x00050004 //DDRSS_CTL_114_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081CC 0x00000004 //DDRSS_CTL_115_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081D0 0x00040003 //DDRSS_CTL_116_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081D4 0x00040005 //DDRSS_CTL_117_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081D8 0x00000000 //DDRSS_CTL_118_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081DC 0x00061800 //DDRSS_CTL_119_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081E0 0x00061800 //DDRSS_CTL_120_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081E4 0x00061800 //DDRSS_CTL_121_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081E8 0x00061800 //DDRSS_CTL_122_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081EC 0x00061800 //DDRSS_CTL_123_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081F0 0x00000000 //DDRSS_CTL_124_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081F4 0x0000AAA0 //DDRSS_CTL_125_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081F8 0x00061800 //DDRSS_CTL_126_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3081FC 0x00061800 //DDRSS_CTL_127_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308200 0x00061800 //DDRSS_CTL_128_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308204 0x00061800 //DDRSS_CTL_129_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308208 0x00061800 //DDRSS_CTL_130_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30820C 0x00000000 //DDRSS_CTL_131_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308210 0x0000AAA0 // DDRSS_CTL_132_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308214 0x00061800 //DDRSS_CTL_133_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308218 0x00061800 //DDRSS_CTL_134_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30821C 0x00061800 //DDRSS_CTL_135_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308220 0x00061800 //DDRSS_CTL_136_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308224 0x00061800 //DDRSS_CTL_137_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308228 0x00000000 //DDRSS_CTL_138_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30822C 0x0000AAA0 // DDRSS_CTL_139_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308230 0x00000000 //DDRSS_CTL_140_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308234 0x00000000 //DDRSS_CTL_141_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308238 0x00000000 //DDRSS_CTL_142_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30823C 0x00000000 //DDRSS_CTL_143_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308240 0x00000000 //DDRSS_CTL_144_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308244 0x00000000 //DDRSS_CTL_145_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308248 0x00000000 //DDRSS_CTL_146_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30824C 0x00000000 //DDRSS_CTL_147_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308250 0x00000000 //DDRSS_CTL_148_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308254 0x00000000 //DDRSS_CTL_149_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308258 0x00000000 //DDRSS_CTL_150_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30825C 0x00000000 //DDRSS_CTL_151_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308260 0x00000000 //DDRSS_CTL_152_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308264 0x00000000 //DDRSS_CTL_153_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308268 0x00000000 //DDRSS_CTL_154_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30826C 0x00000000 //DDRSS_CTL_155_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308270 0x080C0000 //DDRSS_CTL_156_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308274 0x080C080C //DDRSS_CTL_157_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308278 0x00000000 //DDRSS_CTL_158_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30827C 0x07010A09 //DDRSS_CTL_159_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308280 0x000E0A09 //DDRSS_CTL_160_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308284 0x010A0900 //DDRSS_CTL_161_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308288 0x0E0A0907 //DDRSS_CTL_162_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30828C 0x0A090000 //DDRSS_CTL_163_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308290 0x0A090701 //DDRSS_CTL_164_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308294 0x0000000E //DDRSS_CTL_165_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308298 0x00040003 //DDRSS_CTL_166_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30829C 0x00004007 //DDRSS_CTL_167_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082A0 0x00000000 //DDRSS_CTL_168_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082A4 0x00000000 //DDRSS_CTL_169_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082A8 0x00000000 //DDRSS_CTL_170_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082AC 0x00000000 //DDRSS_CTL_171_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082B0 0x00000000 //DDRSS_CTL_172_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082B4 0x00000000 //DDRSS_CTL_173_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082B8 0x01000000 //DDRSS_CTL_174_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082BC 0x00000000 //DDRSS_CTL_175_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082C0 0x00001500 //DDRSS_CTL_176_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082C4 0x0000100E //DDRSS_CTL_177_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082C8 0x00000000 //DDRSS_CTL_178_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082CC 0x00000000 //DDRSS_CTL_179_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082D0 0x00000001 //DDRSS_CTL_180_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082D4 0x00000002 //DDRSS_CTL_181_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082D8 0x00000C00 //DDRSS_CTL_182_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082DC 0x00001000 //DDRSS_CTL_183_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082E0 0x00000C00 //DDRSS_CTL_184_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082E4 0x00001000 // DDRSS_CTL_185_data
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082E8 0x00000C00 //DDRSS_CTL_186_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082EC 0x00001000 //DDRSS_CTL_187_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082F0 0x00000000 //DDRSS_CTL_188_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082F4 0x00000000 //DDRSS_CTL_189_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082F8 0x00000000 //DDRSS_CTL_190_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3082FC 0x00000000 //DDRSS_CTL_191_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308300 0x00000000 //DDRSS_CTL_192_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308304 0x00000000 //DDRSS_CTL_193_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308308 0x00000000 //DDRSS_CTL_194_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30830C 0x00000000 //DDRSS_CTL_195_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308310 0x00000000 //DDRSS_CTL_196_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308314 0x00000000 //DDRSS_CTL_197_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308318 0x00000000 //DDRSS_CTL_198_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30831C 0x00000000 //DDRSS_CTL_199_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308320 0x00000000 //DDRSS_CTL_200_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308324 0x00000000 //DDRSS_CTL_201_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308328 0x00000000 //DDRSS_CTL_202_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30832C 0x00000000 //DDRSS_CTL_203_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308330 0x00042400 //DDRSS_CTL_204_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308334 0x00000301 //DDRSS_CTL_205_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308338 0x00000000 //DDRSS_CTL_206_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30833C 0x00000424 //DDRSS_CTL_207_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308340 0x00000301 //DDRSS_CTL_208_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308344 0x00000000 //DDRSS_CTL_209_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308348 0x00000424 // DDRSS_CTL_210_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30834C 0x00000301 //DDRSS_CTL_211_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308350 0x00000000 //DDRSS_CTL_212_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308354 0x00000424 // DDRSS_CTL_213_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308358 0x00000301 //DDRSS_CTL_214_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30835C 0x00000000 //DDRSS_CTL_215_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308360 0x00000424 // DDRSS_CTL_216_data
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308364 0x00000301 //DDRSS_CTL_217_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308368 0x00000000 //DDRSS_CTL_218_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30836C 0x00000424 // DDRSS_CTL_219_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308370 0x00000301 //DDRSS_CTL_220_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308374 0x00000000 //DDRSS_CTL_221_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308378 0x00000000 //DDRSS_CTL_222_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30837C 0x00000000 //DDRSS_CTL_223_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308380 0x00000000 //DDRSS_CTL_224_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308384 0x00000000 //DDRSS_CTL_225_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308388 0x00000000 //DDRSS_CTL_2226_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30838C 0x00000000 //DDRSS_CTL_227_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308390 0x00000000 //DDRSS_CTL_228_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308394 0x00000000 //DDRSS_CTL_229_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308398 0x00000000 //DDRSS_CTL_230_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30839C 0x00000000 //DDRSS_CTL_231_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083A0 0x00000000 //DDRSS_CTL_232_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083A4 0x00000000 //DDRSS_CTL_233_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083A8 0x00000000 //DDRSS_CTL_234_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083AC 0x00000000 //DDRSS_CTL_235_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083B0 0x00001401 //DDRSS_CTL_236_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083B4 0x00001401 //DDRSS_CTL_237_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083B8 0x00001401 //DDRSS_CTL_238_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083BC 0x00001401 //DDRSS_CTL_239_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083C0 0x00001401 //DDRSS_CTL_240_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083C4 0x00001401 //DDRSS_CTL_241_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083C8 0x00000493 //DDRSS_CTL_242_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083CC 0x00000493 //DDRSS_CTL_243_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083D0 0x00000493 //DDRSS_CTL_244_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083D4 0x00000493 //DDRSS_CTL_245_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083D8 0x00000493 //DDRSS_CTL_246_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083DC 0x00000493 //DDRSS_CTL_247_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083E0 0x00000000 //DDRSS_CTL_248_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083E4 0x00000000 //DDRSS_CTL_249_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083E8 0x00000000 //DDRSS_CTL_250_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083EC 0x00000000 //DDRSS_CTL_251_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083F0 0x00000000 //DDRSS_CTL_252_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083F4 0x00000000 //DDRSS_CTL_253_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083F8 0x00000000 //DDRSS_CTL_254_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3083FC 0x00000000 //DDRSS_CTL_255_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308400 0x00000000 //DDRSS_CTL_256_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308404 0x00000000 //DDRSS_CTL_257_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308408 0x00000000 //DDRSS_CTL_258_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30840C 0x00000000 //DDRSS_CTL_259_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308410 0x00000000 //DDRSS_CTL_260_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308414 0x00000000 //DDRSS_CTL_261_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308418 0x00000000 //DDRSS_CTL_262_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30841C 0x00000000 //DDRSS_CTL_263_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308420 0x00000000 //DDRSS_CTL_264_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308424 0x00000000 //DDRSS_CTL_265_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308428 0x00000000 //DDRSS_CTL_266_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30842C 0x00000000 //DDRSS_CTL_267_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308430 0x00000000 //DDRSS_CTL_268_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308434 0x00000000 //DDRSS_CTL_269_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308438 0x00000000 //DDRSS_CTL_270_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30843C 0x00000000 //DDRSS_CTL_271_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308440 0x00000000 //DDRSS_CTL_272_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308444 0x00000000 //DDRSS_CTL_273_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308448 0x00000000 //DDRSS_CTL_274_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30844C 0x00000000 //DDRSS_CTL_275_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308450 0x00000000 //DDRSS_CTL_276_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308454 0x00010000 // DDRSS_CTL_277_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308458 0x00000000 //DDRSS_CTL_278_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30845C 0x00000100 //DDRSS_CTL_279_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308460 0x00000000 //DDRSS_CTL_280_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308464 0x00000101 //DDRSS_CTL_281_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308468 0x00000000 //DDRSS_CTL_282_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30846C 0x00000000 //DDRSS_CTL_283_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308470 0x00000000 //DDRSS_CTL_284_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308474 0x00000000 //DDRSS_CTL_285_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308478 0x00000000 //DDRSS_CTL_286_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30847C 0x00000000 //DDRSS_CTL_287_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308480 0x00000000 //DDRSS_CTL_288_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308484 0x00000FFF //DDRSS_CTL_289_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308488 0x0C181511 //DDRSS_CTL_290_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30848C 0x00000304 //DDRSS_CTL_291_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308490 0x00000000 //DDRSS_CTL_292_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308494 0x00000000 //DDRSS_CTL_293_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308498 0x00000000 //DDRSS_CTL_294_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30849C 0x00000000 //DDRSS_CTL_295_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084A0 0x00000000 //DDRSS_CTL_296_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084A4 0x00000000 //DDRSS_CTL_297_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084A8 0x00000000 //DDRSS_CTL_298_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084AC 0x00000000 //DDRSS_CTL_299_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084B0 0x00000000 //DDRSS_CTL_300_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084B4 0x00000000 //DDRSS_CTL_301_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084B8 0x00000000 //DDRSS_CTL_302_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084BC 0x00000000 //DDRSS_CTL_303_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084C0 0x00000000 //DDRSS_CTL_304_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084C4 0x00040000 // DDRSS_CTL_305_data
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084C8 0x00800200 // DDRSS_CTL_306_data
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084CC 0x00000000 //DDRSS_CTL_307_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084D0 0x02000400 //DDRSS_CTL_308_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084D4 0x00000080 //DDRSS_CTL_309_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084D8 0x00040000 //DDRSS_CTL_310_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084DC 0x00800200 // DDRSS_CTL_311_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084E0 0x00000000 //DDRSS_CTL_312_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084E4 0x00000000 //DDRSS_CTL_313_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084E8 0x00000000 //DDRSS_CTL_314_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084EC 0x00000100 //DDRSS_CTL_315_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084F0 0x01010000 // DDRSS_CTL_316_data
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084F4 0x00000000 //DDRSS_CTL_317_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084F8 0x3FFF0000 //DDRSS_CTL_318_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3084FC 0x000FFF00 //DDRSS_CTL_319_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308500 0xFFFFFFFF //DDRSS_CTL_320_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308504 0x000FFF00 //DDRSS_CTL_321_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308508 0x0A000000 //DDRSS_CTL_322_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30850C 0x0001FFFF //DDRSS_CTL_323_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308510 0x01010101 // DDRSS_CTL_324_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308514 0x01010101 //DDRSS_CTL_325_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308518 0x00000118 //DDRSS_CTL_326_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30851C 0x00000C01 //DDRSS_CTL_327_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308520 0x00000000 //DDRSS_CTL_328_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308524 0x00000000 //DDRSS_CTL_329_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308528 0x00000000 //DDRSS_CTL_330_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30852C 0x01000000 //DDRSS_CTL_331_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308530 0x00000100 //DDRSS_CTL_332_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308534 0x00010000 //DDRSS_CTL_333_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308538 0x00000000 //DDRSS_CTL_334_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30853C 0x00000000 //DDRSS_CTL_335_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308540 0x00000000 //DDRSS_CTL_333_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308544 0x00000000 //DDRSS_CTL_337_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308548 0x00000000 //DDRSS_CTL_338_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30854C 0x00000000 //DDRSS_CTL_339_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308550 0x00000000 //DDRSS_CTL_340_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308554 0x00000000 //DDRSS_CTL_341_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308558 0x00000000 //DDRSS_CTL_342_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30855C 0x00000000 //DDRSS_CTL_343_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308560 0x00000000 //DDRSS_CTL_344_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308564 0x00000000 //DDRSS_CTL_345_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308568 0x00000000 //DDRSS_CTL_34A_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30856C 0x00000000 //DDRSS_CTL_347_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308570 0x00000000 //DDRSS_CTL_348_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308574 0x00000000 //DDRSS_CTL_349_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308578 0x00000000 //DDRSS_CTL_350_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30857C 0x00000000 //DDRSS_CTL_351_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308580 0x00000000 //DDRSS_CTL_352_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308584 0x00000000 //DDRSS_CTL_353_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308588 0x00000000 //DDRSS_CTL_354_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30858C 0x00000000 //DDRSS_CTL_355_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308590 0x00000000 //DDRSS_CTL_356_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308594 0x00000000 //DDRSS_CTL_357_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308598 0x00000000 //DDRSS_CTL_358_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30859C 0x00000000 //DDRSS_CTL_359_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085A0 0x00000000 //DDRSS_CTL_360_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085A4 0x00000000 //DDRSS_CTL_361_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085A8 0x00000000 //DDRSS_CTL_362_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085AC 0x00000000 //DDRSS_CTL_363_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085B0 0x00000000 //DDRSS_CTL_364_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085B4 0x7A4D1804 //DDRSS_CTL_365_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085B8 0x540006E1 //DDRSS_CTL_366_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085BC 0x7FF29DF0 //DDRSS_CTL_367_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085C0 0x00000000 //DDRSS_CTL_368_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085C4 0x00000000 //DDRSS_CTL_369_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085C8 0x0C000000 //DDRSS_CTL_370_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085CC 0x060C0606 //DDRSS_CTL_371_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085D0 0x060C06 //DDRSS_CTL_372_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085D4 0x00010101 //DDRSS_CTL_373_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085D8 0x02000000 //DDRSS_CTL_374_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085DC 0x05020101 //DDRSS_CTL_375_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085E0 0x00000505 //DDRSS_CTL_376_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085E4 0x02020200 // DDRSS_CTL_377_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085E8 0x02020202///DDRSS_CTL_378_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085EC 0x02020202 //DDRSS_CTL_379_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085F0 0x020202///DDRSS_CTL_380_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085F4 0x00000000 //DDRSS_CTL_381_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085F8 0x00000000 //DDRSS_CTL_382_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F3085FC 0x04000100 //DDRSS_CTL_383_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308600 0x1E000304 //DDRSS_CTL_384_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308604 0x000030C0 //DDRSS_CTL_385_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308608 0x00000200 // DDRSS_CTL_386\data
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30860C 0x00000200 // DDRSS_CTL_387_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308610 0x00000200 // DDRSS_CTL_388_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308614 0x00000200 // DDRSS_CTL_389_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308618 0x0000DB60 //DDRSS_CTL_390_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30861C 0x0001E780 //DDRSS_CTL_391_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308620 0x0C0D0302 //DDRSS_CTL_392_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308624 0x001E090A //DDRSS_CTL_393_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308628 0x000030C0 //DDRSS_CTL_394_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30862C 0x00000200 // DDRSS_CTL_395_data
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308630 0x00000200 // DDRSS_CTL_396_data
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308634 0x00000200 // DDRSS_CTL_397_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308638 0x00000200 // DDRSS_CTL_398_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30863C 0x0000DB60 //DDRSS_CTL_399_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308640 0x0001E780 //DDRSS_CTL_400_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308644 0x0C0D0302 //DDRSS_CTL_401_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308648 0x001E090A //DDRSS_CTL_402_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30864C 0x000030C0 //DDRSS_CTL_403_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308650 0x00000200 // DDRSS_CTL_404_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308654 0x00000200 // DDRSS_CTL_405_data
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308658 0x00000200 //DDRSS_CTL_406_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30865C 0x00000200 //DDRSS_CTL_407_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308660 0x0000DB60 //DDRSS_CTL_408_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308664 0x0001E780 //DDRSS_CTL_409_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308668 0x0C0D0302 //DDRSS_CTL_410_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30866C 0x0000090A //DDRSS_CTL_411_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308670 0x00000000 //DDRSS_CTL_412_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308674 0x0302000A //DDRSS_CTL_413_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308678 0x01000500 //DDRSS_CTL_414_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30867C 0x01010001 //DDRSS_CTL_415_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308680 0x00010001 //DDRSS_CTL_416_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308684 0x01010001 //DDRSS_CTL_417_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308688 0x02010000 //DDRSS_CTL_418_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30868C 0x00000200 //DDRSS_CTL_419_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308690 0x02000201 //DDRSS_CTL_420_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308694 0x00000000 //DDRSS_CTL_421_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F308698 0x00202020 //DDRSS_CTL_422_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A000 0x00000A01 //DDRSS_PI_0_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A004 0xAE8D79E2 //DDRSS_PI_1_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A008 0x0714B570 //DDRSS_PI_2_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A00C 0x01011387 //DDRSS_PI_3_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A010 0x00000001 //DDRSS_PI_4_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A014 0x00010064 // DDRSS_PI_5_data
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A018 0x00000000 //DDRSS_PI_6_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A01C 0x00000000 //DDRSS_PI_7_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A020 0x00000000 //DDRSS_PI_8_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A024 0x00047CB1 //DDRSS_PI_9_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A028 0x0000000F //DDRSS_PI_10_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A02C 0x00000000 //DDRSS_PI_11_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A030 0x00000000 //DDRSS_PI_12_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A034 0x00010001 //DDRSS_PI_13_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A038 0x00000000 //DDRSS_PI_14_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A03C 0x00010001 //DDRSS_PI_15_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A040 0x00000005 //DDRSS_PI_16_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A044 0x00010000 // DDRSS_PI_17_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A048 0x00000000 //DDRSS_PI_18_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A04C 0x00000000 //DDRSS_PI_19_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A050 0x00000000 //DDRSS_PI_20_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A054 0x00000000 //DDRSS_PI_21_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A058 0x00000000 //DDRSS_PI_22_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A05C 0x00000000 //DDRSS_PI_23_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A060 0x280D0001 //DDRSS_PI_24_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A064 0x00000000 //DDRSS_PI_25_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A068 0x00010000 // DDRSS_PI_26_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A06C 0x00003200 //DDRSS_PI_27_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A070 0x00000000 //DDRSS_PI_28_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A074 0x00000000 //DDRSS_PI_29_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A078 0x00060602 //DDRSS_PI_30_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A07C 0x00000000 //DDRSS_PI_31_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A080 0x00000000 //DDRSS_PI_32_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A084 0x00000000 //DDRSS_PI_33_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A088 0x00000001 //DDRSS_PI_34_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A08C 0x00000055 //DDRSS_PI_35_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A090 0x000000AA //DDRSS_PI_36_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A094 0x000000AD //DDRSS_PI_37_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A098 0x00000052 //DDRSS_PI_38_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A09C 0x0000006A //DDRSS_PI_39_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0A0 0x00000095 //DDRSS_PI_40_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0A4 0x00000095 //DDRSS_PI_41_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0A8 0x000000AD //DDRSS_PI_42_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0AC 0x00000000 //DDRSS_PI_43_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0B0 0x00000000 //DDRSS_PI_44_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0B4 0x00010100 //DDRSS_PI_45_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0B8 0x00000014 //DDRSS_PI_46_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0BC 0x000007D0 //DDRSS_PI_47_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0C0 0x00000300 //DDRSS_PI_48_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0C4 0x00000000 //DDRSS_PI_49_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0C8 0x00000000 //DDRSS_PI_50_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0CC 0x01000000 //DDRSS_PI_51_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0D0 0x00010101 //DDRSS_PI_52_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0D4 0x0100090C //DDRSS_PI_53_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0D8 0x00000000 //DDRSS_PI_54_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0DC 0x00010000 // DDRSS_PI_55_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0E0 0x00000000 //DDRSS_PI_56_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0E4 0x00000000 //DDRSS_PI_57_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0E8 0x00000000 //DDRSS_PI_58_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0EC 0x00000000 //DDRSS_PI_59_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0F0 0x00001400 //DDRSS_PI_60_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0F4 0x00000000 //DDRSS_PI_61_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0F8 0x01000000 //DDRSS_PI_62_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A0FC 0x00000404 //DDRSS_PI_63_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A100 0x00000001 //DDRSS_PI_64_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A104 0x0001010E //DDRSS_PI_65_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A108 0x02040100 //DDRSS_PI_66_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A10C 0x00010000 //DDRSS_PI_67_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A110 0x00000034 //DDRSS_PI_68_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A114 0x00000000 //DDRSS_PI_69_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A118 0x00000000 //DDRSS_PI_70_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A11C 0x00000000 //DDRSS_PI_71_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A120 0x00000000 //DDRSS_PI_72_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A124 0x00000000 //DDRSS_PI_73_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A128 0x00000000 //DDRSS_PI_74_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A12C 0x00000005 //DDRSS_PI_75_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A130 0x01000000 //DDRSS_PI_76_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A134 0x04000100 //DDRSS_PI_77_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A138 0x00020000 //DDRSS_PI_78_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A13C 0x00010002 //DDRSS_PI_79_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A140 0x00000001 //DDRSS_PI_80_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A144 0x00020001 //DDRSS_PI_81_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A148 0x00020002 //DDRSS_PI_82_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A14C 0x29C02000 //DDRSS_PI_83_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A150 0x00000000 //DDRSS_PI_84_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A154 0x00000000 //DDRSS_PI_85_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A158 0x00000000 //DDRSS_PI_86_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A15C 0x00000000 //DDRSS_PI_87_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A160 0x00000000 //DDRSS_PI_88_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A164 0x00000000 //DDRSS_PI_89_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A168 0x00000000 //DDRSS_PI_90_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A16C 0x00000300 //DDRSS_PI_91_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A170 0x0A090B0C //DDRSS_PI_92_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A174 0x04060708 //DDRSS_PI_93_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A178 0x01000005 //DDRSS_PI_94_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A17C 0x00000800 //DDRSS_PI_95_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A180 0x00000000 //DDRSS_PI_96_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A184 0x00010008 //DDRSS_PI_97_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A188 0x00000000 //DDRSS_PI_98_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A18C 0x0000AA00 //DDRSS_PI_99_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A190 0x00000000 //DDRSS_PI_100_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A194 0x00010000 // DDRSS_PI_101_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A198 0x00000000 //DDRSS_PI_102_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A19C 0x00000000 //DDRSS_PI_103_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1A0 0x00000000 //DDRSS_PI_104_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1A4 0x00000000 //DDRSS_PI_105_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1A8 0x00000000 //DDRSS_PI_106_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1AC 0x00000000 //DDRSS_PI_107_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1B0 0x00000000 //DDRSS_PI_108_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1B4 0x00000000 //DDRSS_PI_109_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1B8 0x00000000 //DDRSS_PI_110_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1BC 0x00000000 //DDRSS_PI_111_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1C0 0x00000000 //DDRSS_PI_112_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1C4 0x00000000 //DDRSS_PI_113_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1C8 0x00000000 //DDRSS_PI_114_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1CC 0x00000000 //DDRSS_PI_115_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1D0 0x00000000 //DDRSS_PI_116_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1D4 0x00000000 //DDRSS_PI_117_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1D8 0x00000000 //DDRSS_PI_118_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1DC 0x00000000 //DDRSS_PI_119_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1E0 0x00000000 //DDRSS_PI_120_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1E4 0x00000000 //DDRSS_PI_121_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1E8 0x00000000 //DDRSS_PI_122_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1EC 0x00000000 //DDRSS_PI_123_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1F0 0x00000008 //DDRSS_PI_124_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1F4 0x00000000 //DDRSS_PI_125_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1F8 0x00000000 //DDRSS_PI_126_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A1FC 0x00000000 //DDRSS_PI_127_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A200 0x00000000 //DDRSS_PI_128_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A204 0x00000000 //DDRSS_PI_129_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A208 0x00000000 //DDRSS_PI_130_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A20C 0x00000000 //DDRSS_PI_131_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A210 0x00000000 //DDRSS_PI_132_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A214 0x00010100 //DDRSS_PI_133_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A218 0x00000000 //DDRSS_PI_134_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A21C 0x00000000 //DDRSS_PI_135_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A220 0x00027100 //DDRSS_PI_136_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A224 0x00061A80 //DDRSS_PI_137_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A228 0x00000100 //DDRSS_PI_138_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A22C 0x00000000 //DDRSS_PI_139_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A230 0x00000000 //DDRSS_PI_140_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A234 0x00000000 //DDRSS_PI_141_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A238 0x00000000 //DDRSS_PI_142_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A23C 0x00000000 //DDRSS_PI_143_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A240 0x01000000 //DDRSS_PI_144_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A244 0x81010003 //DDRSS_PI_145_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A248 0x02000101 //DDRSS_PI_146_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A24C 0x01030101 //DDRSS_PI_147_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A250 0x00010400 //DDRSS_PI_148_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A254 0x06000105 //DDRSS_PI_149_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A258 0x01070001 //DDRSS_PI_150_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A25C 0x00000000 //DDRSS_PI_151_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A260 0x00000000 //DDRSS_PI_152_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A264 0x00000001 //DDRSS_PI_153_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A268 0x00010000 // DDRSS_PI_154_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A26C 0x00000000 //DDRSS_PI_155_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A270 0x00000000 //DDRSS_PI_156_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A274 0x00000000 //DDRSS_PI_157_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A278 0x00000000 //DDRSS_PI_158_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A27C 0x00010000 // DDRSS_PI_159_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A280 0x00000004 //DDRSS_PI_160_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A284 0x00000000 //DDRSS_PI_161_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A288 0x00000000 //DDRSS_PI_162_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A28C 0x00000000 //DDRSS_PI_163_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A290 0x00007800 //DDRSS_PI_164_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A294 0x00780078 //DDRSS_PI_165_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A298 0x001414 //DDRSS_PI_166_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A29C 0x0000003A //DDRSS_PI_167_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2A0 0x0000003A //DDRSS_PI_168_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2A4 0x0004003A //DDRSS_PI_169_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2A8 0x04000400 //DDRSS_PI_170_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2AC 0xC8040009 //DDRSS_PI_171_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2B0 0x0400091C //DDRSS_PI_172_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2B4 0x00091CC8 //DDRSS_PI_173_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2B8 0x001CC804 //DDRSS_PI_174_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2BC 0x00000118 //DDRSS_PI_175_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2C0 0x00001860 // DDRSS_PI_176_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2C4 0x00000118 //DDRSS_PI_177_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2C8 0x00001860 // DDRSS_PI_178_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2CC 0x00000118 //DDRSS_PI_179_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2D0 0x04001860 // DDRSS_PI_180_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2D4 0x01010404 //DDRSS_PI_181_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2D8 0x00001901 //DDRSS_PI_182_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2DC 0x00190019 //DDRSS_PI_183_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2E0 0x010C010C //DDRSS_PI_184_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2E4 0x0000010C //DDRSS_PI_185_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2E8 0x00000000 //DDRSS_PI_186_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2EC 0x05000000 //DDRSS_PI_187_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2F0 0x01010505 //DDRSS_PI_188_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2F4 0x01010101 //DDRSS_PI_189_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2F8 0x001818 //DDRSS_PI_190_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A2FC 0x00000000 //DDRSS_PI_191_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A300 0x00000000 //DDRSS_PI_192_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A304 0x0D000000 //DDRSS_PI_193_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A308 0x0A0D0D//DDRSS_PI_194_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A30C 0x03030A //DDRSS_PI_195_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A310 0x00000000 //DDRSS_PI_196_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A314 0x00000000 //DDRSS_PI_197_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A318 0x00000000 //DDRSS_PI_198_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A31C 0x00000000 //DDRSS_PI_199_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A320 0x00000000 //DDRSS_PI_200_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A324 0x00000000 //DDRSS_PI_201_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A328 0x00000000 //DDRSS_PI_202_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A32C 0x00000000 //DDRSS_PI_203_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A330 0x00000000 //DDRSS_PI_204_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A334 0x00000000 //DDRSS_PI_205_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A338 0x00000000 //DDRSS_PI_206_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A33C 0x00000000 //DDRSS_PI_207_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A340 0x00000000 //DDRSS_PI_208_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A344 0x0D090000 //DDRSS_PI_209_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A348 0x0D09000D //DDRSS_PI_210_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A34C 0x0D09000D //DDRSS_PI_211_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A350 0x0000000D //DDRSS_PI_212_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A354 0x00000000 //DDRSS_PI_213_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A358 0x00000000 //DDRSS_PI_214_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A35C 0x00000000 //DDRSS_PI_215_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A360 0x00000000 //DDRSS_PI_216_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A364 0x16000000 //DDRSS_PI_217_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A368 0x001600C8 //DDRSS_PI_218_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A36C 0x001600C8 //DDRSS_PI_219_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A370 0x010100C8 //DDRSS_PI_220_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A374 0x00001B01 //DDRSS_PI_221_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A378 0x1F0F0053 //DDRSS_PI_222_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A37C 0x05000001 //DDRSS_PI_223_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A380 0x001B0A0D //DDRSS_PI_224_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A384 0x1F0F0053 //DDRSS_PI_225_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A388 0x05000001 //DDRSS_PI_2226_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A38C 0x001B0A0D //DDRSS_PI_227_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A390 0x1F0F0053 //DDRSS_PI_228_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A394 0x05000001 //DDRSS_PI_229_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A398 0x00010A0D //DDRSS_PI_230_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A39C 0x0C0B0700 //DDRSS_PI_231_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3A0 0x000D0605 //DDRSS_PI_232_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3A4 0x0000C570 //DDRSS_PI_233_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3A8 0x0000001D //DDRSS_PI_234_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3AC 0x180A0800 //DDRSS_PI_235_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3B0 0x0B071C1C //DDRSS_PI_236_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3B4 0x0D06050C //DDRSS_PI_237_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3B8 0x0000C570 //DDRSS_PI_238_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3BC 0x0000001D //DDRSS_PI_239_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3C0 0x180A0800 //DDRSS_PI_240_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3C4 0x0B071C1C //DDRSS_PI_241_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3C8 0x0D06050C //DDRSS_PI_242_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3CC 0x0000C570 //DDRSS_PI_243_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3D0 0x0000001D //DDRSS_PI_244_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3D4 0x180A0800 //DDRSS_PI_245_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3D8 0x00001C1C //DDRSS_PI_246_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3DC 0x000030C0 //DDRSS_PI_247_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3E0 0x0001E780 //DDRSS_PI_248_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3E4 0x000030C0 //DDRSS_PI_249_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3E8 0x0001E780 //DDRSS_PI_250_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3EC 0x000030C0 //DDRSS_PI_251_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3F0 0x0001E780 //DDRSS_PI_252_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3F4 0x02550255 //DDRSS_PI_253_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3F8 0x030255 //DDRSS_PI_254_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A3FC 0x00025503 //DDRSS_PI_255_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A400 0x02550255 //DDRSS_PI_256_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A404 0x0C080C08 //DDRSS_PI_257_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A408 0x00000C08 //DDRSS_PI_258_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A40C 0x000890B8 //DDRSS_PI_259_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A410 0x00000000 //DDRSS_PI_260_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A414 0x00000000 //DDRSS_PI_261_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A418 0x00000000 //DDRSS_PI_262_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A41C 0x00000120 //DDRSS_PI_263_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A420 0x000890B8 //DDRSS_PI_264_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A424 0x00000000 //DDRSS_PI_265_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A428 0x00000000 //DDRSS_PI_266_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A42C 0x00000000 //DDRSS_PI_267_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A430 0x00000120 //DDRSS_PI_268_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A434 0x000890B8 //DDRSS_PI_269_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A438 0x00000000 //DDRSS_PI_270_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A43C 0x00000000 //DDRSS_PI_271_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A440 0x00000000 //DDRSS_PI_272_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A444 0x02000120 //DDRSS_PI_273_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A448 0x00000080 //DDRSS_PI_274_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A44C 0x00020000 //DDRSS_PI_275_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A450 0x00000080 //DDRSS_PI_276_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A454 0x00020000 //DDRSS_PI_277_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A458 0x00000080 //DDRSS_PI_278_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A45C 0x00000000 //DDRSS_PI_279_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A460 0x00000000 //DDRSS_PI_280_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A464 0x00040404 //DDRSS_PI_281_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A468 0x00000000 //DDRSS_PI_282_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A46C 0x02010102 //DDRSS_PI_283_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A470 0x67676767 //DDRSS_PI_284_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A474 0x00000202 //DDRSS_PI_285_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A478 0x00000000 //DDRSS_PI_286_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A47C 0x00000000 //DDRSS_PI_287_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A480 0x00000000 //DDRSS_PI_288_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A484 0x00000000 //DDRSS_PI_289_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A488 0x00000000 //DDRSS_PI_290_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A48C 0x0D100F00 //DDRSS_PI_291_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A490 0x0003020E //DDRSS_PI_292_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A494 0x00000001 //DDRSS_PI_293_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A498 0x01000000 //DDRSS_PI_294_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A49C 0x00020201 //DDRSS_PI_295_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4A0 0x00000000 //DDRSS_PI_296_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4A4 0x00000424 //DDRSS_PI_297_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4A8 0x00000301 //DDRSS_PI_298_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4AC 0x00000000 //DDRSS_PI_299_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4B0 0x00000000 //DDRSS_PI_300_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4B4 0x00000000 //DDRSS_PI_301_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4B8 0x00001401 //DDRSS_PI_302_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4BC 0x00000493 //DDRSS_PI_303_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4C0 0x00000000 //DDRSS_PI_304_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4C4 0x00000424 // DDRSS_PI_305_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4C8 0x00000301 //DDRSS_PI_306_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4CC 0x00000000 //DDRSS_PI_307_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4D0 0x00000000 //DDRSS_PI_308_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4D4 0x00000000 //DDRSS_PI_309_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4D8 0x00001401 //DDRSS_PI_310_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4DC 0x00000493 //DDRSS_PI_311_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4E0 0x00000000 //DDRSS_PI_312_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4E4 0x00000424 // DDRSS_PI_313_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4E8 0x00000301 //DDRSS_PI_314_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4EC 0x00000000 //DDRSS_PI_315_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4F0 0x00000000 //DDRSS_PI_316_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4F4 0x00000000 //DDRSS_PI_317_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4F8 0x00001401 //DDRSS_PI_318_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A4FC 0x00000493 //DDRSS_PI_319_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A500 0x00000000 //DDRSS_PI_320_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A504 0x00000424 //DDRSS_PI_321_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A508 0x00000301 //DDRSS_PI_322_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A50C 0x00000000 //DDRSS_PI_323_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A510 0x00000000 //DDRSS_PI_324_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A514 0x00000000 //DDRSS_PI_325_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A518 0x00001401 //DDRSS_PI_326_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A51C 0x00000493 //DDRSS_PI_327_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A520 0x00000000 //DDRSS_PI_328_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A524 0x00000424 //DDRSS_PI_329_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A528 0x00000301 //DDRSS_PI_330_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A52C 0x00000000 //DDRSS_PI_331_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A530 0x00000000 //DDRSS_PI_332_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A534 0x00000000 //DDRSS_PI_333_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A538 0x00001401 //DDRSS_PI_334_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A53C 0x00000493 //DDRSS_PI_335_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A540 0x00000000 //DDRSS_PI_333_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A544 0x00000424 // DDRSS_PI_337_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A548 0x00000301 //DDRSS_PI_338_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A54C 0x00000000 //DDRSS_PI_339_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A550 0x00000000 //DDRSS_PI_340_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A554 0x00000000 //DDRSS_PI_341_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A558 0x00001401 //DDRSS_PI_342_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A55C 0x00000493 //DDRSS_PI_343_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30A560 0x00000000 //DDRSS_PI_344_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C000 0x04C00000 //DDRSS_PHY_0_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C004 0x00000000 //DDRSS_PHY_1_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C008 0x00000200 // DDRSS_PHY_2_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C00C 0x00000000 //DDRSS_PHY_3_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C010 0x00000000 //DDRSS_PHY_4_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C014 0x00000000 //DDRSS_PHY_5_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C018 0x00000000 //DDRSS_PHY_6_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C01C 0x00000000 //DDRSS_PHY_7_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C020 0x00000001 //DDRSS_PHY_8_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C024 0x00000000 //DDRSS_PHY_9_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C028 0x094C0000 //DDRSS_PHY_10_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C02C 0x010101FF //DDRSS_PHY_11_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C030 0x00010000 // DDRSS_PHY_12_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C034 0x00C02004 //DDRSS_PHY_13_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C038 0x00CC0008 //DDRSS_PHY_14_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C03C 0x00660201 //DDRSS_PHY_15_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C040 0x00000000 //DDRSS_PHY_16_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C044 0x00000000 //DDRSS_PHY_17_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C048 0x00000000 //DDRSS_PHY_18_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C04C 0x0000AAAA //DDRSS_PHY_19_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C050 0x0000555//DDRSS_PHY_20_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C054 0x0000B5B5 //DDRSS_PHY_21_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C058 0x00004A4A //DDRSS_PHY_22_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C05C 0x00005656 // DDRSS_PHY_23_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C060 0x0000A9A9 //DDRSS_PHY_24_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C064 0x0000B7B7 //DDRSS_PHY_25_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C068 0x00004848///DDRSS_PHY_26_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C06C 0x00000000 //DDRSS_PHY_27_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C070 0x00000000 //DDRSS_PHY_28_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C074 0x08000000 //DDRSS_PHY_29_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C078 0x0F000008 //DDRSS_PHY_30_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C07C 0x00000F0F //DDRSS_PHY_31_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C080 0x00E4E400 //DDRSS_PHY_32_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C084 0x00070820 //DDRSS_PHY_33_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C088 0x000C0020 //DDRSS_PHY_34_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C08C 0x00062000 //DDRSS_PHY_35_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C090 0x00000000 //DDRSS_PHY_36_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C094 0x5555555///DDRSS_PHY_37_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C098 0xAAAAAAAAAAAA //DDRSS_PHY_38_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C09C 0x555555///DDRSS_PHY_39_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0A0 0xAAAAAAAAAA //DDRSS_PHY_40_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0A4 0x0000555///DDRSS_PHY_41_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0A8 0x01000100 //DDRSS_PHY_42_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0AC 0x00800180 //DDRSS_PHY_43_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0B0 0x00000000 //DDRSS_PHY_44_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0B4 0x00100000 //DDRSS_PHY_45_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0B8 0x00000000 //DDRSS_PHY_46_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0BC 0x0A0A000C //DDRSS_PHY_47_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0C0 0x0000000C //DDRSS_PHY_48_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0C4 0x00020200 // DDRSS_PHY_49_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0C8 0x01CC01B4 //DDRSS_PHY_50_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0CC 0x00000FFF //DDRSS_PHY_51_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0D0 0x00000000 //DDRSS_PHY_52_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0D4 0x02640258 //DDRSS_PHY_53_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0D8 0x00000030 //DDRSS_PHY_54_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0DC 0x01200048 //DDRSS_PHY_55_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0E0 0x00000000 //DDRSS_PHY_56_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0E4 0x0C000000 //DDRSS_PHY_57_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0E8 0x07FF0000 //DDRSS_PHY_58_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0EC 0x00000000 //DDRSS_PHY_59_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0F0 0x00000000 //DDRSS_PHY_60_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0F4 0x00000000 //DDRSS_PHY_61_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0F8 0x00000000 //DDRSS_PHY_62_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C0FC 0x00000000 //DDRSS_PHY_63_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C100 0x00000000 //DDRSS_PHY_64_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C104 0x00000004 //DDRSS_PHY_65_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C108 0x00000000 //DDRSS_PHY_66_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C10C 0x00000000 //DDRSS_PHY_67_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C110 0x00000000 //DDRSS_PHY_68_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C114 0x00000000 //DDRSS_PHY_69_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C118 0x00000000 //DDRSS_PHY_70_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C11C 0x00000000 //DDRSS_PHY_71_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C120 0x041F07FF //DDRSS_PHY_72_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C124 0x00000000 //DDRSS_PHY_73_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C128 0x01CCB001 //DDRSS_PHY_74_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C12C 0x2000CCB0 //DDRSS_PHY_75_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C130 0x20000140 //DDRSS_PHY_76_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C134 0x07FF0200 // DDRSS_PHY_77_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C138 0x0000DD01 //DDRSS_PHY_78_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C13C 0x10100303 //DDRSS_PHY_79_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C140 0x10101010 //DDRSS_PHY_80_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C144 0x10101010 //DDRSS_PHY_81_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C148 0x00021010//DDRSS_PHY_82_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C14C 0x00100010 //DDRSS_PHY_83_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C150 0x00100010 //DDRSS_PHY_84_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C154 0x00100010 //DDRSS_PHY_85_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C158 0x00100010 //DDRSS_PHY_86_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C15C 0x02020010 //DDRSS_PHY_87_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C160 0x51515041 //DDRSS_PHY_88_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C164 0x31804000 // DDRSS_PHY_89_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C168 0x04A00340 //DDRSS_PHY_90_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C16C 0x010080//DDRSS_PHY_91_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C170 0x04050001 //DDRSS_PHY_92_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C174 0x00000504 //DDRSS_PHY_93_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C178 0x42100010 //DDRSS_PHY_94_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C17C 0x010C053E //DDRSS_PHY_95_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C180 0x000F0C14 //DDRSS_PHY_96_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C184 0x01000140 //DDRSS_PHY_97_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C188 0x007A0120 //DDRSS_PHY_98_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C18C 0x00000C00 //DDRSS_PHY_99_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C190 0x000001CC //DDRSS_PHY_100_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C194 0x20100200 // DDRSS_PHY_101_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C198 0x00000005 //DDRSS_PHY_102_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C19C 0x76543210 //DDRSS_PHY_103_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1A0 0x00000008 //DDRSS_PHY_104_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1A4 0x02800280 //DDRSS_PHY_105_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1A8 0x02800280 //DDRSS_PHY_106_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1AC 0x02800280 //DDRSS_PHY_107_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1B0 0x02800280 //DDRSS_PHY_108_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1B4 0x01C00280 //DDRSS_PHY_109_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1B8 0x0000B402 //DDRSS_PHY_110_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1BC 0x00AE00B4 //DDRSS_PHY_111_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1C0 0x00B400B4 //DDRSS_PHY_112_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1C4 0x00B400B4 //DDRSS_PHY_113_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1C8 0x00B400B4 //DDRSS_PHY_114_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1CC 0x00A800B4 //DDRSS_PHY_115_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1D0 0x00AE00AE //DDRSS_PHY_116_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1D4 0x00B400AE //DDRSS_PHY_117_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1D8 0x00B400B4 //DDRSS_PHY_118_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1DC 0x015E00B4 //DDRSS_PHY_119_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1E0 0x01A00000 //DDRSS_PHY_120_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1E4 0x00000000 //DDRSS_PHY_121_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1E8 0x00000000 //DDRSS_PHY_122_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1EC 0x00080200 // DDRSS_PHY_123_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1F0 0x00000000 //DDRSS_PHY_124_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C1F4 0x00000000 //DDRSS_PHY_125_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C400 0x04C00000 //DDRSS_PHY_256_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C404 0x00000000 //DDRSS_PHY_257_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C408 0x00000200 // DDRSS_PHY_258_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C40C 0x00000000 //DDRSS_PHY_259_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C410 0x00000000 //DDRSS_PHY_260_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C414 0x00000000 //DDRSS_PHY_261_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C418 0x00000000 //DDRSS_PHY_262_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C41C 0x00000000 //DDRSS_PHY_263_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C420 0x00000001 //DDRSS_PHY_264_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C424 0x00000000 //DDRSS_PHY_265_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C428 0x094C0000 //DDRSS_PHY_266_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C42C 0x010101FF //DDRSS_PHY_267_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C430 0x00010000 // DDRSS_PHY_268_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C434 0x00C02004 //DDRSS_PHY_269_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C438 0x00CC0008 //DDRSS_PHY_270_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C43C 0x00660201 //DDRSS_PHY_271_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C440 0x00000000 //DDRSS_PHY_272_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C444 0x00000000 //DDRSS_PHY_273_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C448 0x00000000 //DDRSS_PHY_274_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C44C 0x0000AAAA //DDRSS_PHY_275_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C450 0x0000555//DDRSS_PHY_276_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C454 0x0000B5B5 //DDRSS_PHY_277_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C458 0x00004A4A //DDRSS_PHY_278_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C45C 0x00005656 // DDRSS_PHY_279_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C460 0x0000A9A9 //DDRSS_PHY_280_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C464 0x0000B7B7 //DDRSS_PHY_281_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C468 0x00004848///DDRSS_PHY_282_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C46C 0x00000000 //DDRSS_PHY_283_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C470 0x00000000 //DDRSS_PHY_284_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C474 0x08000000 //DDRSS_PHY_285_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C478 0x0F000008 //DDRSS_PHY_286_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C47C 0x00000F0F //DDRSS_PHY_287_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C480 0x00E4E400 //DDRSS_PHY_288_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C484 0x00070820 //DDRSS_PHY_289_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C488 0x000C0020 //DDRSS_PHY_290_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C48C 0x00062000 //DDRSS_PHY_291_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C490 0x00000000 //DDRSS_PHY_292_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C494 0x5555555///DDRSS_PHY_293_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C498 0xAAAAAAAAAAAA //DDRSS_PHY_294_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C49C 0x555555 //DDRSS_PHY_295_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4A0 0xAAAAAAAAAA //DDRSS_PHY_296_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4A4 0x0000555//DDRSS_PHY_297_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4A8 0x01000100 //DDRSS_PHY_298_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4AC 0x00800180 //DDRSS_PHY_299_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4B0 0x00000000 //DDRSS_PHY_300_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4B4 0x00100000 //DDRSS_PHY_301_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4B8 0x00000000 //DDRSS_PHY_302_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4BC 0x0509000B //DDRSS_PHY_303_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4C0 0x00000014 //DDRSS_PHY_304_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4C4 0x00020000 //DDRSS_PHY_305_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4C8 0x01D801C0 //DDRSS_PHY_306_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4CC 0x00000FFF //DDRSS_PHY_307_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4D0 0x00000000 //DDRSS_PHY_308_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4D4 0x02640258 //DDRSS_PHY_309_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4D8 0x00000030 //DDRSS_PHY_310_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4DC 0x0114003C / DDRSS_PHY_311_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4E0 0x00000000 //DDRSS_PHY_312_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4E4 0x0C000000 //DDRSS_PHY_313_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4E8 0x07FF0000 //DDRSS_PHY_314_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4EC 0x00000000 //DDRSS_PHY_315_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4F0 0x00000000 //DDRSS_PHY_316_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4F4 0x00000000 //DDRSS_PHY_317_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4F8 0x00000000 //DDRSS_PHY_318_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C4FC 0x00000000 //DDRSS_PHY_319_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C500 0x00000000 //DDRSS_PHY_320_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C504 0x00000004 //DDRSS_PHY_321_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C508 0x00000000 //DDRSS_PHY_322_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C50C 0x00000000 //DDRSS_PHY_323_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C510 0x00000000 //DDRSS_PHY_324_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C514 0x00000000 //DDRSS_PHY_325_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C518 0x00000000 //DDRSS_PHY_326_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C51C 0x00000000 //DDRSS_PHY_327_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C520 0x041F07FF //DDRSS_PHY_328_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C524 0x00000000 //DDRSS_PHY_329_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C528 0x01CCB001 //DDRSS_PHY_330_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C52C 0x2000CCB0 //DDRSS_PHY_331_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C530 0x20000140 //DDRSS_PHY_332_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C534 0x07FF0200 //DDRSS_PHY_333_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C538 0x0000DD01 //DDRSS_PHY_334_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C53C 0x10100303 //DDRSS_PHY_335_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C540 0x10101010 //DDRSS_PHY_333_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C544 0x10101010 // DDRSS_PHY_337_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C548 0x00021010//DDRSS_PHY_338_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C54C 0x00100010 //DDRSS_PHY_339_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C550 0x00100010 //DDRSS_PHY_340_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C554 0x00100010 //DDRSS_PHY_341_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C558 0x00100010 //DDRSS_PHY_342_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C55C 0x02020010 //DDRSS_PHY_343_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C560 0x51515041 //DDRSS_PHY_344_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C564 0x31804000 //DDRSS_PHY_345_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C568 0x04A00340 //DDRSS_PHY_34_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C56C 0x010080//DDRSS_PHY_347_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C570 0x04050001 //DDRSS_PHY_348_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C574 0x00000504 //DDRSS_PHY_349_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C578 0x42100010 //DDRSS_PHY_350_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C57C 0x010C053E //DDRSS_PHY_351_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C580 0x000F0C14 //DDRSS_PHY_352_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C584 0x01000140 //DDRSS_PHY_353_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C588 0x007A0120 //DDRSS_PHY_354_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C58C 0x00000C00 //DDRSS_PHY_355_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C590 0x000001CC //DDRSS_PHY_356_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C594 0x20100200 // DDRSS_PHY_357_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C598 0x00000005 //DDRSS_PHY_358_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C59C 0x76543210 //DDRSS_PHY_359_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5A0 0x00000008 //DDRSS_PHY_360_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5A4 0x02800280 //DDRSS_PHY_361_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5A8 0x02800280 //DDRSS_PHY_362_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5AC 0x02800280 //DDRSS_PHY_363_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5B0 0x02800280 //DDRSS_PHY_364_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5B4 0x01CC0280 //DDRSS_PHY_365_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5B8 0x0000A802 //DDRSS_PHY_366_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5BC 0x00A200B4 //DDRSS_PHY_367_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5C0 0x00A200A8 //DDRSS_PHY_368_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5C4 0x00AE00A8 //DDRSS_PHY_369_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5C8 0x00A800B4 //DDRSS_PHY_370_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5CC 0x00A800B4 //DDRSS_PHY_371_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5D0 0x00A800A8 //DDRSS_PHY_372_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5D4 0x00A800A8 //DDRSS_PHY_373_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5D8 0x00A800A8 //DDRSS_PHY_374_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5DC 0x015E00B4 //DDRSS_PHY_375_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5E0 0x01A00000 //DDRSS_PHY_376_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5E4 0x00000000 //DDRSS_PHY_377_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5E8 0x00000000 //DDRSS_PHY_378_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5EC 0x00080200 //DDRSS_PHY_379_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5F0 0x00000000 //DDRSS_PHY_380_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C5F4 0x00000000 //DDRSS_PHY_381_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C800 0x00000100 //DDRSS_PHY_512_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C804 0x00001000 //DDRSS_PHY_513_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C808 0x000A0000 //DDRSS_PHY_514_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C80C 0x00000000 //DDRSS_PHY_515_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C810 0x00000000 //DDRSS_PHY_516_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C814 0x00000100 //DDRSS_PHY_517_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C818 0x00000000 //DDRSS_PHY_518_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C81C 0x00000000 //DDRSS_PHY_519_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C820 0x00000000 //DDRSS_PHY_520_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C824 0x00000000 //DDRSS_PHY_521_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C828 0x00000000 //DDRSS_PHY_52_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C82C 0x00000000 //DDRSS_PHY_523_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C830 0x00000000 //DDRSS_PHY_524_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C834 0x00DCBA98 //DDRSS_PHY_525_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C838 0x00000000 //DDRSS_PHY_526_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C83C 0x00000000 //DDRSS_PHY_527_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C840 0x00000000 //DDRSS_PHY_528_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C844 0x00000000 //DDRSS_PHY_529_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C848 0x00000000 //DDRSS_PHY_530_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C84C 0x00000100 //DDRSS_PHY_531_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C850 0x00000000 //DDRSS_PHY_532_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C854 0x00000000 //DDRSS_PHY_533_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C858 0x00000000 //DDRSS_PHY_534_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C85C 0x00000000 //DDRSS_PHY_535_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C860 0x00000000 //DDRSS_PHY_536_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C864 0x00000000 //DDRSS_PHY_537_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C868 0x00000000 //DDRSS_PHY_538_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C86C 0x00000000 //DDRSS_PHY_539_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C870 0x0A418820 //DDRSS_PHY_540_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C874 0x103F0000 //DDRSS_PHY_541_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C878 0x000F0100 //DDRSS_PHY_542_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C87C 0x0000000F //DDRSS_PHY_543_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C880 0x020002CC //DDRSS_PHY_544_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C884 0x00030000 //DDRSS_PHY_545_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C888 0x00000300 //DDRSS_PHY_545_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C88C 0x00000300 //DDRSS_PHY_547_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C890 0x00000300 //DDRSS_PHY_548_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C894 0x00000300 //DDRSS_PHY_549_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C898 0x00000300 //DDRSS_PHY_550_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C89C 0x42080010 //DDRSS_PHY_551_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C8A0 0x0000003E //DDRSS_PHY_552_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C8A4 0x00000000 //DDRSS_PHY_553_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30C8A8 0x00000000 //DDRSS_PHY_554_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC00 0x00000100 //DDRSS_PHY_768_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC04 0x00001000 //DDRSS_PHY_76L_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC08 0x00090000 //DDRSS_PHY_770_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC0C 0x00000000 //DDRSS_PHY_771_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC10 0x00000000 //DDRSS_PHY_772_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC14 0x00000100 //DDRSS_PHY_773_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC18 0x00000000 //DDRSS_PHY_774_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC1C 0x00000000 //DDRSS_PHY_775_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC20 0x00000000 //DDRSS_PHY_776_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC24 0x00000000 //DDRSS_PHY_777_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC28 0x00000000 //DDRSS_PHY_778_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC2C 0x00000000 //DDRSS_PHY_779_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC30 0x00000000 //DDRSS_PHY_780_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC34 0x00DCBA98 //DDRSS_PHY_781_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC38 0x00000000 //DDRSS_PHY_782_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC3C 0x00000000 //DDRSS_PHY_783_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC40 0x00000000 //DDRSS_PHY_784_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC44 0x00000000 //DDRSS_PHY_785_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC48 0x00000000 //DDRSS_PHY_787_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC4C 0x00000100 //DDRSS_PHY_787_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC50 0x00000000 //DDRSS_PHY_788_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC54 0x00000000 //DDRSS_PHY_789_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC58 0x00000000 //DDRSS_PHY_790_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC5C 0x00000000 //DDRSS_PHY_791_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC60 0x00000000 //DDRSS_PHY_792_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC64 0x00000000 //DDRSS_PHY_793_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC68 0x00000000 //DDRSS_PHY_794_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC6C 0x00000000 //DDRSS_PHY_795_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC70 0x16A4A0E6///DDRSS_PHY_796_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC74 0x103F0000 //DDRSS_PHY_797_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC78 0x000F0000 //DDRSS_PHY_798_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC7C 0x0000000F //DDRSS_PHY_799_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC80 0x020002CC //DDRSS_PHY_800_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC84 0x00030000 //DDRSS_PHY_801_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC88 0x00000300 //DDRSS_PHY_802_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC8C 0x00000300 //DDRSS_PHY_803_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC90 0x00000300 //DDRSS_PHY_804_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC94 0x00000300 //DDRSS_PHY_805_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC98 0x00000300 //DDRSS_PHY_806_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CC9C 0x42080010 //DDRSS_PHY_807_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CCA0 0x0000003E //DDRSS_PHY_808_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CCA4 0x00000000 //DDRSS_PHY_809_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30CCA8 0x00000000 //DDRSS_PHY_810_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D000 0x00000100 //DDRSS_PHY_1024_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D004 0x00001000 //DDRSS_PHY_1025_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D008 0x00090000 //DDRSS_PHY_1026_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D00C 0x00000000 //DDRSS_PHY_1027_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D010 0x00000000 //DDRSS_PHY_1028_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D014 0x00000100 //DDRSS_PHY_1029_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D018 0x00000000 //DDRSS_PHY_1030_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D01C 0x00000000 //DDRSS_PHY_1031_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D020 0x00000000 //DDRSS_PHY_1032_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D024 0x00000000 //DDRSS_PHY_1033_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D028 0x00000000 //DDRSS_PHY_1034_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D02C 0x00000000 //DDRSS_PHY_1035_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D030 0x00000000 //DDRSS_PHY_1036_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D034 0x00DCBA98 //DDRSS_PHY_1037_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D038 0x00000000 //DDRSS_PHY_1038_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D03C 0x00000000 //DDRSS_PHY_1039_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D040 0x00000000 //DDRSS_PHY_1040_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D044 0x00000000 //DDRSS_PHY_1041_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D048 0x00000000 //DDRSS_PHY_1042_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D04C 0x00000100 //DDRSS_PHY_1043_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D050 0x00000000 //DDRSS_PHY_1044_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D054 0x00000000 //DDRSS_PHY_1045_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D058 0x00000000 //DDRSS_PHY_1046_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D05C 0x00000000 //DDRSS_PHY_1047_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D060 0x00000000 //DDRSS_PHY_1048_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D064 0x00000000 //DDRSS_PHY_1049_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D068 0x00000000 //DDRSS_PHY_1050_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D06C 0x00000000 //DDRSS_PHY_1051_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D070 0x2307B9AC //DDRSS_PHY_1052_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D074 0x10030000 //DDRSS_PHY_1053_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D078 0x000F0000 //DDRSS_PHY_1054_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D07C 0x0000000F //DDRSS_PHY_1055_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D080 0x020002CC //DDRSS_PHY_1056_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D084 0x00030000 //DDRSS_PHY_1057_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D088 0x00000300 //DDRSS_PHY_1058_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D08C 0x00000300 //DDRSS_PHY_1059_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D090 0x00000300 //DDRSS_PHY_1060_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D094 0x00000300 //DDRSS_PHY_1061_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D098 0x00000300 //DDRSS_PHY_1062_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D09C 0x42080010 //DDRSS_PHY_1063_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D0A0 0x0000003E //DDRSS_PHY_1064_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D0A4 0x00000000 //DDRSS_PHY_1065_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D0A8 0x00000000 //DDRSS_PHY_1061066_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D400 0x00000000 //DDRSS_PHY_1280_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D404 0x00000100 //DDRSS_PHY_1281_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D408 0x00000000 //DDRSS_PHY_1282_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D40C 0x00000000 //DDRSS_PHY_1283_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D410 0x00000000 //DDRSS_PHY_1284_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D414 0x00000000 //DDRSS_PHY_1285_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D418 0x00050000 //DDRSS_PHY_1286_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D41C 0x04000100 //DDRSS_PHY_1287_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D420 0x00000055 //DDRSS_PHY_1288_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D424 0x00000000 //DDRSS_PHY_1289_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D428 0x06800000 //DDRSS_PHY_1290_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D42C 0x00000000 //DDRSS_PHY_1291_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D430 0x00000000 //DDRSS_PHY_1292_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D434 0x01002000 //DDRSS_PHY_1293_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D438 0x00004001 //DDRSS_PHY_1294_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D43C 0x00020028 //DDRSS_PHY_1295_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D440 0x00010100 //DDRSS_PHY_1296_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D444 0x00000001 //DDRSS_PHY_1297_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D448 0x00000000 //DDRSS_PHY_1298_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D44C 0x0F0F0E06 //DDRSS_PHY_1299_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D450 0x00010101 //DDRSS_PHY_1300_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D454 0x010F0004 //DDRSS_PHY_1301_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D458 0x00000000 //DDRSS_PHY_1302_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D45C 0x20125770 //DDRSS_PHY_1303_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D460 0x00000064 //DDRSS_PHY_1304_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D464 0x00000000 //DDRSS_PHY_1305_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D468 0x00000000 //DDRSS_PHY_1306_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D46C 0x01020103 //DDRSS_PHY_1307_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D470 0x03020102 //DDRSS_PHY_1308_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D474 0x03030303 //DDRSS_PHY_1309_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D478 0x03030303 //DDRSS_PHY_1310_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D47C 0x00040000 //DDRSS_PHY_1311_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D480 0x00005201 //DDRSS_PHY_1312_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D484 0x00000003 //DDRSS_PHY_1313_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D488 0x00010000 // DDRSS_PHY_1314_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D48C 0x00000000 //DDRSS_PHY_1315_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D490 0x00000003 //DDRSS_PHY_1316_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D494 0x00010000 // DDRSS_PHY_1317_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D498 0x00000000 //DDRSS_PHY_1318_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D49C 0x07070001 //DDRSS_PHY_1319_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4A0 0x00005400 //DDRSS_PHY_1320_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4A4 0x000040A2 //DDRSS_PHY_1321_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4A8 0x00038952 //DDRSS_PHY_1322_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4AC 0x00018952 //DDRSS_PHY_1323_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4B0 0x00018952 //DDRSS_PHY_1324_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4B4 0x00018952 //DDRSS_PHY_1325数据
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4B8 0x00019992 //DDRSS_PHY_1326_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4BC 0x00018952 //DDRSS_PHY_1327_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4C0 0x000189A3 //DDRSS_PHY_1328_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4C4 0x000189A3 //DDRSS_PHY_1329_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4C8 0x00018952 //DDRSS_PHY_1330_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4CC 0x00018952 //DDRSS_PHY_1331_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4D0 0x00000000 //DDRSS_PHY_1332_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4D4 0x00000046 //DDRSS_PHY_1333_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4D8 0x00000400 //DDRSS_PHY_1334_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4DC 0x00000008 //DDRSS_PHY_1335_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4E0 0x00818952 //DDRSS_PHY_1336_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4E4 0x008189A3 //DDRSS_PHY_1337_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4E8 0x00189520 //DDRSS_PHY_1338_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4EC 0x00189A38 //DDRSS_PHY_1339_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4F0 0x00F8952F //DDRSS_PHY_1340_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4F4 0x03F89A3F //DDRSS_PHY_1341_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4F8 0x00000000 //DDRSS_PHY_1342_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D4FC 0x00000000 //DDRSS_PHY_1343_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D500 0xB3000000 //DDRSS_PHY_1344_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D504 0x04102006 //DDRSS_PHY_1345_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D508 0x00041020 //DDRSS_PHY_1346_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D50C 0x01C98C98 //DDRSS_PHY_1347_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D510 0x3F400000 //DDRSS_PHY_1348_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D514 0x3F3F1F3F //DDRSS_PHY_1349_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D518 0x0000001F // DDRSS_PHY_1350_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D51C 0x00000000 //DDRSS_PHY_1351_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D520 0x00000000 //DDRSS_PHY_1352_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D524 0x00000000 //DDRSS_PHY_1353(2001)数据
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D528 0x00000001 //DDRSS_PHY_1354_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D52C 0x00000000 //DDRSS_PHY_1355_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D530 0x00000000 //DDRSS_PHY_1356_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D534 0x00000000 //DDRSS_PHY_1357_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D538 0x00000000 //DDRSS_PHY_1358_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D53C 0x76543210 //DDRSS_PHY_1359_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D540 0x00000098 //DDRSS_PHY_1360_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D544 0x00000000 //DDRSS_PHY_1361_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D548 0x00000000 //DDRSS_PHY_1362_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D54C 0x00000000 //DDRSS_PHY_1363_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D550 0x00040700 //DDRSS_PHY_1364_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D554 0x00000000 //DDRSS_PHY_1365_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D558 0x00000000 //DDRSS_PHY_136_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D55C 0x00000000 //DDRSS_PHY_1367_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D560 0x030F7102 //DDRSS_PHY_1368_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D564 0x00000100 //DDRSS_PHY_1369_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D568 0x00000000 //DDRSS_PHY_1370_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D56C 0x0001F7C0 //DDRSS_PHY_1371_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D570 0x00020002 //DDRSS_PHY_1372_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D574 0x00000000 //DDRSS_PHY_1373数据
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D578 0x00001142 //DDRSS_PHY_1374_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D57C 0x03020400 //DDRSS_PHY_1375_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D580 0x00000080 //DDRSS_PHY_1376_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D584 0x03900390 //DDRSS_PHY_1377_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D588 0x03900390 //DDRSS_PHY_1378_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D58C 0x03900390 //DDRSS_PHY_1379_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D590 0x03900390 //DDRSS_PHY_1380_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D594 0x03900390 //DDRSS_PHY_1381_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D598 0x03900390 //DDRSS_PHY_1382_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D59C 0x00000300 //DDRSS_PHY_1383_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5A0 0x00000300 //DDRSS_PHY_1384_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5A4 0x00000300 //DDRSS_PHY_1385_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5A8 0x00000300 //DDRSS_PHY_1386_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5AC 0x31823FC7 //DDRSS_PHY_1387_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5B0 0x00000000 //DDRSS_PHY_1388_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5B4 0x0C000D3F //DDRSS_PHY_1389_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5B8 0x30000D3F //DDRSS_PHY_1390_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5BC 0x300D3F11 //DDRSS_PHY_1391_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5C0 0x01990000 //DDRSS_PHY_1392_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5C4 0x000D3FCC //DDRSS_PHY_1393_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5C8 0x00000C11 //DDRSS_PHY_1394_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5CC 0x300D3F11 //DDRSS_PHY_1395_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5D0 0x01990000 //DDRSS_PHY_1396_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5D4 0x300C3F11 //DDRSS_PHY_1397_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5D8 0x01990000 //DDRSS_PHY_1398_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5DC 0x300C3F11 //DDRSS_PHY_1399_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5E0 0x01990000 //DDRSS_PHY_1400_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5E4 0x300D3F11 //DDRSS_PHY_1401_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5E8 0x01990000 //DDRSS_PHY_1402_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5EC 0x300D3F11 //DDRSS_PHY_1403_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5F0 0x01990000 //DDRSS_PHY_1404_DATA
MAIN_Cortex_R5_0_0：GEL 输出：0x0F30D5F4 0x20040004 //DDRSS_PHY_1405_DATA

0 admin 3 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

Jimin、我目前看不到 regdump 有什么问题。我想让您尝试用 gels 而不是 SDK 来初始化 DDR。为此、您能否为电路板通电、请确保没有引导(例如、如果您的引导源是 SD 卡、请卸下 SD 卡)、然后

在 CCS 中创建目标配置、方法是转到 View->Target Configurations、然后右键单击 User Defined -> New Target Configuration、并为文件命名并点击 Finish。将弹出一个窗口、选择"Board：AM64x_GP_EVM"、然后点击"Save"。 filename.ccxml 将显示在 Target Configurations 窗口中

-右键单击刚刚创建的此目标配置，然后选择“启动选定的配置”

-在"Debug"窗口中、右键单击 DMSC 并选择"Connect Target"。这将自动运行 GEL 脚本以初始化 PLL 和 PSC

-在 Debug 窗口中、右键点击 CortexA53_0并选择 Connect Target。这将自动运行 GEL 脚本以初始化 DDR。

控制台应指示 DDR 初始化成功。此时，打开存储器浏览器(View->Memory Browser)，将地址设置为0x80000000，查看是否可以在窗口中成功读取/写入。

告诉我您的观察结果、并发送"Console"窗口的输出

此致、

James

0 admin 3 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

谢谢、JJD.我按照您的指示执行 GEL 初始 DDR。但我无法按照以下屏幕短接方式连接 A53_0。因此我尝试连接 R50_0、成功了。 CCS 版本11.1.0。 SDK 版本8.2.0.31。

[引用 userid="1187" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4413589 #4413589"]在"Debug"窗口中、右键单击 CortexA53_0并选择"Connect Target"。这将自动运行 GEL 脚本以初始化 DDR。[/quot]

我尝试使用最新的 CCS 版本12.0.0。 SDK 版本8.4.0.17.一切正常！控制台输出如下所示

e2e.ti.com/.../GELInitialDDR.txt

当我打开存储器浏览器时、显示0x8000000000-0x8000010f 区域、如下所示。

然后、我将 ADDR 0x8000000的值更改为 0x8000000f、如下所示、IT 成功。

谢谢、

jimin.Li

0 admin 3 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

好的、您的硬件似乎正常工作。您的初始代码中可能存在一些不使用正确 DDR 配置的问题、或者某些问题会破坏配置。您能否仔细检查代码构建？

此致、

James

0 admin 3 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

谢谢、James。

硬件工作正常吗？

[引用 userid="1187" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4417949 #4417949"]您的硬件似乎在正常工作

初始代码和配置您的意思是我们在 Linux SDK 中的 DDR 初始代码吗？

[引用 userid="1187" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4417949 #4417949"]您的初始代码中可能存在一些未使用正确 DDR 配置的问题，或者某些问题会破坏配置[/quot]

GEL 初始化的 DDR 的控制台输出可以显示任何情况正常？只是我们的初始 DDR 代码存在一些问题？如果是、我将尝试使用 GEL DDR 配置来配置我们的 DDR 初始代码。

此外、我已将 Linux SDK 更新为8.4.1.4、它仍然存在这种现象。

[引用 userid="522430" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail "]我们在定制板上遇到了随机现象，即 DDR 测试 memcpy 在 R5 spl 初始 DDR 之后失败。

谢谢、

jimin.Li

0 admin 3 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

Jimin、您应该使用 https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM64x_beta 上的 SYSCFG 工具为您正在使用的 DDR 生成配置。由于它似乎在使用 GEL 中的配置、因此我附加了两个相同的配置、一个是 GEL 格式、另一个是 u-boot 格式.dtsi。您需要在代码构建中使用此 DDR 配置、Linux SDK 中的 DDR 配置可能不适用于您的电路板。

/cfs-file/__key/communityserver-discussions-components-files/791/k3_2D00_am64_2D00_ddr_2D00_config-_2800_20_2900_.dtsi

/cfs-file/__key/communityserver-discussions-components-files/791/AM64x_2D00_DDRConfig-_2800_8_2900_.gel

GEL 应与 CCS12.0随附的相同、并且还应在您的电路板上工作。请像上面所做的那样首先检查这个、然后如果成功的话、将.dtsi 编译到 uboot 中并尝试再次测试

此致、

James

0 admin 3 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

谢谢、JJD。

我们检查随附的 dtsi 与 Linux SDK8.4源代码 dtsi 之间的区别、仅下面两个不同的配置参数、对吧？

[引用 userid="1187" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4425244 #4425244"]/cfs-file/__key/communityserver-discussions-components-files/791/k3_2D00_am64_2D00_ddr_2D00_config-_2800_20_2900_.dtsi [/quot]

我们已根据您的建议将您提供的 dtsi 应用于我们的定制板。这种现象仍然存在。

[引用 userid="522430" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4418144 #4418144"]我们在定制板上遇到了随机现象，即 DDR 测试 memcpy 在 R5 spl 初始 DDR 之后失败。

我们的定制板还具有 AM2434 ALV SR1.0、我们将使用相同的 DDR 配置文件在 AM6442和 AM2434处进行交叉验证。原因我们在 AM2434 ALV SR1.0处仍然没有 DDR 测试失败。您有其他建议吗？

谢谢、

jimin.Li

0 admin 3 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好、Jimin、您显示的2个差异不会影响您的结果。这些只是为了与最新建议保持一致而进行的一些小改动。

我对你的最后一句话感到困惑。那么、您有带 AM2434和 AM6442的电路板吗？您能否详细说明哪些电路板(以及多少电路板)可与最新的.dtsi 配合使用、哪些电路板不能配合使用？ GEL 在两种类型的电路板上都能工作吗？ .dtsi 呢？

这两个器件在 DDR 方面的运行应该相同、因此这两个器件的配置应该相同。

我发送的最新 GEL 和.dtsi 是完全相同的配置、因此、如果您可以让板与 GEL 一起工作、但不能与.dtsi 一起工作、我认为问题是其他地方的、可能是您正在运行的测试。您能给我提供有关如何从 u-boot 运行测试的更多详细信息吗？内核？等等？

此致、

James

0 admin 3 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 JJD。

是的、我们的代价电路板都有 AM6442和 AM2434。主板有一个 AM2434、子板有一个 AM6442。通过连接器与主板连接的子板。

我们对这些电路板使用相同的 DDR 配置(AM64x-EVM 处理器 Linux SDK8.4中的 dtsi)，这是因为这两个电路板使用相同的 DDR MT40A1G16KD-062E IT：e.

在 AM64x-EVM 处理器 Linux sdk8.4中、 R5Fss0-0使用 tiboot3.bin 作为初始 DDR 的初始代码，在 DDR 初始之后，我们仅添加如下所示的 DDR memcpy 测试 C 代码。然后我们将相同的 tiboot3.bin 刻录到主板和子板。然后，我们发现只有子板遇到随机挂起，DDR 测试失败，主板从未遇到过这种现象。

e2e.ti.com/.../am642_5F00_init.c

[引用 userid="1187" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4428149 #4428149">您是否拥有采用 AM2434和 AM6442的电路板？您能否详细说明哪些电路板(以及多少电路板)可与最新的.dtsi 配合使用、哪些电路板不能配合使用？ GEL 在两种类型的电路板上都能工作吗？ .dtsi 呢？[/quot]

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// SPDX-License-Identifier: GPL-2.0+
/*
 * This file was generated with the
 * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40
 * Wed Feb 02 2022 16:24:50 GMT-0600 (Central Standard Time)
 * DDR Type: DDR4
 * Frequency = 800MHz (1600MTs)
 * Density: 16Gb
 * Number of Ranks: 1
 */
#define DDRSS_PLL_FHS_CNT 6
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_CTL_0_DATA 0x00000A00
#define DDRSS_CTL_1_DATA 0x00000000
#define DDRSS_CTL_2_DATA 0x00000000
#define DDRSS_CTL_3_DATA 0x00000000
#define DDRSS_CTL_4_DATA 0x00000000
#define DDRSS_CTL_5_DATA 0x00000000
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

// SPDX-License-Identifier: GPL-2.0+
/*
 * This file was generated with the
 * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40
 * Wed Feb 02 2022 16:24:50 GMT-0600 (Central Standard Time)
 * DDR Type: DDR4
 * Frequency = 800MHz (1600MTs)
 * Density: 16Gb
 * Number of Ranks: 1
 */

#define DDRSS_PLL_FHS_CNT 6
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000

#define DDRSS_CTL_0_DATA 0x00000A00
#define DDRSS_CTL_1_DATA 0x00000000
#define DDRSS_CTL_2_DATA 0x00000000
#define DDRSS_CTL_3_DATA 0x00000000
#define DDRSS_CTL_4_DATA 0x00000000
#define DDRSS_CTL_5_DATA 0x00000000
#define DDRSS_CTL_6_DATA 0x00000000
#define DDRSS_CTL_7_DATA 0x000890B8
#define DDRSS_CTL_8_DATA 0x00000000
#define DDRSS_CTL_9_DATA 0x00000000
#define DDRSS_CTL_10_DATA 0x00000000
#define DDRSS_CTL_11_DATA 0x000890B8
#define DDRSS_CTL_12_DATA 0x00000000
#define DDRSS_CTL_13_DATA 0x00000000
#define DDRSS_CTL_14_DATA 0x00000000
#define DDRSS_CTL_15_DATA 0x000890B8
#define DDRSS_CTL_16_DATA 0x00000000
#define DDRSS_CTL_17_DATA 0x00000000
#define DDRSS_CTL_18_DATA 0x00000000
#define DDRSS_CTL_19_DATA 0x01010100
#define DDRSS_CTL_20_DATA 0x01000100
#define DDRSS_CTL_21_DATA 0x01000110
#define DDRSS_CTL_22_DATA 0x02010002
#define DDRSS_CTL_23_DATA 0x00027100
#define DDRSS_CTL_24_DATA 0x00061A80
#define DDRSS_CTL_25_DATA 0x02550255
#define DDRSS_CTL_26_DATA 0x00000255
#define DDRSS_CTL_27_DATA 0x00000000
#define DDRSS_CTL_28_DATA 0x00000000
#define DDRSS_CTL_29_DATA 0x00000000
#define DDRSS_CTL_30_DATA 0x00000000
#define DDRSS_CTL_31_DATA 0x00000000
#define DDRSS_CTL_32_DATA 0x00000000
#define DDRSS_CTL_33_DATA 0x00000000
#define DDRSS_CTL_34_DATA 0x00000000
#define DDRSS_CTL_35_DATA 0x00000000
#define DDRSS_CTL_36_DATA 0x00000000
#define DDRSS_CTL_37_DATA 0x00000000
#define DDRSS_CTL_38_DATA 0x0400091C
#define DDRSS_CTL_39_DATA 0x1C1C1C1C
#define DDRSS_CTL_40_DATA 0x0400091C
#define DDRSS_CTL_41_DATA 0x1C1C1C1C
#define DDRSS_CTL_42_DATA 0x0400091C
#define DDRSS_CTL_43_DATA 0x1C1C1C1C
#define DDRSS_CTL_44_DATA 0x05050404
#define DDRSS_CTL_45_DATA 0x00002706
#define DDRSS_CTL_46_DATA 0x0602001D
#define DDRSS_CTL_47_DATA 0x05001D0B
#define DDRSS_CTL_48_DATA 0x00270605
#define DDRSS_CTL_49_DATA 0x0602001D
#define DDRSS_CTL_50_DATA 0x05001D0B
#define DDRSS_CTL_51_DATA 0x00270605
#define DDRSS_CTL_52_DATA 0x0602001D
#define DDRSS_CTL_53_DATA 0x07001D0B
#define DDRSS_CTL_54_DATA 0x00180807
#define DDRSS_CTL_55_DATA 0x0400DB60
#define DDRSS_CTL_56_DATA 0x07070009
#define DDRSS_CTL_57_DATA 0x00001808
#define DDRSS_CTL_58_DATA 0x0400DB60
#define DDRSS_CTL_59_DATA 0x07070009
#define DDRSS_CTL_60_DATA 0x00001808
#define DDRSS_CTL_61_DATA 0x0400DB60
#define DDRSS_CTL_62_DATA 0x03000009
#define DDRSS_CTL_63_DATA 0x0D0C0002
#define DDRSS_CTL_64_DATA 0x0D0C0D0C
#define DDRSS_CTL_65_DATA 0x01010000
#define DDRSS_CTL_66_DATA 0x03191919
#define DDRSS_CTL_67_DATA 0x0B0B0B0B
#define DDRSS_CTL_68_DATA 0x00000B0B
#define DDRSS_CTL_69_DATA 0x00000101
#define DDRSS_CTL_70_DATA 0x00000000
#define DDRSS_CTL_71_DATA 0x01000000
#define DDRSS_CTL_72_DATA 0x01180803
#define DDRSS_CTL_73_DATA 0x00001860
#define DDRSS_CTL_74_DATA 0x00000118
#define DDRSS_CTL_75_DATA 0x00001860
#define DDRSS_CTL_76_DATA 0x00000118
#define DDRSS_CTL_77_DATA 0x00001860
#define DDRSS_CTL_78_DATA 0x00000005
#define DDRSS_CTL_79_DATA 0x00000000
#define DDRSS_CTL_80_DATA 0x00000000
#define DDRSS_CTL_81_DATA 0x00000000
#define DDRSS_CTL_82_DATA 0x00000000
#define DDRSS_CTL_83_DATA 0x00000000
#define DDRSS_CTL_84_DATA 0x00000000
#define DDRSS_CTL_85_DATA 0x00000000
#define DDRSS_CTL_86_DATA 0x00000000
#define DDRSS_CTL_87_DATA 0x00090009
#define DDRSS_CTL_88_DATA 0x00000009
#define DDRSS_CTL_89_DATA 0x00000000
#define DDRSS_CTL_90_DATA 0x00000000
#define DDRSS_CTL_91_DATA 0x00000000
#define DDRSS_CTL_92_DATA 0x00000000
#define DDRSS_CTL_93_DATA 0x00000000
#define DDRSS_CTL_94_DATA 0x00010001
#define DDRSS_CTL_95_DATA 0x00025501
#define DDRSS_CTL_96_DATA 0x02550120
#define DDRSS_CTL_97_DATA 0x02550120
#define DDRSS_CTL_98_DATA 0x01200120
#define DDRSS_CTL_99_DATA 0x01200120
#define DDRSS_CTL_100_DATA 0x00000000
#define DDRSS_CTL_101_DATA 0x00000000
#define DDRSS_CTL_102_DATA 0x00000000
#define DDRSS_CTL_103_DATA 0x00000000
#define DDRSS_CTL_104_DATA 0x00000000
#define DDRSS_CTL_105_DATA 0x00000000
#define DDRSS_CTL_106_DATA 0x03010000
#define DDRSS_CTL_107_DATA 0x00010000
#define DDRSS_CTL_108_DATA 0x00000000
#define DDRSS_CTL_109_DATA 0x01000000
#define DDRSS_CTL_110_DATA 0x80104002
#define DDRSS_CTL_111_DATA 0x00040003
#define DDRSS_CTL_112_DATA 0x00040005
#define DDRSS_CTL_113_DATA 0x00030000
#define DDRSS_CTL_114_DATA 0x00050004
#define DDRSS_CTL_115_DATA 0x00000004
#define DDRSS_CTL_116_DATA 0x00040003
#define DDRSS_CTL_117_DATA 0x00040005
#define DDRSS_CTL_118_DATA 0x00000000
#define DDRSS_CTL_119_DATA 0x00061800
#define DDRSS_CTL_120_DATA 0x00061800
#define DDRSS_CTL_121_DATA 0x00061800
#define DDRSS_CTL_122_DATA 0x00061800
#define DDRSS_CTL_123_DATA 0x00061800
#define DDRSS_CTL_124_DATA 0x00000000
#define DDRSS_CTL_125_DATA 0x0000AAA0
#define DDRSS_CTL_126_DATA 0x00061800
#define DDRSS_CTL_127_DATA 0x00061800
#define DDRSS_CTL_128_DATA 0x00061800
#define DDRSS_CTL_129_DATA 0x00061800
#define DDRSS_CTL_130_DATA 0x00061800
#define DDRSS_CTL_131_DATA 0x00000000
#define DDRSS_CTL_132_DATA 0x0000AAA0
#define DDRSS_CTL_133_DATA 0x00061800
#define DDRSS_CTL_134_DATA 0x00061800
#define DDRSS_CTL_135_DATA 0x00061800
#define DDRSS_CTL_136_DATA 0x00061800
#define DDRSS_CTL_137_DATA 0x00061800
#define DDRSS_CTL_138_DATA 0x00000000
#define DDRSS_CTL_139_DATA 0x0000AAA0
#define DDRSS_CTL_140_DATA 0x00000000
#define DDRSS_CTL_141_DATA 0x00000000
#define DDRSS_CTL_142_DATA 0x00000000
#define DDRSS_CTL_143_DATA 0x00000000
#define DDRSS_CTL_144_DATA 0x00000000
#define DDRSS_CTL_145_DATA 0x00000000
#define DDRSS_CTL_146_DATA 0x00000000
#define DDRSS_CTL_147_DATA 0x00000000
#define DDRSS_CTL_148_DATA 0x00000000
#define DDRSS_CTL_149_DATA 0x00000000
#define DDRSS_CTL_150_DATA 0x00000000
#define DDRSS_CTL_151_DATA 0x00000000
#define DDRSS_CTL_152_DATA 0x00000000
#define DDRSS_CTL_153_DATA 0x00000000
#define DDRSS_CTL_154_DATA 0x00000000
#define DDRSS_CTL_155_DATA 0x00000000
#define DDRSS_CTL_156_DATA 0x080C0000
#define DDRSS_CTL_157_DATA 0x080C080C
#define DDRSS_CTL_158_DATA 0x00000000
#define DDRSS_CTL_159_DATA 0x07010A09
#define DDRSS_CTL_160_DATA 0x000E0A09
#define DDRSS_CTL_161_DATA 0x010A0900
#define DDRSS_CTL_162_DATA 0x0E0A0907
#define DDRSS_CTL_163_DATA 0x0A090000
#define DDRSS_CTL_164_DATA 0x0A090701
#define DDRSS_CTL_165_DATA 0x0000000E
#define DDRSS_CTL_166_DATA 0x00040003
#define DDRSS_CTL_167_DATA 0x00000007
#define DDRSS_CTL_168_DATA 0x00000000
#define DDRSS_CTL_169_DATA 0x00000000
#define DDRSS_CTL_170_DATA 0x00000000
#define DDRSS_CTL_171_DATA 0x00000000
#define DDRSS_CTL_172_DATA 0x00000000
#define DDRSS_CTL_173_DATA 0x00000000
#define DDRSS_CTL_174_DATA 0x01000000
#define DDRSS_CTL_175_DATA 0x00000000
#define DDRSS_CTL_176_DATA 0x00001500
#define DDRSS_CTL_177_DATA 0x0000100E
#define DDRSS_CTL_178_DATA 0x00000000
#define DDRSS_CTL_179_DATA 0x00000000
#define DDRSS_CTL_180_DATA 0x00000001
#define DDRSS_CTL_181_DATA 0x00000002
#define DDRSS_CTL_182_DATA 0x00000C00
#define DDRSS_CTL_183_DATA 0x00001000
#define DDRSS_CTL_184_DATA 0x00000C00
#define DDRSS_CTL_185_DATA 0x00001000
#define DDRSS_CTL_186_DATA 0x00000C00
#define DDRSS_CTL_187_DATA 0x00001000
#define DDRSS_CTL_188_DATA 0x00000000
#define DDRSS_CTL_189_DATA 0x00000000
#define DDRSS_CTL_190_DATA 0x00000000
#define DDRSS_CTL_191_DATA 0x00000000
#define DDRSS_CTL_192_DATA 0x00000000
#define DDRSS_CTL_193_DATA 0x00000000
#define DDRSS_CTL_194_DATA 0x00000000
#define DDRSS_CTL_195_DATA 0x00000000
#define DDRSS_CTL_196_DATA 0x00000000
#define DDRSS_CTL_197_DATA 0x00000000
#define DDRSS_CTL_198_DATA 0x00000000
#define DDRSS_CTL_199_DATA 0x00000000
#define DDRSS_CTL_200_DATA 0x00000000
#define DDRSS_CTL_201_DATA 0x00000000
#define DDRSS_CTL_202_DATA 0x00000000
#define DDRSS_CTL_203_DATA 0x00000000
#define DDRSS_CTL_204_DATA 0x00042400
#define DDRSS_CTL_205_DATA 0x00000301
#define DDRSS_CTL_206_DATA 0x00000000
#define DDRSS_CTL_207_DATA 0x00000424
#define DDRSS_CTL_208_DATA 0x00000301
#define DDRSS_CTL_209_DATA 0x00000000
#define DDRSS_CTL_210_DATA 0x00000424
#define DDRSS_CTL_211_DATA 0x00000301
#define DDRSS_CTL_212_DATA 0x00000000
#define DDRSS_CTL_213_DATA 0x00000424
#define DDRSS_CTL_214_DATA 0x00000301
#define DDRSS_CTL_215_DATA 0x00000000
#define DDRSS_CTL_216_DATA 0x00000424
#define DDRSS_CTL_217_DATA 0x00000301
#define DDRSS_CTL_218_DATA 0x00000000
#define DDRSS_CTL_219_DATA 0x00000424
#define DDRSS_CTL_220_DATA 0x00000301
#define DDRSS_CTL_221_DATA 0x00000000
#define DDRSS_CTL_222_DATA 0x00000000
#define DDRSS_CTL_223_DATA 0x00000000
#define DDRSS_CTL_224_DATA 0x00000000
#define DDRSS_CTL_225_DATA 0x00000000
#define DDRSS_CTL_226_DATA 0x00000000
#define DDRSS_CTL_227_DATA 0x00000000
#define DDRSS_CTL_228_DATA 0x00000000
#define DDRSS_CTL_229_DATA 0x00000000
#define DDRSS_CTL_230_DATA 0x00000000
#define DDRSS_CTL_231_DATA 0x00000000
#define DDRSS_CTL_232_DATA 0x00000000
#define DDRSS_CTL_233_DATA 0x00000000
#define DDRSS_CTL_234_DATA 0x00000000
#define DDRSS_CTL_235_DATA 0x00000000
#define DDRSS_CTL_236_DATA 0x00001401
#define DDRSS_CTL_237_DATA 0x00001401
#define DDRSS_CTL_238_DATA 0x00001401
#define DDRSS_CTL_239_DATA 0x00001401
#define DDRSS_CTL_240_DATA 0x00001401
#define DDRSS_CTL_241_DATA 0x00001401
#define DDRSS_CTL_242_DATA 0x00000493
#define DDRSS_CTL_243_DATA 0x00000493
#define DDRSS_CTL_244_DATA 0x00000493
#define DDRSS_CTL_245_DATA 0x00000493
#define DDRSS_CTL_246_DATA 0x00000493
#define DDRSS_CTL_247_DATA 0x00000493
#define DDRSS_CTL_248_DATA 0x00000000
#define DDRSS_CTL_249_DATA 0x00000000
#define DDRSS_CTL_250_DATA 0x00000000
#define DDRSS_CTL_251_DATA 0x00000000
#define DDRSS_CTL_252_DATA 0x00000000
#define DDRSS_CTL_253_DATA 0x00000000
#define DDRSS_CTL_254_DATA 0x00000000
#define DDRSS_CTL_255_DATA 0x00000000
#define DDRSS_CTL_256_DATA 0x00000000
#define DDRSS_CTL_257_DATA 0x00000000
#define DDRSS_CTL_258_DATA 0x00000000
#define DDRSS_CTL_259_DATA 0x00000000
#define DDRSS_CTL_260_DATA 0x00000000
#define DDRSS_CTL_261_DATA 0x00000000
#define DDRSS_CTL_262_DATA 0x00000000
#define DDRSS_CTL_263_DATA 0x00000000
#define DDRSS_CTL_264_DATA 0x00000000
#define DDRSS_CTL_265_DATA 0x00000000
#define DDRSS_CTL_266_DATA 0x00000000
#define DDRSS_CTL_267_DATA 0x00000000
#define DDRSS_CTL_268_DATA 0x00000000
#define DDRSS_CTL_269_DATA 0x00000000
#define DDRSS_CTL_270_DATA 0x00000000
#define DDRSS_CTL_271_DATA 0x00000000
#define DDRSS_CTL_272_DATA 0x00000000
#define DDRSS_CTL_273_DATA 0x00000000
#define DDRSS_CTL_274_DATA 0x00000000
#define DDRSS_CTL_275_DATA 0x00000000
#define DDRSS_CTL_276_DATA 0x00000000
#define DDRSS_CTL_277_DATA 0x00010000
#define DDRSS_CTL_278_DATA 0x00000000
#define DDRSS_CTL_279_DATA 0x00000000
#define DDRSS_CTL_280_DATA 0x00000000
#define DDRSS_CTL_281_DATA 0x00000101
#define DDRSS_CTL_282_DATA 0x00000000
#define DDRSS_CTL_283_DATA 0x00000000
#define DDRSS_CTL_284_DATA 0x00000000
#define DDRSS_CTL_285_DATA 0x00000000
#define DDRSS_CTL_286_DATA 0x00000000
#define DDRSS_CTL_287_DATA 0x00000000
#define DDRSS_CTL_288_DATA 0x00000000
#define DDRSS_CTL_289_DATA 0x00000000
#define DDRSS_CTL_290_DATA 0x0C181511
#define DDRSS_CTL_291_DATA 0x00000304
#define DDRSS_CTL_292_DATA 0x00000000
#define DDRSS_CTL_293_DATA 0x00000000
#define DDRSS_CTL_294_DATA 0x00000000
#define DDRSS_CTL_295_DATA 0x00000000
#define DDRSS_CTL_296_DATA 0x00000000
#define DDRSS_CTL_297_DATA 0x00000000
#define DDRSS_CTL_298_DATA 0x00000000
#define DDRSS_CTL_299_DATA 0x00000000
#define DDRSS_CTL_300_DATA 0x00000000
#define DDRSS_CTL_301_DATA 0x00000000
#define DDRSS_CTL_302_DATA 0x00000000
#define DDRSS_CTL_303_DATA 0x00000000
#define DDRSS_CTL_304_DATA 0x00000000
#define DDRSS_CTL_305_DATA 0x00040000
#define DDRSS_CTL_306_DATA 0x00800200
#define DDRSS_CTL_307_DATA 0x00000000
#define DDRSS_CTL_308_DATA 0x02000400
#define DDRSS_CTL_309_DATA 0x00000080
#define DDRSS_CTL_310_DATA 0x00040000
#define DDRSS_CTL_311_DATA 0x00800200
#define DDRSS_CTL_312_DATA 0x00000000
#define DDRSS_CTL_313_DATA 0x00000000
#define DDRSS_CTL_314_DATA 0x00000000
#define DDRSS_CTL_315_DATA 0x00000100
#define DDRSS_CTL_316_DATA 0x01010000
#define DDRSS_CTL_317_DATA 0x00000000
#define DDRSS_CTL_318_DATA 0x3FFF0000
#define DDRSS_CTL_319_DATA 0x000FFF00
#define DDRSS_CTL_320_DATA 0xFFFFFFFF
#define DDRSS_CTL_321_DATA 0x000FFF00
#define DDRSS_CTL_322_DATA 0x0A000000
#define DDRSS_CTL_323_DATA 0x0001FFFF
#define DDRSS_CTL_324_DATA 0x01010101
#define DDRSS_CTL_325_DATA 0x01010101
#define DDRSS_CTL_326_DATA 0x00000118
#define DDRSS_CTL_327_DATA 0x00000C01
#define DDRSS_CTL_328_DATA 0x00000000
#define DDRSS_CTL_329_DATA 0x00000000
#define DDRSS_CTL_330_DATA 0x00000000
#define DDRSS_CTL_331_DATA 0x01000000
#define DDRSS_CTL_332_DATA 0x00000100
#define DDRSS_CTL_333_DATA 0x00010000
#define DDRSS_CTL_334_DATA 0x00000000
#define DDRSS_CTL_335_DATA 0x00000000
#define DDRSS_CTL_336_DATA 0x00000000
#define DDRSS_CTL_337_DATA 0x00000000
#define DDRSS_CTL_338_DATA 0x00000000
#define DDRSS_CTL_339_DATA 0x00000000
#define DDRSS_CTL_340_DATA 0x00000000
#define DDRSS_CTL_341_DATA 0x00000000
#define DDRSS_CTL_342_DATA 0x00000000
#define DDRSS_CTL_343_DATA 0x00000000
#define DDRSS_CTL_344_DATA 0x00000000
#define DDRSS_CTL_345_DATA 0x00000000
#define DDRSS_CTL_346_DATA 0x00000000
#define DDRSS_CTL_347_DATA 0x00000000
#define DDRSS_CTL_348_DATA 0x00000000
#define DDRSS_CTL_349_DATA 0x00000000
#define DDRSS_CTL_350_DATA 0x00000000
#define DDRSS_CTL_351_DATA 0x00000000
#define DDRSS_CTL_352_DATA 0x00000000
#define DDRSS_CTL_353_DATA 0x00000000
#define DDRSS_CTL_354_DATA 0x00000000
#define DDRSS_CTL_355_DATA 0x00000000
#define DDRSS_CTL_356_DATA 0x00000000
#define DDRSS_CTL_357_DATA 0x00000000
#define DDRSS_CTL_358_DATA 0x00000000
#define DDRSS_CTL_359_DATA 0x00000000
#define DDRSS_CTL_360_DATA 0x00000000
#define DDRSS_CTL_361_DATA 0x00000000
#define DDRSS_CTL_362_DATA 0x00000000
#define DDRSS_CTL_363_DATA 0x00000000
#define DDRSS_CTL_364_DATA 0x00000000
#define DDRSS_CTL_365_DATA 0x00000000
#define DDRSS_CTL_366_DATA 0x00000000
#define DDRSS_CTL_367_DATA 0x00000000
#define DDRSS_CTL_368_DATA 0x00000000
#define DDRSS_CTL_369_DATA 0x00000000
#define DDRSS_CTL_370_DATA 0x0C000000
#define DDRSS_CTL_371_DATA 0x060C0606
#define DDRSS_CTL_372_DATA 0x06060C06
#define DDRSS_CTL_373_DATA 0x00010101
#define DDRSS_CTL_374_DATA 0x02000000
#define DDRSS_CTL_375_DATA 0x05020101
#define DDRSS_CTL_376_DATA 0x00000505
#define DDRSS_CTL_377_DATA 0x02020200
#define DDRSS_CTL_378_DATA 0x02020202
#define DDRSS_CTL_379_DATA 0x02020202
#define DDRSS_CTL_380_DATA 0x02020202
#define DDRSS_CTL_381_DATA 0x00000000
#define DDRSS_CTL_382_DATA 0x00000000
#define DDRSS_CTL_383_DATA 0x04000100
#define DDRSS_CTL_384_DATA 0x1E000004
#define DDRSS_CTL_385_DATA 0x000030C0
#define DDRSS_CTL_386_DATA 0x00000200
#define DDRSS_CTL_387_DATA 0x00000200
#define DDRSS_CTL_388_DATA 0x00000200
#define DDRSS_CTL_389_DATA 0x00000200
#define DDRSS_CTL_390_DATA 0x0000DB60
#define DDRSS_CTL_391_DATA 0x0001E780
#define DDRSS_CTL_392_DATA 0x0C0D0302
#define DDRSS_CTL_393_DATA 0x001E090A
#define DDRSS_CTL_394_DATA 0x000030C0
#define DDRSS_CTL_395_DATA 0x00000200
#define DDRSS_CTL_396_DATA 0x00000200
#define DDRSS_CTL_397_DATA 0x00000200
#define DDRSS_CTL_398_DATA 0x00000200
#define DDRSS_CTL_399_DATA 0x0000DB60
#define DDRSS_CTL_400_DATA 0x0001E780
#define DDRSS_CTL_401_DATA 0x0C0D0302
#define DDRSS_CTL_402_DATA 0x001E090A
#define DDRSS_CTL_403_DATA 0x000030C0
#define DDRSS_CTL_404_DATA 0x00000200
#define DDRSS_CTL_405_DATA 0x00000200
#define DDRSS_CTL_406_DATA 0x00000200
#define DDRSS_CTL_407_DATA 0x00000200
#define DDRSS_CTL_408_DATA 0x0000DB60
#define DDRSS_CTL_409_DATA 0x0001E780
#define DDRSS_CTL_410_DATA 0x0C0D0302
#define DDRSS_CTL_411_DATA 0x0000090A
#define DDRSS_CTL_412_DATA 0x00000000
#define DDRSS_CTL_413_DATA 0x0302000A
#define DDRSS_CTL_414_DATA 0x01000500
#define DDRSS_CTL_415_DATA 0x01010001
#define DDRSS_CTL_416_DATA 0x00010001
#define DDRSS_CTL_417_DATA 0x01010001
#define DDRSS_CTL_418_DATA 0x02010000
#define DDRSS_CTL_419_DATA 0x00000200
#define DDRSS_CTL_420_DATA 0x02000201
#define DDRSS_CTL_421_DATA 0x00000000
#define DDRSS_CTL_422_DATA 0x00202020
#define DDRSS_PI_0_DATA 0x00000A00
#define DDRSS_PI_1_DATA 0x00000000
#define DDRSS_PI_2_DATA 0x00000000
#define DDRSS_PI_3_DATA 0x01000000
#define DDRSS_PI_4_DATA 0x00000001
#define DDRSS_PI_5_DATA 0x00010064
#define DDRSS_PI_6_DATA 0x00000000
#define DDRSS_PI_7_DATA 0x00000000
#define DDRSS_PI_8_DATA 0x00000000
#define DDRSS_PI_9_DATA 0x00000000
#define DDRSS_PI_10_DATA 0x00000000
#define DDRSS_PI_11_DATA 0x00000000
#define DDRSS_PI_12_DATA 0x00000000
#define DDRSS_PI_13_DATA 0x00010001
#define DDRSS_PI_14_DATA 0x00000000
#define DDRSS_PI_15_DATA 0x00010001
#define DDRSS_PI_16_DATA 0x00000005
#define DDRSS_PI_17_DATA 0x00000000
#define DDRSS_PI_18_DATA 0x00000000
#define DDRSS_PI_19_DATA 0x00000000
#define DDRSS_PI_20_DATA 0x00000000
#define DDRSS_PI_21_DATA 0x00000000
#define DDRSS_PI_22_DATA 0x00000000
#define DDRSS_PI_23_DATA 0x00000000
#define DDRSS_PI_24_DATA 0x280D0001
#define DDRSS_PI_25_DATA 0x00000000
#define DDRSS_PI_26_DATA 0x00010000
#define DDRSS_PI_27_DATA 0x00003200
#define DDRSS_PI_28_DATA 0x00000000
#define DDRSS_PI_29_DATA 0x00000000
#define DDRSS_PI_30_DATA 0x00060602
#define DDRSS_PI_31_DATA 0x00000000
#define DDRSS_PI_32_DATA 0x00000000
#define DDRSS_PI_33_DATA 0x00000000
#define DDRSS_PI_34_DATA 0x00000001
#define DDRSS_PI_35_DATA 0x00000055
#define DDRSS_PI_36_DATA 0x000000AA
#define DDRSS_PI_37_DATA 0x000000AD
#define DDRSS_PI_38_DATA 0x00000052
#define DDRSS_PI_39_DATA 0x0000006A
#define DDRSS_PI_40_DATA 0x00000095
#define DDRSS_PI_41_DATA 0x00000095
#define DDRSS_PI_42_DATA 0x000000AD
#define DDRSS_PI_43_DATA 0x00000000
#define DDRSS_PI_44_DATA 0x00000000
#define DDRSS_PI_45_DATA 0x00010100
#define DDRSS_PI_46_DATA 0x00000014
#define DDRSS_PI_47_DATA 0x000007D0
#define DDRSS_PI_48_DATA 0x00000300
#define DDRSS_PI_49_DATA 0x00000000
#define DDRSS_PI_50_DATA 0x00000000
#define DDRSS_PI_51_DATA 0x01000000
#define DDRSS_PI_52_DATA 0x00010101
#define DDRSS_PI_53_DATA 0x01000000
#define DDRSS_PI_54_DATA 0x00000000
#define DDRSS_PI_55_DATA 0x00010000
#define DDRSS_PI_56_DATA 0x00000000
#define DDRSS_PI_57_DATA 0x00000000
#define DDRSS_PI_58_DATA 0x00000000
#define DDRSS_PI_59_DATA 0x00000000
#define DDRSS_PI_60_DATA 0x00001400
#define DDRSS_PI_61_DATA 0x00000000
#define DDRSS_PI_62_DATA 0x01000000
#define DDRSS_PI_63_DATA 0x00000404
#define DDRSS_PI_64_DATA 0x00000001
#define DDRSS_PI_65_DATA 0x0001010E
#define DDRSS_PI_66_DATA 0x02040100
#define DDRSS_PI_67_DATA 0x00010000
#define DDRSS_PI_68_DATA 0x00000034
#define DDRSS_PI_69_DATA 0x00000000
#define DDRSS_PI_70_DATA 0x00000000
#define DDRSS_PI_71_DATA 0x00000000
#define DDRSS_PI_72_DATA 0x00000000
#define DDRSS_PI_73_DATA 0x00000000
#define DDRSS_PI_74_DATA 0x00000000
#define DDRSS_PI_75_DATA 0x00000005
#define DDRSS_PI_76_DATA 0x01000000
#define DDRSS_PI_77_DATA 0x04000100
#define DDRSS_PI_78_DATA 0x00020000
#define DDRSS_PI_79_DATA 0x00010002
#define DDRSS_PI_80_DATA 0x00000001
#define DDRSS_PI_81_DATA 0x00020001
#define DDRSS_PI_82_DATA 0x00020002
#define DDRSS_PI_83_DATA 0x00000000
#define DDRSS_PI_84_DATA 0x00000000
#define DDRSS_PI_85_DATA 0x00000000
#define DDRSS_PI_86_DATA 0x00000000
#define DDRSS_PI_87_DATA 0x00000000
#define DDRSS_PI_88_DATA 0x00000000
#define DDRSS_PI_89_DATA 0x00000000
#define DDRSS_PI_90_DATA 0x00000000
#define DDRSS_PI_91_DATA 0x00000300
#define DDRSS_PI_92_DATA 0x0A090B0C
#define DDRSS_PI_93_DATA 0x04060708
#define DDRSS_PI_94_DATA 0x01000005
#define DDRSS_PI_95_DATA 0x00000800
#define DDRSS_PI_96_DATA 0x00000000
#define DDRSS_PI_97_DATA 0x00010008
#define DDRSS_PI_98_DATA 0x00000000
#define DDRSS_PI_99_DATA 0x0000AA00
#define DDRSS_PI_100_DATA 0x00000000
#define DDRSS_PI_101_DATA 0x00010000
#define DDRSS_PI_102_DATA 0x00000000
#define DDRSS_PI_103_DATA 0x00000000
#define DDRSS_PI_104_DATA 0x00000000
#define DDRSS_PI_105_DATA 0x00000000
#define DDRSS_PI_106_DATA 0x00000000
#define DDRSS_PI_107_DATA 0x00000000
#define DDRSS_PI_108_DATA 0x00000000
#define DDRSS_PI_109_DATA 0x00000000
#define DDRSS_PI_110_DATA 0x00000000
#define DDRSS_PI_111_DATA 0x00000000
#define DDRSS_PI_112_DATA 0x00000000
#define DDRSS_PI_113_DATA 0x00000000
#define DDRSS_PI_114_DATA 0x00000000
#define DDRSS_PI_115_DATA 0x00000000
#define DDRSS_PI_116_DATA 0x00000000
#define DDRSS_PI_117_DATA 0x00000000
#define DDRSS_PI_118_DATA 0x00000000
#define DDRSS_PI_119_DATA 0x00000000
#define DDRSS_PI_120_DATA 0x00000000
#define DDRSS_PI_121_DATA 0x00000000
#define DDRSS_PI_122_DATA 0x00000000
#define DDRSS_PI_123_DATA 0x00000000
#define DDRSS_PI_124_DATA 0x00000008
#define DDRSS_PI_125_DATA 0x00000000
#define DDRSS_PI_126_DATA 0x00000000
#define DDRSS_PI_127_DATA 0x00000000
#define DDRSS_PI_128_DATA 0x00000000
#define DDRSS_PI_129_DATA 0x00000000
#define DDRSS_PI_130_DATA 0x00000000
#define DDRSS_PI_131_DATA 0x00000000
#define DDRSS_PI_132_DATA 0x00000000
#define DDRSS_PI_133_DATA 0x00010100
#define DDRSS_PI_134_DATA 0x00000000
#define DDRSS_PI_135_DATA 0x00000000
#define DDRSS_PI_136_DATA 0x00027100
#define DDRSS_PI_137_DATA 0x00061A80
#define DDRSS_PI_138_DATA 0x00000100
#define DDRSS_PI_139_DATA 0x00000000
#define DDRSS_PI_140_DATA 0x00000000
#define DDRSS_PI_141_DATA 0x00000000
#define DDRSS_PI_142_DATA 0x00000000
#define DDRSS_PI_143_DATA 0x00000000
#define DDRSS_PI_144_DATA 0x01000000
#define DDRSS_PI_145_DATA 0x00010003
#define DDRSS_PI_146_DATA 0x02000101
#define DDRSS_PI_147_DATA 0x01030001
#define DDRSS_PI_148_DATA 0x00010400
#define DDRSS_PI_149_DATA 0x06000105
#define DDRSS_PI_150_DATA 0x01070001
#define DDRSS_PI_151_DATA 0x00000000
#define DDRSS_PI_152_DATA 0x00000000
#define DDRSS_PI_153_DATA 0x00000000
#define DDRSS_PI_154_DATA 0x00010000
#define DDRSS_PI_155_DATA 0x00000000
#define DDRSS_PI_156_DATA 0x00000000
#define DDRSS_PI_157_DATA 0x00000000
#define DDRSS_PI_158_DATA 0x00000000
#define DDRSS_PI_159_DATA 0x00010000
#define DDRSS_PI_160_DATA 0x00000004
#define DDRSS_PI_161_DATA 0x00000000
#define DDRSS_PI_162_DATA 0x00000000
#define DDRSS_PI_163_DATA 0x00000000
#define DDRSS_PI_164_DATA 0x00007800
#define DDRSS_PI_165_DATA 0x00780078
#define DDRSS_PI_166_DATA 0x00141414
#define DDRSS_PI_167_DATA 0x0000003A
#define DDRSS_PI_168_DATA 0x0000003A
#define DDRSS_PI_169_DATA 0x0004003A
#define DDRSS_PI_170_DATA 0x04000400
#define DDRSS_PI_171_DATA 0xC8040009
#define DDRSS_PI_172_DATA 0x0400091C
#define DDRSS_PI_173_DATA 0x00091CC8
#define DDRSS_PI_174_DATA 0x001CC804
#define DDRSS_PI_175_DATA 0x00000118
#define DDRSS_PI_176_DATA 0x00001860
#define DDRSS_PI_177_DATA 0x00000118
#define DDRSS_PI_178_DATA 0x00001860
#define DDRSS_PI_179_DATA 0x00000118
#define DDRSS_PI_180_DATA 0x04001860
#define DDRSS_PI_181_DATA 0x01010404
#define DDRSS_PI_182_DATA 0x00001901
#define DDRSS_PI_183_DATA 0x00190019
#define DDRSS_PI_184_DATA 0x010C010C
#define DDRSS_PI_185_DATA 0x0000010C
#define DDRSS_PI_186_DATA 0x00000000
#define DDRSS_PI_187_DATA 0x05000000
#define DDRSS_PI_188_DATA 0x01010505
#define DDRSS_PI_189_DATA 0x01010101
#define DDRSS_PI_190_DATA 0x00181818
#define DDRSS_PI_191_DATA 0x00000000
#define DDRSS_PI_192_DATA 0x00000000
#define DDRSS_PI_193_DATA 0x0D000000
#define DDRSS_PI_194_DATA 0x0A0A0D0D
#define DDRSS_PI_195_DATA 0x0303030A
#define DDRSS_PI_196_DATA 0x00000000
#define DDRSS_PI_197_DATA 0x00000000
#define DDRSS_PI_198_DATA 0x00000000
#define DDRSS_PI_199_DATA 0x00000000
#define DDRSS_PI_200_DATA 0x00000000
#define DDRSS_PI_201_DATA 0x00000000
#define DDRSS_PI_202_DATA 0x00000000
#define DDRSS_PI_203_DATA 0x00000000
#define DDRSS_PI_204_DATA 0x00000000
#define DDRSS_PI_205_DATA 0x00000000
#define DDRSS_PI_206_DATA 0x00000000
#define DDRSS_PI_207_DATA 0x00000000
#define DDRSS_PI_208_DATA 0x00000000
#define DDRSS_PI_209_DATA 0x0D090000
#define DDRSS_PI_210_DATA 0x0D09000D
#define DDRSS_PI_211_DATA 0x0D09000D
#define DDRSS_PI_212_DATA 0x0000000D
#define DDRSS_PI_213_DATA 0x00000000
#define DDRSS_PI_214_DATA 0x00000000
#define DDRSS_PI_215_DATA 0x00000000
#define DDRSS_PI_216_DATA 0x00000000
#define DDRSS_PI_217_DATA 0x16000000
#define DDRSS_PI_218_DATA 0x001600C8
#define DDRSS_PI_219_DATA 0x001600C8
#define DDRSS_PI_220_DATA 0x010100C8
#define DDRSS_PI_221_DATA 0x00001B01
#define DDRSS_PI_222_DATA 0x1F0F0053
#define DDRSS_PI_223_DATA 0x05000001
#define DDRSS_PI_224_DATA 0x001B0A0D
#define DDRSS_PI_225_DATA 0x1F0F0053
#define DDRSS_PI_226_DATA 0x05000001
#define DDRSS_PI_227_DATA 0x001B0A0D
#define DDRSS_PI_228_DATA 0x1F0F0053
#define DDRSS_PI_229_DATA 0x05000001
#define DDRSS_PI_230_DATA 0x00010A0D
#define DDRSS_PI_231_DATA 0x0C0B0700
#define DDRSS_PI_232_DATA 0x000D0605
#define DDRSS_PI_233_DATA 0x0000C570
#define DDRSS_PI_234_DATA 0x0000001D
#define DDRSS_PI_235_DATA 0x180A0800
#define DDRSS_PI_236_DATA 0x0B071C1C
#define DDRSS_PI_237_DATA 0x0D06050C
#define DDRSS_PI_238_DATA 0x0000C570
#define DDRSS_PI_239_DATA 0x0000001D
#define DDRSS_PI_240_DATA 0x180A0800
#define DDRSS_PI_241_DATA 0x0B071C1C
#define DDRSS_PI_242_DATA 0x0D06050C
#define DDRSS_PI_243_DATA 0x0000C570
#define DDRSS_PI_244_DATA 0x0000001D
#define DDRSS_PI_245_DATA 0x180A0800
#define DDRSS_PI_246_DATA 0x00001C1C
#define DDRSS_PI_247_DATA 0x000030C0
#define DDRSS_PI_248_DATA 0x0001E780
#define DDRSS_PI_249_DATA 0x000030C0
#define DDRSS_PI_250_DATA 0x0001E780
#define DDRSS_PI_251_DATA 0x000030C0
#define DDRSS_PI_252_DATA 0x0001E780
#define DDRSS_PI_253_DATA 0x02550255
#define DDRSS_PI_254_DATA 0x03030255
#define DDRSS_PI_255_DATA 0x00025503
#define DDRSS_PI_256_DATA 0x02550255
#define DDRSS_PI_257_DATA 0x0C080C08
#define DDRSS_PI_258_DATA 0x00000C08
#define DDRSS_PI_259_DATA 0x000890B8
#define DDRSS_PI_260_DATA 0x00000000
#define DDRSS_PI_261_DATA 0x00000000
#define DDRSS_PI_262_DATA 0x00000000
#define DDRSS_PI_263_DATA 0x00000120
#define DDRSS_PI_264_DATA 0x000890B8
#define DDRSS_PI_265_DATA 0x00000000
#define DDRSS_PI_266_DATA 0x00000000
#define DDRSS_PI_267_DATA 0x00000000
#define DDRSS_PI_268_DATA 0x00000120
#define DDRSS_PI_269_DATA 0x000890B8
#define DDRSS_PI_270_DATA 0x00000000
#define DDRSS_PI_271_DATA 0x00000000
#define DDRSS_PI_272_DATA 0x00000000
#define DDRSS_PI_273_DATA 0x02000120
#define DDRSS_PI_274_DATA 0x00000080
#define DDRSS_PI_275_DATA 0x00020000
#define DDRSS_PI_276_DATA 0x00000080
#define DDRSS_PI_277_DATA 0x00020000
#define DDRSS_PI_278_DATA 0x00000080
#define DDRSS_PI_279_DATA 0x00000000
#define DDRSS_PI_280_DATA 0x00000000
#define DDRSS_PI_281_DATA 0x00040404
#define DDRSS_PI_282_DATA 0x00000000
#define DDRSS_PI_283_DATA 0x02010102
#define DDRSS_PI_284_DATA 0x67676767
#define DDRSS_PI_285_DATA 0x00000202
#define DDRSS_PI_286_DATA 0x00000000
#define DDRSS_PI_287_DATA 0x00000000
#define DDRSS_PI_288_DATA 0x00000000
#define DDRSS_PI_289_DATA 0x00000000
#define DDRSS_PI_290_DATA 0x00000000
#define DDRSS_PI_291_DATA 0x0D100F00
#define DDRSS_PI_292_DATA 0x0003020E
#define DDRSS_PI_293_DATA 0x00000001
#define DDRSS_PI_294_DATA 0x01000000
#define DDRSS_PI_295_DATA 0x00020201
#define DDRSS_PI_296_DATA 0x00000000
#define DDRSS_PI_297_DATA 0x00000424
#define DDRSS_PI_298_DATA 0x00000301
#define DDRSS_PI_299_DATA 0x00000000
#define DDRSS_PI_300_DATA 0x00000000
#define DDRSS_PI_301_DATA 0x00000000
#define DDRSS_PI_302_DATA 0x00001401
#define DDRSS_PI_303_DATA 0x00000493
#define DDRSS_PI_304_DATA 0x00000000
#define DDRSS_PI_305_DATA 0x00000424
#define DDRSS_PI_306_DATA 0x00000301
#define DDRSS_PI_307_DATA 0x00000000
#define DDRSS_PI_308_DATA 0x00000000
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_310_DATA 0x00001401
#define DDRSS_PI_311_DATA 0x00000493
#define DDRSS_PI_312_DATA 0x00000000
#define DDRSS_PI_313_DATA 0x00000424
#define DDRSS_PI_314_DATA 0x00000301
#define DDRSS_PI_315_DATA 0x00000000
#define DDRSS_PI_316_DATA 0x00000000
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_318_DATA 0x00001401
#define DDRSS_PI_319_DATA 0x00000493
#define DDRSS_PI_320_DATA 0x00000000
#define DDRSS_PI_321_DATA 0x00000424
#define DDRSS_PI_322_DATA 0x00000301
#define DDRSS_PI_323_DATA 0x00000000
#define DDRSS_PI_324_DATA 0x00000000
#define DDRSS_PI_325_DATA 0x00000000
#define DDRSS_PI_326_DATA 0x00001401
#define DDRSS_PI_327_DATA 0x00000493
#define DDRSS_PI_328_DATA 0x00000000
#define DDRSS_PI_329_DATA 0x00000424
#define DDRSS_PI_330_DATA 0x00000301
#define DDRSS_PI_331_DATA 0x00000000
#define DDRSS_PI_332_DATA 0x00000000
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_334_DATA 0x00001401
#define DDRSS_PI_335_DATA 0x00000493
#define DDRSS_PI_336_DATA 0x00000000
#define DDRSS_PI_337_DATA 0x00000424
#define DDRSS_PI_338_DATA 0x00000301
#define DDRSS_PI_339_DATA 0x00000000
#define DDRSS_PI_340_DATA 0x00000000
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_342_DATA 0x00001401
#define DDRSS_PI_343_DATA 0x00000493
#define DDRSS_PI_344_DATA 0x00000000
#define DDRSS_PHY_0_DATA 0x04C00000
#define DDRSS_PHY_1_DATA 0x00000000
#define DDRSS_PHY_2_DATA 0x00000200
#define DDRSS_PHY_3_DATA 0x00000000
#define DDRSS_PHY_4_DATA 0x00000000
#define DDRSS_PHY_5_DATA 0x00000000
#define DDRSS_PHY_6_DATA 0x00000000
#define DDRSS_PHY_7_DATA 0x00000000
#define DDRSS_PHY_8_DATA 0x00000001
#define DDRSS_PHY_9_DATA 0x00000000
#define DDRSS_PHY_10_DATA 0x00000000
#define DDRSS_PHY_11_DATA 0x010101FF
#define DDRSS_PHY_12_DATA 0x00010000
#define DDRSS_PHY_13_DATA 0x00C00004
#define DDRSS_PHY_14_DATA 0x00CC0008
#define DDRSS_PHY_15_DATA 0x00660201
#define DDRSS_PHY_16_DATA 0x00000000
#define DDRSS_PHY_17_DATA 0x00000000
#define DDRSS_PHY_18_DATA 0x00000000
#define DDRSS_PHY_19_DATA 0x0000AAAA
#define DDRSS_PHY_20_DATA 0x00005555
#define DDRSS_PHY_21_DATA 0x0000B5B5
#define DDRSS_PHY_22_DATA 0x00004A4A
#define DDRSS_PHY_23_DATA 0x00005656
#define DDRSS_PHY_24_DATA 0x0000A9A9
#define DDRSS_PHY_25_DATA 0x0000B7B7
#define DDRSS_PHY_26_DATA 0x00004848
#define DDRSS_PHY_27_DATA 0x00000000
#define DDRSS_PHY_28_DATA 0x00000000
#define DDRSS_PHY_29_DATA 0x08000000
#define DDRSS_PHY_30_DATA 0x0F000008
#define DDRSS_PHY_31_DATA 0x00000F0F
#define DDRSS_PHY_32_DATA 0x00E4E400
#define DDRSS_PHY_33_DATA 0x00070820
#define DDRSS_PHY_34_DATA 0x000C0020
#define DDRSS_PHY_35_DATA 0x00062000
#define DDRSS_PHY_36_DATA 0x00000000
#define DDRSS_PHY_37_DATA 0x55555555
#define DDRSS_PHY_38_DATA 0xAAAAAAAA
#define DDRSS_PHY_39_DATA 0x55555555
#define DDRSS_PHY_40_DATA 0xAAAAAAAA
#define DDRSS_PHY_41_DATA 0x00005555
#define DDRSS_PHY_42_DATA 0x01000100
#define DDRSS_PHY_43_DATA 0x00800180
#define DDRSS_PHY_44_DATA 0x00000000
#define DDRSS_PHY_45_DATA 0x00000000
#define DDRSS_PHY_46_DATA 0x00000000
#define DDRSS_PHY_47_DATA 0x00000000
#define DDRSS_PHY_48_DATA 0x00000000
#define DDRSS_PHY_49_DATA 0x00000000
#define DDRSS_PHY_50_DATA 0x00000000
#define DDRSS_PHY_51_DATA 0x00000000
#define DDRSS_PHY_52_DATA 0x00000000
#define DDRSS_PHY_53_DATA 0x00000000
#define DDRSS_PHY_54_DATA 0x00000000
#define DDRSS_PHY_55_DATA 0x00000000
#define DDRSS_PHY_56_DATA 0x00000000
#define DDRSS_PHY_57_DATA 0x00000000
#define DDRSS_PHY_58_DATA 0x00000000
#define DDRSS_PHY_59_DATA 0x00000000
#define DDRSS_PHY_60_DATA 0x00000000
#define DDRSS_PHY_61_DATA 0x00000000
#define DDRSS_PHY_62_DATA 0x00000000
#define DDRSS_PHY_63_DATA 0x00000000
#define DDRSS_PHY_64_DATA 0x00000000
#define DDRSS_PHY_65_DATA 0x00000004
#define DDRSS_PHY_66_DATA 0x00000000
#define DDRSS_PHY_67_DATA 0x00000000
#define DDRSS_PHY_68_DATA 0x00000000
#define DDRSS_PHY_69_DATA 0x00000000
#define DDRSS_PHY_70_DATA 0x00000000
#define DDRSS_PHY_71_DATA 0x00000000
#define DDRSS_PHY_72_DATA 0x041F07FF
#define DDRSS_PHY_73_DATA 0x00000000
#define DDRSS_PHY_74_DATA 0x01CCB001
#define DDRSS_PHY_75_DATA 0x2000CCB0
#define DDRSS_PHY_76_DATA 0x20000140
#define DDRSS_PHY_77_DATA 0x07FF0200
#define DDRSS_PHY_78_DATA 0x0000DD01
#define DDRSS_PHY_79_DATA 0x10100303
#define DDRSS_PHY_80_DATA 0x10101010
#define DDRSS_PHY_81_DATA 0x10101010
#define DDRSS_PHY_82_DATA 0x00021010
#define DDRSS_PHY_83_DATA 0x00100010
#define DDRSS_PHY_84_DATA 0x00100010
#define DDRSS_PHY_85_DATA 0x00100010
#define DDRSS_PHY_86_DATA 0x00100010
#define DDRSS_PHY_87_DATA 0x02020010
#define DDRSS_PHY_88_DATA 0x51515041
#define DDRSS_PHY_89_DATA 0x31804000
#define DDRSS_PHY_90_DATA 0x04BF0340
#define DDRSS_PHY_91_DATA 0x01008080
#define DDRSS_PHY_92_DATA 0x04050001
#define DDRSS_PHY_93_DATA 0x00000504
#define DDRSS_PHY_94_DATA 0x42100010
#define DDRSS_PHY_95_DATA 0x010C053E
#define DDRSS_PHY_96_DATA 0x000F0C14
#define DDRSS_PHY_97_DATA 0x01000140
#define DDRSS_PHY_98_DATA 0x007A0120
#define DDRSS_PHY_99_DATA 0x00000C00
#define DDRSS_PHY_100_DATA 0x000001CC
#define DDRSS_PHY_101_DATA 0x20100200
#define DDRSS_PHY_102_DATA 0x00000005
#define DDRSS_PHY_103_DATA 0x76543210
#define DDRSS_PHY_104_DATA 0x00000008
#define DDRSS_PHY_105_DATA 0x02800280
#define DDRSS_PHY_106_DATA 0x02800280
#define DDRSS_PHY_107_DATA 0x02800280
#define DDRSS_PHY_108_DATA 0x02800280
#define DDRSS_PHY_109_DATA 0x00000280
#define DDRSS_PHY_110_DATA 0x00008000
#define DDRSS_PHY_111_DATA 0x00800080
#define DDRSS_PHY_112_DATA 0x00800080
#define DDRSS_PHY_113_DATA 0x00800080
#define DDRSS_PHY_114_DATA 0x00800080
#define DDRSS_PHY_115_DATA 0x00800080
#define DDRSS_PHY_116_DATA 0x00800080
#define DDRSS_PHY_117_DATA 0x00800080
#define DDRSS_PHY_118_DATA 0x00800080
#define DDRSS_PHY_119_DATA 0x01000080
#define DDRSS_PHY_120_DATA 0x01A00000
#define DDRSS_PHY_121_DATA 0x00000000
#define DDRSS_PHY_122_DATA 0x00000000
#define DDRSS_PHY_123_DATA 0x00080200
#define DDRSS_PHY_124_DATA 0x00000000
#define DDRSS_PHY_125_DATA 0x00000000
#define DDRSS_PHY_126_DATA 0x00000000
#define DDRSS_PHY_127_DATA 0x00000000
#define DDRSS_PHY_128_DATA 0x00000000
#define DDRSS_PHY_129_DATA 0x00000000
#define DDRSS_PHY_130_DATA 0x00000000
#define DDRSS_PHY_131_DATA 0x00000000
#define DDRSS_PHY_132_DATA 0x00000000
#define DDRSS_PHY_133_DATA 0x00000000
#define DDRSS_PHY_134_DATA 0x00000000
#define DDRSS_PHY_135_DATA 0x00000000
#define DDRSS_PHY_136_DATA 0x00000000
#define DDRSS_PHY_137_DATA 0x00000000
#define DDRSS_PHY_138_DATA 0x00000000
#define DDRSS_PHY_139_DATA 0x00000000
#define DDRSS_PHY_140_DATA 0x00000000
#define DDRSS_PHY_141_DATA 0x00000000
#define DDRSS_PHY_142_DATA 0x00000000
#define DDRSS_PHY_143_DATA 0x00000000
#define DDRSS_PHY_144_DATA 0x00000000
#define DDRSS_PHY_145_DATA 0x00000000
#define DDRSS_PHY_146_DATA 0x00000000
#define DDRSS_PHY_147_DATA 0x00000000
#define DDRSS_PHY_148_DATA 0x00000000
#define DDRSS_PHY_149_DATA 0x00000000
#define DDRSS_PHY_150_DATA 0x00000000
#define DDRSS_PHY_151_DATA 0x00000000
#define DDRSS_PHY_152_DATA 0x00000000
#define DDRSS_PHY_153_DATA 0x00000000
#define DDRSS_PHY_154_DATA 0x00000000
#define DDRSS_PHY_155_DATA 0x00000000
#define DDRSS_PHY_156_DATA 0x00000000
#define DDRSS_PHY_157_DATA 0x00000000
#define DDRSS_PHY_158_DATA 0x00000000
#define DDRSS_PHY_159_DATA 0x00000000
#define DDRSS_PHY_160_DATA 0x00000000
#define DDRSS_PHY_161_DATA 0x00000000
#define DDRSS_PHY_162_DATA 0x00000000
#define DDRSS_PHY_163_DATA 0x00000000
#define DDRSS_PHY_164_DATA 0x00000000
#define DDRSS_PHY_165_DATA 0x00000000
#define DDRSS_PHY_166_DATA 0x00000000
#define DDRSS_PHY_167_DATA 0x00000000
#define DDRSS_PHY_168_DATA 0x00000000
#define DDRSS_PHY_169_DATA 0x00000000
#define DDRSS_PHY_170_DATA 0x00000000
#define DDRSS_PHY_171_DATA 0x00000000
#define DDRSS_PHY_172_DATA 0x00000000
#define DDRSS_PHY_173_DATA 0x00000000
#define DDRSS_PHY_174_DATA 0x00000000
#define DDRSS_PHY_175_DATA 0x00000000
#define DDRSS_PHY_176_DATA 0x00000000
#define DDRSS_PHY_177_DATA 0x00000000
#define DDRSS_PHY_178_DATA 0x00000000
#define DDRSS_PHY_179_DATA 0x00000000
#define DDRSS_PHY_180_DATA 0x00000000
#define DDRSS_PHY_181_DATA 0x00000000
#define DDRSS_PHY_182_DATA 0x00000000
#define DDRSS_PHY_183_DATA 0x00000000
#define DDRSS_PHY_184_DATA 0x00000000
#define DDRSS_PHY_185_DATA 0x00000000
#define DDRSS_PHY_186_DATA 0x00000000
#define DDRSS_PHY_187_DATA 0x00000000
#define DDRSS_PHY_188_DATA 0x00000000
#define DDRSS_PHY_189_DATA 0x00000000
#define DDRSS_PHY_190_DATA 0x00000000
#define DDRSS_PHY_191_DATA 0x00000000
#define DDRSS_PHY_192_DATA 0x00000000
#define DDRSS_PHY_193_DATA 0x00000000
#define DDRSS_PHY_194_DATA 0x00000000
#define DDRSS_PHY_195_DATA 0x00000000
#define DDRSS_PHY_196_DATA 0x00000000
#define DDRSS_PHY_197_DATA 0x00000000
#define DDRSS_PHY_198_DATA 0x00000000
#define DDRSS_PHY_199_DATA 0x00000000
#define DDRSS_PHY_200_DATA 0x00000000
#define DDRSS_PHY_201_DATA 0x00000000
#define DDRSS_PHY_202_DATA 0x00000000
#define DDRSS_PHY_203_DATA 0x00000000
#define DDRSS_PHY_204_DATA 0x00000000
#define DDRSS_PHY_205_DATA 0x00000000
#define DDRSS_PHY_206_DATA 0x00000000
#define DDRSS_PHY_207_DATA 0x00000000
#define DDRSS_PHY_208_DATA 0x00000000
#define DDRSS_PHY_209_DATA 0x00000000
#define DDRSS_PHY_210_DATA 0x00000000
#define DDRSS_PHY_211_DATA 0x00000000
#define DDRSS_PHY_212_DATA 0x00000000
#define DDRSS_PHY_213_DATA 0x00000000
#define DDRSS_PHY_214_DATA 0x00000000
#define DDRSS_PHY_215_DATA 0x00000000
#define DDRSS_PHY_216_DATA 0x00000000
#define DDRSS_PHY_217_DATA 0x00000000
#define DDRSS_PHY_218_DATA 0x00000000
#define DDRSS_PHY_219_DATA 0x00000000
#define DDRSS_PHY_220_DATA 0x00000000
#define DDRSS_PHY_221_DATA 0x00000000
#define DDRSS_PHY_222_DATA 0x00000000
#define DDRSS_PHY_223_DATA 0x00000000
#define DDRSS_PHY_224_DATA 0x00000000
#define DDRSS_PHY_225_DATA 0x00000000
#define DDRSS_PHY_226_DATA 0x00000000
#define DDRSS_PHY_227_DATA 0x00000000
#define DDRSS_PHY_228_DATA 0x00000000
#define DDRSS_PHY_229_DATA 0x00000000
#define DDRSS_PHY_230_DATA 0x00000000
#define DDRSS_PHY_231_DATA 0x00000000
#define DDRSS_PHY_232_DATA 0x00000000
#define DDRSS_PHY_233_DATA 0x00000000
#define DDRSS_PHY_234_DATA 0x00000000
#define DDRSS_PHY_235_DATA 0x00000000
#define DDRSS_PHY_236_DATA 0x00000000
#define DDRSS_PHY_237_DATA 0x00000000
#define DDRSS_PHY_238_DATA 0x00000000
#define DDRSS_PHY_239_DATA 0x00000000
#define DDRSS_PHY_240_DATA 0x00000000
#define DDRSS_PHY_241_DATA 0x00000000
#define DDRSS_PHY_242_DATA 0x00000000
#define DDRSS_PHY_243_DATA 0x00000000
#define DDRSS_PHY_244_DATA 0x00000000
#define DDRSS_PHY_245_DATA 0x00000000
#define DDRSS_PHY_246_DATA 0x00000000
#define DDRSS_PHY_247_DATA 0x00000000
#define DDRSS_PHY_248_DATA 0x00000000
#define DDRSS_PHY_249_DATA 0x00000000
#define DDRSS_PHY_250_DATA 0x00000000
#define DDRSS_PHY_251_DATA 0x00000000
#define DDRSS_PHY_252_DATA 0x00000000
#define DDRSS_PHY_253_DATA 0x00000000
#define DDRSS_PHY_254_DATA 0x00000000
#define DDRSS_PHY_255_DATA 0x00000000
#define DDRSS_PHY_256_DATA 0x04C00000
#define DDRSS_PHY_257_DATA 0x00000000
#define DDRSS_PHY_258_DATA 0x00000200
#define DDRSS_PHY_259_DATA 0x00000000
#define DDRSS_PHY_260_DATA 0x00000000
#define DDRSS_PHY_261_DATA 0x00000000
#define DDRSS_PHY_262_DATA 0x00000000
#define DDRSS_PHY_263_DATA 0x00000000
#define DDRSS_PHY_264_DATA 0x00000001
#define DDRSS_PHY_265_DATA 0x00000000
#define DDRSS_PHY_266_DATA 0x00000000
#define DDRSS_PHY_267_DATA 0x010101FF
#define DDRSS_PHY_268_DATA 0x00010000
#define DDRSS_PHY_269_DATA 0x00C00004
#define DDRSS_PHY_270_DATA 0x00CC0008
#define DDRSS_PHY_271_DATA 0x00660201
#define DDRSS_PHY_272_DATA 0x00000000
#define DDRSS_PHY_273_DATA 0x00000000
#define DDRSS_PHY_274_DATA 0x00000000
#define DDRSS_PHY_275_DATA 0x0000AAAA
#define DDRSS_PHY_276_DATA 0x00005555
#define DDRSS_PHY_277_DATA 0x0000B5B5
#define DDRSS_PHY_278_DATA 0x00004A4A
#define DDRSS_PHY_279_DATA 0x00005656
#define DDRSS_PHY_280_DATA 0x0000A9A9
#define DDRSS_PHY_281_DATA 0x0000B7B7
#define DDRSS_PHY_282_DATA 0x00004848
#define DDRSS_PHY_283_DATA 0x00000000
#define DDRSS_PHY_284_DATA 0x00000000
#define DDRSS_PHY_285_DATA 0x08000000
#define DDRSS_PHY_286_DATA 0x0F000008
#define DDRSS_PHY_287_DATA 0x00000F0F
#define DDRSS_PHY_288_DATA 0x00E4E400
#define DDRSS_PHY_289_DATA 0x00070820
#define DDRSS_PHY_290_DATA 0x000C0020
#define DDRSS_PHY_291_DATA 0x00062000
#define DDRSS_PHY_292_DATA 0x00000000
#define DDRSS_PHY_293_DATA 0x55555555
#define DDRSS_PHY_294_DATA 0xAAAAAAAA
#define DDRSS_PHY_295_DATA 0x55555555
#define DDRSS_PHY_296_DATA 0xAAAAAAAA
#define DDRSS_PHY_297_DATA 0x00005555
#define DDRSS_PHY_298_DATA 0x01000100
#define DDRSS_PHY_299_DATA 0x00800180
#define DDRSS_PHY_300_DATA 0x00000000
#define DDRSS_PHY_301_DATA 0x00000000
#define DDRSS_PHY_302_DATA 0x00000000
#define DDRSS_PHY_303_DATA 0x00000000
#define DDRSS_PHY_304_DATA 0x00000000
#define DDRSS_PHY_305_DATA 0x00000000
#define DDRSS_PHY_306_DATA 0x00000000
#define DDRSS_PHY_307_DATA 0x00000000
#define DDRSS_PHY_308_DATA 0x00000000
#define DDRSS_PHY_309_DATA 0x00000000
#define DDRSS_PHY_310_DATA 0x00000000
#define DDRSS_PHY_311_DATA 0x00000000
#define DDRSS_PHY_312_DATA 0x00000000
#define DDRSS_PHY_313_DATA 0x00000000
#define DDRSS_PHY_314_DATA 0x00000000
#define DDRSS_PHY_315_DATA 0x00000000
#define DDRSS_PHY_316_DATA 0x00000000
#define DDRSS_PHY_317_DATA 0x00000000
#define DDRSS_PHY_318_DATA 0x00000000
#define DDRSS_PHY_319_DATA 0x00000000
#define DDRSS_PHY_320_DATA 0x00000000
#define DDRSS_PHY_321_DATA 0x00000004
#define DDRSS_PHY_322_DATA 0x00000000
#define DDRSS_PHY_323_DATA 0x00000000
#define DDRSS_PHY_324_DATA 0x00000000
#define DDRSS_PHY_325_DATA 0x00000000
#define DDRSS_PHY_326_DATA 0x00000000
#define DDRSS_PHY_327_DATA 0x00000000
#define DDRSS_PHY_328_DATA 0x041F07FF
#define DDRSS_PHY_329_DATA 0x00000000
#define DDRSS_PHY_330_DATA 0x01CCB001
#define DDRSS_PHY_331_DATA 0x2000CCB0
#define DDRSS_PHY_332_DATA 0x20000140
#define DDRSS_PHY_333_DATA 0x07FF0200
#define DDRSS_PHY_334_DATA 0x0000DD01
#define DDRSS_PHY_335_DATA 0x10100303
#define DDRSS_PHY_336_DATA 0x10101010
#define DDRSS_PHY_337_DATA 0x10101010
#define DDRSS_PHY_338_DATA 0x00021010
#define DDRSS_PHY_339_DATA 0x00100010
#define DDRSS_PHY_340_DATA 0x00100010
#define DDRSS_PHY_341_DATA 0x00100010
#define DDRSS_PHY_342_DATA 0x00100010
#define DDRSS_PHY_343_DATA 0x02020010
#define DDRSS_PHY_344_DATA 0x51515041
#define DDRSS_PHY_345_DATA 0x31804000
#define DDRSS_PHY_346_DATA 0x04BF0340
#define DDRSS_PHY_347_DATA 0x01008080
#define DDRSS_PHY_348_DATA 0x04050001
#define DDRSS_PHY_349_DATA 0x00000504
#define DDRSS_PHY_350_DATA 0x42100010
#define DDRSS_PHY_351_DATA 0x010C053E
#define DDRSS_PHY_352_DATA 0x000F0C14
#define DDRSS_PHY_353_DATA 0x01000140
#define DDRSS_PHY_354_DATA 0x007A0120
#define DDRSS_PHY_355_DATA 0x00000C00
#define DDRSS_PHY_356_DATA 0x000001CC
#define DDRSS_PHY_357_DATA 0x20100200
#define DDRSS_PHY_358_DATA 0x00000005
#define DDRSS_PHY_359_DATA 0x76543210
#define DDRSS_PHY_360_DATA 0x00000008
#define DDRSS_PHY_361_DATA 0x02800280
#define DDRSS_PHY_362_DATA 0x02800280
#define DDRSS_PHY_363_DATA 0x02800280
#define DDRSS_PHY_364_DATA 0x02800280
#define DDRSS_PHY_365_DATA 0x00000280
#define DDRSS_PHY_366_DATA 0x00008000
#define DDRSS_PHY_367_DATA 0x00800080
#define DDRSS_PHY_368_DATA 0x00800080
#define DDRSS_PHY_369_DATA 0x00800080
#define DDRSS_PHY_370_DATA 0x00800080
#define DDRSS_PHY_371_DATA 0x00800080
#define DDRSS_PHY_372_DATA 0x00800080
#define DDRSS_PHY_373_DATA 0x00800080
#define DDRSS_PHY_374_DATA 0x00800080
#define DDRSS_PHY_375_DATA 0x01000080
#define DDRSS_PHY_376_DATA 0x01A00000
#define DDRSS_PHY_377_DATA 0x00000000
#define DDRSS_PHY_378_DATA 0x00000000
#define DDRSS_PHY_379_DATA 0x00080200
#define DDRSS_PHY_380_DATA 0x00000000
#define DDRSS_PHY_381_DATA 0x00000000
#define DDRSS_PHY_382_DATA 0x00000000
#define DDRSS_PHY_383_DATA 0x00000000
#define DDRSS_PHY_384_DATA 0x00000000
#define DDRSS_PHY_385_DATA 0x00000000
#define DDRSS_PHY_386_DATA 0x00000000
#define DDRSS_PHY_387_DATA 0x00000000
#define DDRSS_PHY_388_DATA 0x00000000
#define DDRSS_PHY_389_DATA 0x00000000
#define DDRSS_PHY_390_DATA 0x00000000
#define DDRSS_PHY_391_DATA 0x00000000
#define DDRSS_PHY_392_DATA 0x00000000
#define DDRSS_PHY_393_DATA 0x00000000
#define DDRSS_PHY_394_DATA 0x00000000
#define DDRSS_PHY_395_DATA 0x00000000
#define DDRSS_PHY_396_DATA 0x00000000
#define DDRSS_PHY_397_DATA 0x00000000
#define DDRSS_PHY_398_DATA 0x00000000
#define DDRSS_PHY_399_DATA 0x00000000
#define DDRSS_PHY_400_DATA 0x00000000
#define DDRSS_PHY_401_DATA 0x00000000
#define DDRSS_PHY_402_DATA 0x00000000
#define DDRSS_PHY_403_DATA 0x00000000
#define DDRSS_PHY_404_DATA 0x00000000
#define DDRSS_PHY_405_DATA 0x00000000
#define DDRSS_PHY_406_DATA 0x00000000
#define DDRSS_PHY_407_DATA 0x00000000
#define DDRSS_PHY_408_DATA 0x00000000
#define DDRSS_PHY_409_DATA 0x00000000
#define DDRSS_PHY_410_DATA 0x00000000
#define DDRSS_PHY_411_DATA 0x00000000
#define DDRSS_PHY_412_DATA 0x00000000
#define DDRSS_PHY_413_DATA 0x00000000
#define DDRSS_PHY_414_DATA 0x00000000
#define DDRSS_PHY_415_DATA 0x00000000
#define DDRSS_PHY_416_DATA 0x00000000
#define DDRSS_PHY_417_DATA 0x00000000
#define DDRSS_PHY_418_DATA 0x00000000
#define DDRSS_PHY_419_DATA 0x00000000
#define DDRSS_PHY_420_DATA 0x00000000
#define DDRSS_PHY_421_DATA 0x00000000
#define DDRSS_PHY_422_DATA 0x00000000
#define DDRSS_PHY_423_DATA 0x00000000
#define DDRSS_PHY_424_DATA 0x00000000
#define DDRSS_PHY_425_DATA 0x00000000
#define DDRSS_PHY_426_DATA 0x00000000
#define DDRSS_PHY_427_DATA 0x00000000
#define DDRSS_PHY_428_DATA 0x00000000
#define DDRSS_PHY_429_DATA 0x00000000
#define DDRSS_PHY_430_DATA 0x00000000
#define DDRSS_PHY_431_DATA 0x00000000
#define DDRSS_PHY_432_DATA 0x00000000
#define DDRSS_PHY_433_DATA 0x00000000
#define DDRSS_PHY_434_DATA 0x00000000
#define DDRSS_PHY_435_DATA 0x00000000
#define DDRSS_PHY_436_DATA 0x00000000
#define DDRSS_PHY_437_DATA 0x00000000
#define DDRSS_PHY_438_DATA 0x00000000
#define DDRSS_PHY_439_DATA 0x00000000
#define DDRSS_PHY_440_DATA 0x00000000
#define DDRSS_PHY_441_DATA 0x00000000
#define DDRSS_PHY_442_DATA 0x00000000
#define DDRSS_PHY_443_DATA 0x00000000
#define DDRSS_PHY_444_DATA 0x00000000
#define DDRSS_PHY_445_DATA 0x00000000
#define DDRSS_PHY_446_DATA 0x00000000
#define DDRSS_PHY_447_DATA 0x00000000
#define DDRSS_PHY_448_DATA 0x00000000
#define DDRSS_PHY_449_DATA 0x00000000
#define DDRSS_PHY_450_DATA 0x00000000
#define DDRSS_PHY_451_DATA 0x00000000
#define DDRSS_PHY_452_DATA 0x00000000
#define DDRSS_PHY_453_DATA 0x00000000
#define DDRSS_PHY_454_DATA 0x00000000
#define DDRSS_PHY_455_DATA 0x00000000
#define DDRSS_PHY_456_DATA 0x00000000
#define DDRSS_PHY_457_DATA 0x00000000
#define DDRSS_PHY_458_DATA 0x00000000
#define DDRSS_PHY_459_DATA 0x00000000
#define DDRSS_PHY_460_DATA 0x00000000
#define DDRSS_PHY_461_DATA 0x00000000
#define DDRSS_PHY_462_DATA 0x00000000
#define DDRSS_PHY_463_DATA 0x00000000
#define DDRSS_PHY_464_DATA 0x00000000
#define DDRSS_PHY_465_DATA 0x00000000
#define DDRSS_PHY_466_DATA 0x00000000
#define DDRSS_PHY_467_DATA 0x00000000
#define DDRSS_PHY_468_DATA 0x00000000
#define DDRSS_PHY_469_DATA 0x00000000
#define DDRSS_PHY_470_DATA 0x00000000
#define DDRSS_PHY_471_DATA 0x00000000
#define DDRSS_PHY_472_DATA 0x00000000
#define DDRSS_PHY_473_DATA 0x00000000
#define DDRSS_PHY_474_DATA 0x00000000
#define DDRSS_PHY_475_DATA 0x00000000
#define DDRSS_PHY_476_DATA 0x00000000
#define DDRSS_PHY_477_DATA 0x00000000
#define DDRSS_PHY_478_DATA 0x00000000
#define DDRSS_PHY_479_DATA 0x00000000
#define DDRSS_PHY_480_DATA 0x00000000
#define DDRSS_PHY_481_DATA 0x00000000
#define DDRSS_PHY_482_DATA 0x00000000
#define DDRSS_PHY_483_DATA 0x00000000
#define DDRSS_PHY_484_DATA 0x00000000
#define DDRSS_PHY_485_DATA 0x00000000
#define DDRSS_PHY_486_DATA 0x00000000
#define DDRSS_PHY_487_DATA 0x00000000
#define DDRSS_PHY_488_DATA 0x00000000
#define DDRSS_PHY_489_DATA 0x00000000
#define DDRSS_PHY_490_DATA 0x00000000
#define DDRSS_PHY_491_DATA 0x00000000
#define DDRSS_PHY_492_DATA 0x00000000
#define DDRSS_PHY_493_DATA 0x00000000
#define DDRSS_PHY_494_DATA 0x00000000
#define DDRSS_PHY_495_DATA 0x00000000
#define DDRSS_PHY_496_DATA 0x00000000
#define DDRSS_PHY_497_DATA 0x00000000
#define DDRSS_PHY_498_DATA 0x00000000
#define DDRSS_PHY_499_DATA 0x00000000
#define DDRSS_PHY_500_DATA 0x00000000
#define DDRSS_PHY_501_DATA 0x00000000
#define DDRSS_PHY_502_DATA 0x00000000
#define DDRSS_PHY_503_DATA 0x00000000
#define DDRSS_PHY_504_DATA 0x00000000
#define DDRSS_PHY_505_DATA 0x00000000
#define DDRSS_PHY_506_DATA 0x00000000
#define DDRSS_PHY_507_DATA 0x00000000
#define DDRSS_PHY_508_DATA 0x00000000
#define DDRSS_PHY_509_DATA 0x00000000
#define DDRSS_PHY_510_DATA 0x00000000
#define DDRSS_PHY_511_DATA 0x00000000
#define DDRSS_PHY_512_DATA 0x00000100
#define DDRSS_PHY_513_DATA 0x00000000
#define DDRSS_PHY_514_DATA 0x00000000
#define DDRSS_PHY_515_DATA 0x00000000
#define DDRSS_PHY_516_DATA 0x00000000
#define DDRSS_PHY_517_DATA 0x00000100
#define DDRSS_PHY_518_DATA 0x00000000
#define DDRSS_PHY_519_DATA 0x00000000
#define DDRSS_PHY_520_DATA 0x00000000
#define DDRSS_PHY_521_DATA 0x00000000
#define DDRSS_PHY_522_DATA 0x00000000
#define DDRSS_PHY_523_DATA 0x00000000
#define DDRSS_PHY_524_DATA 0x00000000
#define DDRSS_PHY_525_DATA 0x00DCBA98
#define DDRSS_PHY_526_DATA 0x00000000
#define DDRSS_PHY_527_DATA 0x00000000
#define DDRSS_PHY_528_DATA 0x00000000
#define DDRSS_PHY_529_DATA 0x00000000
#define DDRSS_PHY_530_DATA 0x00000000
#define DDRSS_PHY_531_DATA 0x00000000
#define DDRSS_PHY_532_DATA 0x00000000
#define DDRSS_PHY_533_DATA 0x00000000
#define DDRSS_PHY_534_DATA 0x00000000
#define DDRSS_PHY_535_DATA 0x00000000
#define DDRSS_PHY_536_DATA 0x00000000
#define DDRSS_PHY_537_DATA 0x00000000
#define DDRSS_PHY_538_DATA 0x00000000
#define DDRSS_PHY_539_DATA 0x00000000
#define DDRSS_PHY_540_DATA 0x0A418820
#define DDRSS_PHY_541_DATA 0x103F0000
#define DDRSS_PHY_542_DATA 0x000F0100
#define DDRSS_PHY_543_DATA 0x0000000F
#define DDRSS_PHY_544_DATA 0x020002CC
#define DDRSS_PHY_545_DATA 0x00030000
#define DDRSS_PHY_546_DATA 0x00000300
#define DDRSS_PHY_547_DATA 0x00000300
#define DDRSS_PHY_548_DATA 0x00000300
#define DDRSS_PHY_549_DATA 0x00000300
#define DDRSS_PHY_550_DATA 0x00000300
#define DDRSS_PHY_551_DATA 0x42080010
#define DDRSS_PHY_552_DATA 0x0000003E
#define DDRSS_PHY_553_DATA 0x00000000
#define DDRSS_PHY_554_DATA 0x00000000
#define DDRSS_PHY_555_DATA 0x00000000
#define DDRSS_PHY_556_DATA 0x00000000
#define DDRSS_PHY_557_DATA 0x00000000
#define DDRSS_PHY_558_DATA 0x00000000
#define DDRSS_PHY_559_DATA 0x00000000
#define DDRSS_PHY_560_DATA 0x00000000
#define DDRSS_PHY_561_DATA 0x00000000
#define DDRSS_PHY_562_DATA 0x00000000
#define DDRSS_PHY_563_DATA 0x00000000
#define DDRSS_PHY_564_DATA 0x00000000
#define DDRSS_PHY_565_DATA 0x00000000
#define DDRSS_PHY_566_DATA 0x00000000
#define DDRSS_PHY_567_DATA 0x00000000
#define DDRSS_PHY_568_DATA 0x00000000
#define DDRSS_PHY_569_DATA 0x00000000
#define DDRSS_PHY_570_DATA 0x00000000
#define DDRSS_PHY_571_DATA 0x00000000
#define DDRSS_PHY_572_DATA 0x00000000
#define DDRSS_PHY_573_DATA 0x00000000
#define DDRSS_PHY_574_DATA 0x00000000
#define DDRSS_PHY_575_DATA 0x00000000
#define DDRSS_PHY_576_DATA 0x00000000
#define DDRSS_PHY_577_DATA 0x00000000
#define DDRSS_PHY_578_DATA 0x00000000
#define DDRSS_PHY_579_DATA 0x00000000
#define DDRSS_PHY_580_DATA 0x00000000
#define DDRSS_PHY_581_DATA 0x00000000
#define DDRSS_PHY_582_DATA 0x00000000
#define DDRSS_PHY_583_DATA 0x00000000
#define DDRSS_PHY_584_DATA 0x00000000
#define DDRSS_PHY_585_DATA 0x00000000
#define DDRSS_PHY_586_DATA 0x00000000
#define DDRSS_PHY_587_DATA 0x00000000
#define DDRSS_PHY_588_DATA 0x00000000
#define DDRSS_PHY_589_DATA 0x00000000
#define DDRSS_PHY_590_DATA 0x00000000
#define DDRSS_PHY_591_DATA 0x00000000
#define DDRSS_PHY_592_DATA 0x00000000
#define DDRSS_PHY_593_DATA 0x00000000
#define DDRSS_PHY_594_DATA 0x00000000
#define DDRSS_PHY_595_DATA 0x00000000
#define DDRSS_PHY_596_DATA 0x00000000
#define DDRSS_PHY_597_DATA 0x00000000
#define DDRSS_PHY_598_DATA 0x00000000
#define DDRSS_PHY_599_DATA 0x00000000
#define DDRSS_PHY_600_DATA 0x00000000
#define DDRSS_PHY_601_DATA 0x00000000
#define DDRSS_PHY_602_DATA 0x00000000
#define DDRSS_PHY_603_DATA 0x00000000
#define DDRSS_PHY_604_DATA 0x00000000
#define DDRSS_PHY_605_DATA 0x00000000
#define DDRSS_PHY_606_DATA 0x00000000
#define DDRSS_PHY_607_DATA 0x00000000
#define DDRSS_PHY_608_DATA 0x00000000
#define DDRSS_PHY_609_DATA 0x00000000
#define DDRSS_PHY_610_DATA 0x00000000
#define DDRSS_PHY_611_DATA 0x00000000
#define DDRSS_PHY_612_DATA 0x00000000
#define DDRSS_PHY_613_DATA 0x00000000
#define DDRSS_PHY_614_DATA 0x00000000
#define DDRSS_PHY_615_DATA 0x00000000
#define DDRSS_PHY_616_DATA 0x00000000
#define DDRSS_PHY_617_DATA 0x00000000
#define DDRSS_PHY_618_DATA 0x00000000
#define DDRSS_PHY_619_DATA 0x00000000
#define DDRSS_PHY_620_DATA 0x00000000
#define DDRSS_PHY_621_DATA 0x00000000
#define DDRSS_PHY_622_DATA 0x00000000
#define DDRSS_PHY_623_DATA 0x00000000
#define DDRSS_PHY_624_DATA 0x00000000
#define DDRSS_PHY_625_DATA 0x00000000
#define DDRSS_PHY_626_DATA 0x00000000
#define DDRSS_PHY_627_DATA 0x00000000
#define DDRSS_PHY_628_DATA 0x00000000
#define DDRSS_PHY_629_DATA 0x00000000
#define DDRSS_PHY_630_DATA 0x00000000
#define DDRSS_PHY_631_DATA 0x00000000
#define DDRSS_PHY_632_DATA 0x00000000
#define DDRSS_PHY_633_DATA 0x00000000
#define DDRSS_PHY_634_DATA 0x00000000
#define DDRSS_PHY_635_DATA 0x00000000
#define DDRSS_PHY_636_DATA 0x00000000
#define DDRSS_PHY_637_DATA 0x00000000
#define DDRSS_PHY_638_DATA 0x00000000
#define DDRSS_PHY_639_DATA 0x00000000
#define DDRSS_PHY_640_DATA 0x00000000
#define DDRSS_PHY_641_DATA 0x00000000
#define DDRSS_PHY_642_DATA 0x00000000
#define DDRSS_PHY_643_DATA 0x00000000
#define DDRSS_PHY_644_DATA 0x00000000
#define DDRSS_PHY_645_DATA 0x00000000
#define DDRSS_PHY_646_DATA 0x00000000
#define DDRSS_PHY_647_DATA 0x00000000
#define DDRSS_PHY_648_DATA 0x00000000
#define DDRSS_PHY_649_DATA 0x00000000
#define DDRSS_PHY_650_DATA 0x00000000
#define DDRSS_PHY_651_DATA 0x00000000
#define DDRSS_PHY_652_DATA 0x00000000
#define DDRSS_PHY_653_DATA 0x00000000
#define DDRSS_PHY_654_DATA 0x00000000
#define DDRSS_PHY_655_DATA 0x00000000
#define DDRSS_PHY_656_DATA 0x00000000
#define DDRSS_PHY_657_DATA 0x00000000
#define DDRSS_PHY_658_DATA 0x00000000
#define DDRSS_PHY_659_DATA 0x00000000
#define DDRSS_PHY_660_DATA 0x00000000
#define DDRSS_PHY_661_DATA 0x00000000
#define DDRSS_PHY_662_DATA 0x00000000
#define DDRSS_PHY_663_DATA 0x00000000
#define DDRSS_PHY_664_DATA 0x00000000
#define DDRSS_PHY_665_DATA 0x00000000
#define DDRSS_PHY_666_DATA 0x00000000
#define DDRSS_PHY_667_DATA 0x00000000
#define DDRSS_PHY_668_DATA 0x00000000
#define DDRSS_PHY_669_DATA 0x00000000
#define DDRSS_PHY_670_DATA 0x00000000
#define DDRSS_PHY_671_DATA 0x00000000
#define DDRSS_PHY_672_DATA 0x00000000
#define DDRSS_PHY_673_DATA 0x00000000
#define DDRSS_PHY_674_DATA 0x00000000
#define DDRSS_PHY_675_DATA 0x00000000
#define DDRSS_PHY_676_DATA 0x00000000
#define DDRSS_PHY_677_DATA 0x00000000
#define DDRSS_PHY_678_DATA 0x00000000
#define DDRSS_PHY_679_DATA 0x00000000
#define DDRSS_PHY_680_DATA 0x00000000
#define DDRSS_PHY_681_DATA 0x00000000
#define DDRSS_PHY_682_DATA 0x00000000
#define DDRSS_PHY_683_DATA 0x00000000
#define DDRSS_PHY_684_DATA 0x00000000
#define DDRSS_PHY_685_DATA 0x00000000
#define DDRSS_PHY_686_DATA 0x00000000
#define DDRSS_PHY_687_DATA 0x00000000
#define DDRSS_PHY_688_DATA 0x00000000
#define DDRSS_PHY_689_DATA 0x00000000
#define DDRSS_PHY_690_DATA 0x00000000
#define DDRSS_PHY_691_DATA 0x00000000
#define DDRSS_PHY_692_DATA 0x00000000
#define DDRSS_PHY_693_DATA 0x00000000
#define DDRSS_PHY_694_DATA 0x00000000
#define DDRSS_PHY_695_DATA 0x00000000
#define DDRSS_PHY_696_DATA 0x00000000
#define DDRSS_PHY_697_DATA 0x00000000
#define DDRSS_PHY_698_DATA 0x00000000
#define DDRSS_PHY_699_DATA 0x00000000
#define DDRSS_PHY_700_DATA 0x00000000
#define DDRSS_PHY_701_DATA 0x00000000
#define DDRSS_PHY_702_DATA 0x00000000
#define DDRSS_PHY_703_DATA 0x00000000
#define DDRSS_PHY_704_DATA 0x00000000
#define DDRSS_PHY_705_DATA 0x00000000
#define DDRSS_PHY_706_DATA 0x00000000
#define DDRSS_PHY_707_DATA 0x00000000
#define DDRSS_PHY_708_DATA 0x00000000
#define DDRSS_PHY_709_DATA 0x00000000
#define DDRSS_PHY_710_DATA 0x00000000
#define DDRSS_PHY_711_DATA 0x00000000
#define DDRSS_PHY_712_DATA 0x00000000
#define DDRSS_PHY_713_DATA 0x00000000
#define DDRSS_PHY_714_DATA 0x00000000
#define DDRSS_PHY_715_DATA 0x00000000
#define DDRSS_PHY_716_DATA 0x00000000
#define DDRSS_PHY_717_DATA 0x00000000
#define DDRSS_PHY_718_DATA 0x00000000
#define DDRSS_PHY_719_DATA 0x00000000
#define DDRSS_PHY_720_DATA 0x00000000
#define DDRSS_PHY_721_DATA 0x00000000
#define DDRSS_PHY_722_DATA 0x00000000
#define DDRSS_PHY_723_DATA 0x00000000
#define DDRSS_PHY_724_DATA 0x00000000
#define DDRSS_PHY_725_DATA 0x00000000
#define DDRSS_PHY_726_DATA 0x00000000
#define DDRSS_PHY_727_DATA 0x00000000
#define DDRSS_PHY_728_DATA 0x00000000
#define DDRSS_PHY_729_DATA 0x00000000
#define DDRSS_PHY_730_DATA 0x00000000
#define DDRSS_PHY_731_DATA 0x00000000
#define DDRSS_PHY_732_DATA 0x00000000
#define DDRSS_PHY_733_DATA 0x00000000
#define DDRSS_PHY_734_DATA 0x00000000
#define DDRSS_PHY_735_DATA 0x00000000
#define DDRSS_PHY_736_DATA 0x00000000
#define DDRSS_PHY_737_DATA 0x00000000
#define DDRSS_PHY_738_DATA 0x00000000
#define DDRSS_PHY_739_DATA 0x00000000
#define DDRSS_PHY_740_DATA 0x00000000
#define DDRSS_PHY_741_DATA 0x00000000
#define DDRSS_PHY_742_DATA 0x00000000
#define DDRSS_PHY_743_DATA 0x00000000
#define DDRSS_PHY_744_DATA 0x00000000
#define DDRSS_PHY_745_DATA 0x00000000
#define DDRSS_PHY_746_DATA 0x00000000
#define DDRSS_PHY_747_DATA 0x00000000
#define DDRSS_PHY_748_DATA 0x00000000
#define DDRSS_PHY_749_DATA 0x00000000
#define DDRSS_PHY_750_DATA 0x00000000
#define DDRSS_PHY_751_DATA 0x00000000
#define DDRSS_PHY_752_DATA 0x00000000
#define DDRSS_PHY_753_DATA 0x00000000
#define DDRSS_PHY_754_DATA 0x00000000
#define DDRSS_PHY_755_DATA 0x00000000
#define DDRSS_PHY_756_DATA 0x00000000
#define DDRSS_PHY_757_DATA 0x00000000
#define DDRSS_PHY_758_DATA 0x00000000
#define DDRSS_PHY_759_DATA 0x00000000
#define DDRSS_PHY_760_DATA 0x00000000
#define DDRSS_PHY_761_DATA 0x00000000
#define DDRSS_PHY_762_DATA 0x00000000
#define DDRSS_PHY_763_DATA 0x00000000
#define DDRSS_PHY_764_DATA 0x00000000
#define DDRSS_PHY_765_DATA 0x00000000
#define DDRSS_PHY_766_DATA 0x00000000
#define DDRSS_PHY_767_DATA 0x00000000
#define DDRSS_PHY_768_DATA 0x00000100
#define DDRSS_PHY_769_DATA 0x00000000
#define DDRSS_PHY_770_DATA 0x00000000
#define DDRSS_PHY_771_DATA 0x00000000
#define DDRSS_PHY_772_DATA 0x00000000
#define DDRSS_PHY_773_DATA 0x00000100
#define DDRSS_PHY_774_DATA 0x00000000
#define DDRSS_PHY_775_DATA 0x00000000
#define DDRSS_PHY_776_DATA 0x00000000
#define DDRSS_PHY_777_DATA 0x00000000
#define DDRSS_PHY_778_DATA 0x00000000
#define DDRSS_PHY_779_DATA 0x00000000
#define DDRSS_PHY_780_DATA 0x00000000
#define DDRSS_PHY_781_DATA 0x00DCBA98
#define DDRSS_PHY_782_DATA 0x00000000
#define DDRSS_PHY_783_DATA 0x00000000
#define DDRSS_PHY_784_DATA 0x00000000
#define DDRSS_PHY_785_DATA 0x00000000
#define DDRSS_PHY_786_DATA 0x00000000
#define DDRSS_PHY_787_DATA 0x00000000
#define DDRSS_PHY_788_DATA 0x00000000
#define DDRSS_PHY_789_DATA 0x00000000
#define DDRSS_PHY_790_DATA 0x00000000
#define DDRSS_PHY_791_DATA 0x00000000
#define DDRSS_PHY_792_DATA 0x00000000
#define DDRSS_PHY_793_DATA 0x00000000
#define DDRSS_PHY_794_DATA 0x00000000
#define DDRSS_PHY_795_DATA 0x00000000
#define DDRSS_PHY_796_DATA 0x16A4A0E6
#define DDRSS_PHY_797_DATA 0x103F0000
#define DDRSS_PHY_798_DATA 0x000F0000
#define DDRSS_PHY_799_DATA 0x0000000F
#define DDRSS_PHY_800_DATA 0x020002CC
#define DDRSS_PHY_801_DATA 0x00030000
#define DDRSS_PHY_802_DATA 0x00000300
#define DDRSS_PHY_803_DATA 0x00000300
#define DDRSS_PHY_804_DATA 0x00000300
#define DDRSS_PHY_805_DATA 0x00000300
#define DDRSS_PHY_806_DATA 0x00000300
#define DDRSS_PHY_807_DATA 0x42080010
#define DDRSS_PHY_808_DATA 0x0000003E
#define DDRSS_PHY_809_DATA 0x00000000
#define DDRSS_PHY_810_DATA 0x00000000
#define DDRSS_PHY_811_DATA 0x00000000
#define DDRSS_PHY_812_DATA 0x00000000
#define DDRSS_PHY_813_DATA 0x00000000
#define DDRSS_PHY_814_DATA 0x00000000
#define DDRSS_PHY_815_DATA 0x00000000
#define DDRSS_PHY_816_DATA 0x00000000
#define DDRSS_PHY_817_DATA 0x00000000
#define DDRSS_PHY_818_DATA 0x00000000
#define DDRSS_PHY_819_DATA 0x00000000
#define DDRSS_PHY_820_DATA 0x00000000
#define DDRSS_PHY_821_DATA 0x00000000
#define DDRSS_PHY_822_DATA 0x00000000
#define DDRSS_PHY_823_DATA 0x00000000
#define DDRSS_PHY_824_DATA 0x00000000
#define DDRSS_PHY_825_DATA 0x00000000
#define DDRSS_PHY_826_DATA 0x00000000
#define DDRSS_PHY_827_DATA 0x00000000
#define DDRSS_PHY_828_DATA 0x00000000
#define DDRSS_PHY_829_DATA 0x00000000
#define DDRSS_PHY_830_DATA 0x00000000
#define DDRSS_PHY_831_DATA 0x00000000
#define DDRSS_PHY_832_DATA 0x00000000
#define DDRSS_PHY_833_DATA 0x00000000
#define DDRSS_PHY_834_DATA 0x00000000
#define DDRSS_PHY_835_DATA 0x00000000
#define DDRSS_PHY_836_DATA 0x00000000
#define DDRSS_PHY_837_DATA 0x00000000
#define DDRSS_PHY_838_DATA 0x00000000
#define DDRSS_PHY_839_DATA 0x00000000
#define DDRSS_PHY_840_DATA 0x00000000
#define DDRSS_PHY_841_DATA 0x00000000
#define DDRSS_PHY_842_DATA 0x00000000
#define DDRSS_PHY_843_DATA 0x00000000
#define DDRSS_PHY_844_DATA 0x00000000
#define DDRSS_PHY_845_DATA 0x00000000
#define DDRSS_PHY_846_DATA 0x00000000
#define DDRSS_PHY_847_DATA 0x00000000
#define DDRSS_PHY_848_DATA 0x00000000
#define DDRSS_PHY_849_DATA 0x00000000
#define DDRSS_PHY_850_DATA 0x00000000
#define DDRSS_PHY_851_DATA 0x00000000
#define DDRSS_PHY_852_DATA 0x00000000
#define DDRSS_PHY_853_DATA 0x00000000
#define DDRSS_PHY_854_DATA 0x00000000
#define DDRSS_PHY_855_DATA 0x00000000
#define DDRSS_PHY_856_DATA 0x00000000
#define DDRSS_PHY_857_DATA 0x00000000
#define DDRSS_PHY_858_DATA 0x00000000
#define DDRSS_PHY_859_DATA 0x00000000
#define DDRSS_PHY_860_DATA 0x00000000
#define DDRSS_PHY_861_DATA 0x00000000
#define DDRSS_PHY_862_DATA 0x00000000
#define DDRSS_PHY_863_DATA 0x00000000
#define DDRSS_PHY_864_DATA 0x00000000
#define DDRSS_PHY_865_DATA 0x00000000
#define DDRSS_PHY_866_DATA 0x00000000
#define DDRSS_PHY_867_DATA 0x00000000
#define DDRSS_PHY_868_DATA 0x00000000
#define DDRSS_PHY_869_DATA 0x00000000
#define DDRSS_PHY_870_DATA 0x00000000
#define DDRSS_PHY_871_DATA 0x00000000
#define DDRSS_PHY_872_DATA 0x00000000
#define DDRSS_PHY_873_DATA 0x00000000
#define DDRSS_PHY_874_DATA 0x00000000
#define DDRSS_PHY_875_DATA 0x00000000
#define DDRSS_PHY_876_DATA 0x00000000
#define DDRSS_PHY_877_DATA 0x00000000
#define DDRSS_PHY_878_DATA 0x00000000
#define DDRSS_PHY_879_DATA 0x00000000
#define DDRSS_PHY_880_DATA 0x00000000
#define DDRSS_PHY_881_DATA 0x00000000
#define DDRSS_PHY_882_DATA 0x00000000
#define DDRSS_PHY_883_DATA 0x00000000
#define DDRSS_PHY_884_DATA 0x00000000
#define DDRSS_PHY_885_DATA 0x00000000
#define DDRSS_PHY_886_DATA 0x00000000
#define DDRSS_PHY_887_DATA 0x00000000
#define DDRSS_PHY_888_DATA 0x00000000
#define DDRSS_PHY_889_DATA 0x00000000
#define DDRSS_PHY_890_DATA 0x00000000
#define DDRSS_PHY_891_DATA 0x00000000
#define DDRSS_PHY_892_DATA 0x00000000
#define DDRSS_PHY_893_DATA 0x00000000
#define DDRSS_PHY_894_DATA 0x00000000
#define DDRSS_PHY_895_DATA 0x00000000
#define DDRSS_PHY_896_DATA 0x00000000
#define DDRSS_PHY_897_DATA 0x00000000
#define DDRSS_PHY_898_DATA 0x00000000
#define DDRSS_PHY_899_DATA 0x00000000
#define DDRSS_PHY_900_DATA 0x00000000
#define DDRSS_PHY_901_DATA 0x00000000
#define DDRSS_PHY_902_DATA 0x00000000
#define DDRSS_PHY_903_DATA 0x00000000
#define DDRSS_PHY_904_DATA 0x00000000
#define DDRSS_PHY_905_DATA 0x00000000
#define DDRSS_PHY_906_DATA 0x00000000
#define DDRSS_PHY_907_DATA 0x00000000
#define DDRSS_PHY_908_DATA 0x00000000
#define DDRSS_PHY_909_DATA 0x00000000
#define DDRSS_PHY_910_DATA 0x00000000
#define DDRSS_PHY_911_DATA 0x00000000
#define DDRSS_PHY_912_DATA 0x00000000
#define DDRSS_PHY_913_DATA 0x00000000
#define DDRSS_PHY_914_DATA 0x00000000
#define DDRSS_PHY_915_DATA 0x00000000
#define DDRSS_PHY_916_DATA 0x00000000
#define DDRSS_PHY_917_DATA 0x00000000
#define DDRSS_PHY_918_DATA 0x00000000
#define DDRSS_PHY_919_DATA 0x00000000
#define DDRSS_PHY_920_DATA 0x00000000
#define DDRSS_PHY_921_DATA 0x00000000
#define DDRSS_PHY_922_DATA 0x00000000
#define DDRSS_PHY_923_DATA 0x00000000
#define DDRSS_PHY_924_DATA 0x00000000
#define DDRSS_PHY_925_DATA 0x00000000
#define DDRSS_PHY_926_DATA 0x00000000
#define DDRSS_PHY_927_DATA 0x00000000
#define DDRSS_PHY_928_DATA 0x00000000
#define DDRSS_PHY_929_DATA 0x00000000
#define DDRSS_PHY_930_DATA 0x00000000
#define DDRSS_PHY_931_DATA 0x00000000
#define DDRSS_PHY_932_DATA 0x00000000
#define DDRSS_PHY_933_DATA 0x00000000
#define DDRSS_PHY_934_DATA 0x00000000
#define DDRSS_PHY_935_DATA 0x00000000
#define DDRSS_PHY_936_DATA 0x00000000
#define DDRSS_PHY_937_DATA 0x00000000
#define DDRSS_PHY_938_DATA 0x00000000
#define DDRSS_PHY_939_DATA 0x00000000
#define DDRSS_PHY_940_DATA 0x00000000
#define DDRSS_PHY_941_DATA 0x00000000
#define DDRSS_PHY_942_DATA 0x00000000
#define DDRSS_PHY_943_DATA 0x00000000
#define DDRSS_PHY_944_DATA 0x00000000
#define DDRSS_PHY_945_DATA 0x00000000
#define DDRSS_PHY_946_DATA 0x00000000
#define DDRSS_PHY_947_DATA 0x00000000
#define DDRSS_PHY_948_DATA 0x00000000
#define DDRSS_PHY_949_DATA 0x00000000
#define DDRSS_PHY_950_DATA 0x00000000
#define DDRSS_PHY_951_DATA 0x00000000
#define DDRSS_PHY_952_DATA 0x00000000
#define DDRSS_PHY_953_DATA 0x00000000
#define DDRSS_PHY_954_DATA 0x00000000
#define DDRSS_PHY_955_DATA 0x00000000
#define DDRSS_PHY_956_DATA 0x00000000
#define DDRSS_PHY_957_DATA 0x00000000
#define DDRSS_PHY_958_DATA 0x00000000
#define DDRSS_PHY_959_DATA 0x00000000
#define DDRSS_PHY_960_DATA 0x00000000
#define DDRSS_PHY_961_DATA 0x00000000
#define DDRSS_PHY_962_DATA 0x00000000
#define DDRSS_PHY_963_DATA 0x00000000
#define DDRSS_PHY_964_DATA 0x00000000
#define DDRSS_PHY_965_DATA 0x00000000
#define DDRSS_PHY_966_DATA 0x00000000
#define DDRSS_PHY_967_DATA 0x00000000
#define DDRSS_PHY_968_DATA 0x00000000
#define DDRSS_PHY_969_DATA 0x00000000
#define DDRSS_PHY_970_DATA 0x00000000
#define DDRSS_PHY_971_DATA 0x00000000
#define DDRSS_PHY_972_DATA 0x00000000
#define DDRSS_PHY_973_DATA 0x00000000
#define DDRSS_PHY_974_DATA 0x00000000
#define DDRSS_PHY_975_DATA 0x00000000
#define DDRSS_PHY_976_DATA 0x00000000
#define DDRSS_PHY_977_DATA 0x00000000
#define DDRSS_PHY_978_DATA 0x00000000
#define DDRSS_PHY_979_DATA 0x00000000
#define DDRSS_PHY_980_DATA 0x00000000
#define DDRSS_PHY_981_DATA 0x00000000
#define DDRSS_PHY_982_DATA 0x00000000
#define DDRSS_PHY_983_DATA 0x00000000
#define DDRSS_PHY_984_DATA 0x00000000
#define DDRSS_PHY_985_DATA 0x00000000
#define DDRSS_PHY_986_DATA 0x00000000
#define DDRSS_PHY_987_DATA 0x00000000
#define DDRSS_PHY_988_DATA 0x00000000
#define DDRSS_PHY_989_DATA 0x00000000
#define DDRSS_PHY_990_DATA 0x00000000
#define DDRSS_PHY_991_DATA 0x00000000
#define DDRSS_PHY_992_DATA 0x00000000
#define DDRSS_PHY_993_DATA 0x00000000
#define DDRSS_PHY_994_DATA 0x00000000
#define DDRSS_PHY_995_DATA 0x00000000
#define DDRSS_PHY_996_DATA 0x00000000
#define DDRSS_PHY_997_DATA 0x00000000
#define DDRSS_PHY_998_DATA 0x00000000
#define DDRSS_PHY_999_DATA 0x00000000
#define DDRSS_PHY_1000_DATA 0x00000000
#define DDRSS_PHY_1001_DATA 0x00000000
#define DDRSS_PHY_1002_DATA 0x00000000
#define DDRSS_PHY_1003_DATA 0x00000000
#define DDRSS_PHY_1004_DATA 0x00000000
#define DDRSS_PHY_1005_DATA 0x00000000
#define DDRSS_PHY_1006_DATA 0x00000000
#define DDRSS_PHY_1007_DATA 0x00000000
#define DDRSS_PHY_1008_DATA 0x00000000
#define DDRSS_PHY_1009_DATA 0x00000000
#define DDRSS_PHY_1010_DATA 0x00000000
#define DDRSS_PHY_1011_DATA 0x00000000
#define DDRSS_PHY_1012_DATA 0x00000000
#define DDRSS_PHY_1013_DATA 0x00000000
#define DDRSS_PHY_1014_DATA 0x00000000
#define DDRSS_PHY_1015_DATA 0x00000000
#define DDRSS_PHY_1016_DATA 0x00000000
#define DDRSS_PHY_1017_DATA 0x00000000
#define DDRSS_PHY_1018_DATA 0x00000000
#define DDRSS_PHY_1019_DATA 0x00000000
#define DDRSS_PHY_1020_DATA 0x00000000
#define DDRSS_PHY_1021_DATA 0x00000000
#define DDRSS_PHY_1022_DATA 0x00000000
#define DDRSS_PHY_1023_DATA 0x00000000
#define DDRSS_PHY_1024_DATA 0x00000100
#define DDRSS_PHY_1025_DATA 0x00000000
#define DDRSS_PHY_1026_DATA 0x00000000
#define DDRSS_PHY_1027_DATA 0x00000000
#define DDRSS_PHY_1028_DATA 0x00000000
#define DDRSS_PHY_1029_DATA 0x00000100
#define DDRSS_PHY_1030_DATA 0x00000000
#define DDRSS_PHY_1031_DATA 0x00000000
#define DDRSS_PHY_1032_DATA 0x00000000
#define DDRSS_PHY_1033_DATA 0x00000000
#define DDRSS_PHY_1034_DATA 0x00000000
#define DDRSS_PHY_1035_DATA 0x00000000
#define DDRSS_PHY_1036_DATA 0x00000000
#define DDRSS_PHY_1037_DATA 0x00DCBA98
#define DDRSS_PHY_1038_DATA 0x00000000
#define DDRSS_PHY_1039_DATA 0x00000000
#define DDRSS_PHY_1040_DATA 0x00000000
#define DDRSS_PHY_1041_DATA 0x00000000
#define DDRSS_PHY_1042_DATA 0x00000000
#define DDRSS_PHY_1043_DATA 0x00000000
#define DDRSS_PHY_1044_DATA 0x00000000
#define DDRSS_PHY_1045_DATA 0x00000000
#define DDRSS_PHY_1046_DATA 0x00000000
#define DDRSS_PHY_1047_DATA 0x00000000
#define DDRSS_PHY_1048_DATA 0x00000000
#define DDRSS_PHY_1049_DATA 0x00000000
#define DDRSS_PHY_1050_DATA 0x00000000
#define DDRSS_PHY_1051_DATA 0x00000000
#define DDRSS_PHY_1052_DATA 0x2307B9AC
#define DDRSS_PHY_1053_DATA 0x10030000
#define DDRSS_PHY_1054_DATA 0x000F0000
#define DDRSS_PHY_1055_DATA 0x0000000F
#define DDRSS_PHY_1056_DATA 0x020002CC
#define DDRSS_PHY_1057_DATA 0x00030000
#define DDRSS_PHY_1058_DATA 0x00000300
#define DDRSS_PHY_1059_DATA 0x00000300
#define DDRSS_PHY_1060_DATA 0x00000300
#define DDRSS_PHY_1061_DATA 0x00000300
#define DDRSS_PHY_1062_DATA 0x00000300
#define DDRSS_PHY_1063_DATA 0x42080010
#define DDRSS_PHY_1064_DATA 0x0000003E
#define DDRSS_PHY_1065_DATA 0x00000000
#define DDRSS_PHY_1066_DATA 0x00000000
#define DDRSS_PHY_1067_DATA 0x00000000
#define DDRSS_PHY_1068_DATA 0x00000000
#define DDRSS_PHY_1069_DATA 0x00000000
#define DDRSS_PHY_1070_DATA 0x00000000
#define DDRSS_PHY_1071_DATA 0x00000000
#define DDRSS_PHY_1072_DATA 0x00000000
#define DDRSS_PHY_1073_DATA 0x00000000
#define DDRSS_PHY_1074_DATA 0x00000000
#define DDRSS_PHY_1075_DATA 0x00000000
#define DDRSS_PHY_1076_DATA 0x00000000
#define DDRSS_PHY_1077_DATA 0x00000000
#define DDRSS_PHY_1078_DATA 0x00000000
#define DDRSS_PHY_1079_DATA 0x00000000
#define DDRSS_PHY_1080_DATA 0x00000000
#define DDRSS_PHY_1081_DATA 0x00000000
#define DDRSS_PHY_1082_DATA 0x00000000
#define DDRSS_PHY_1083_DATA 0x00000000
#define DDRSS_PHY_1084_DATA 0x00000000
#define DDRSS_PHY_1085_DATA 0x00000000
#define DDRSS_PHY_1086_DATA 0x00000000
#define DDRSS_PHY_1087_DATA 0x00000000
#define DDRSS_PHY_1088_DATA 0x00000000
#define DDRSS_PHY_1089_DATA 0x00000000
#define DDRSS_PHY_1090_DATA 0x00000000
#define DDRSS_PHY_1091_DATA 0x00000000
#define DDRSS_PHY_1092_DATA 0x00000000
#define DDRSS_PHY_1093_DATA 0x00000000
#define DDRSS_PHY_1094_DATA 0x00000000
#define DDRSS_PHY_1095_DATA 0x00000000
#define DDRSS_PHY_1096_DATA 0x00000000
#define DDRSS_PHY_1097_DATA 0x00000000
#define DDRSS_PHY_1098_DATA 0x00000000
#define DDRSS_PHY_1099_DATA 0x00000000
#define DDRSS_PHY_1100_DATA 0x00000000
#define DDRSS_PHY_1101_DATA 0x00000000
#define DDRSS_PHY_1102_DATA 0x00000000
#define DDRSS_PHY_1103_DATA 0x00000000
#define DDRSS_PHY_1104_DATA 0x00000000
#define DDRSS_PHY_1105_DATA 0x00000000
#define DDRSS_PHY_1106_DATA 0x00000000
#define DDRSS_PHY_1107_DATA 0x00000000
#define DDRSS_PHY_1108_DATA 0x00000000
#define DDRSS_PHY_1109_DATA 0x00000000
#define DDRSS_PHY_1110_DATA 0x00000000
#define DDRSS_PHY_1111_DATA 0x00000000
#define DDRSS_PHY_1112_DATA 0x00000000
#define DDRSS_PHY_1113_DATA 0x00000000
#define DDRSS_PHY_1114_DATA 0x00000000
#define DDRSS_PHY_1115_DATA 0x00000000
#define DDRSS_PHY_1116_DATA 0x00000000
#define DDRSS_PHY_1117_DATA 0x00000000
#define DDRSS_PHY_1118_DATA 0x00000000
#define DDRSS_PHY_1119_DATA 0x00000000
#define DDRSS_PHY_1120_DATA 0x00000000
#define DDRSS_PHY_1121_DATA 0x00000000
#define DDRSS_PHY_1122_DATA 0x00000000
#define DDRSS_PHY_1123_DATA 0x00000000
#define DDRSS_PHY_1124_DATA 0x00000000
#define DDRSS_PHY_1125_DATA 0x00000000
#define DDRSS_PHY_1126_DATA 0x00000000
#define DDRSS_PHY_1127_DATA 0x00000000
#define DDRSS_PHY_1128_DATA 0x00000000
#define DDRSS_PHY_1129_DATA 0x00000000
#define DDRSS_PHY_1130_DATA 0x00000000
#define DDRSS_PHY_1131_DATA 0x00000000
#define DDRSS_PHY_1132_DATA 0x00000000
#define DDRSS_PHY_1133_DATA 0x00000000
#define DDRSS_PHY_1134_DATA 0x00000000
#define DDRSS_PHY_1135_DATA 0x00000000
#define DDRSS_PHY_1136_DATA 0x00000000
#define DDRSS_PHY_1137_DATA 0x00000000
#define DDRSS_PHY_1138_DATA 0x00000000
#define DDRSS_PHY_1139_DATA 0x00000000
#define DDRSS_PHY_1140_DATA 0x00000000
#define DDRSS_PHY_1141_DATA 0x00000000
#define DDRSS_PHY_1142_DATA 0x00000000
#define DDRSS_PHY_1143_DATA 0x00000000
#define DDRSS_PHY_1144_DATA 0x00000000
#define DDRSS_PHY_1145_DATA 0x00000000
#define DDRSS_PHY_1146_DATA 0x00000000
#define DDRSS_PHY_1147_DATA 0x00000000
#define DDRSS_PHY_1148_DATA 0x00000000
#define DDRSS_PHY_1149_DATA 0x00000000
#define DDRSS_PHY_1150_DATA 0x00000000
#define DDRSS_PHY_1151_DATA 0x00000000
#define DDRSS_PHY_1152_DATA 0x00000000
#define DDRSS_PHY_1153_DATA 0x00000000
#define DDRSS_PHY_1154_DATA 0x00000000
#define DDRSS_PHY_1155_DATA 0x00000000
#define DDRSS_PHY_1156_DATA 0x00000000
#define DDRSS_PHY_1157_DATA 0x00000000
#define DDRSS_PHY_1158_DATA 0x00000000
#define DDRSS_PHY_1159_DATA 0x00000000
#define DDRSS_PHY_1160_DATA 0x00000000
#define DDRSS_PHY_1161_DATA 0x00000000
#define DDRSS_PHY_1162_DATA 0x00000000
#define DDRSS_PHY_1163_DATA 0x00000000
#define DDRSS_PHY_1164_DATA 0x00000000
#define DDRSS_PHY_1165_DATA 0x00000000
#define DDRSS_PHY_1166_DATA 0x00000000
#define DDRSS_PHY_1167_DATA 0x00000000
#define DDRSS_PHY_1168_DATA 0x00000000
#define DDRSS_PHY_1169_DATA 0x00000000
#define DDRSS_PHY_1170_DATA 0x00000000
#define DDRSS_PHY_1171_DATA 0x00000000
#define DDRSS_PHY_1172_DATA 0x00000000
#define DDRSS_PHY_1173_DATA 0x00000000
#define DDRSS_PHY_1174_DATA 0x00000000
#define DDRSS_PHY_1175_DATA 0x00000000
#define DDRSS_PHY_1176_DATA 0x00000000
#define DDRSS_PHY_1177_DATA 0x00000000
#define DDRSS_PHY_1178_DATA 0x00000000
#define DDRSS_PHY_1179_DATA 0x00000000
#define DDRSS_PHY_1180_DATA 0x00000000
#define DDRSS_PHY_1181_DATA 0x00000000
#define DDRSS_PHY_1182_DATA 0x00000000
#define DDRSS_PHY_1183_DATA 0x00000000
#define DDRSS_PHY_1184_DATA 0x00000000
#define DDRSS_PHY_1185_DATA 0x00000000
#define DDRSS_PHY_1186_DATA 0x00000000
#define DDRSS_PHY_1187_DATA 0x00000000
#define DDRSS_PHY_1188_DATA 0x00000000
#define DDRSS_PHY_1189_DATA 0x00000000
#define DDRSS_PHY_1190_DATA 0x00000000
#define DDRSS_PHY_1191_DATA 0x00000000
#define DDRSS_PHY_1192_DATA 0x00000000
#define DDRSS_PHY_1193_DATA 0x00000000
#define DDRSS_PHY_1194_DATA 0x00000000
#define DDRSS_PHY_1195_DATA 0x00000000
#define DDRSS_PHY_1196_DATA 0x00000000
#define DDRSS_PHY_1197_DATA 0x00000000
#define DDRSS_PHY_1198_DATA 0x00000000
#define DDRSS_PHY_1199_DATA 0x00000000
#define DDRSS_PHY_1200_DATA 0x00000000
#define DDRSS_PHY_1201_DATA 0x00000000
#define DDRSS_PHY_1202_DATA 0x00000000
#define DDRSS_PHY_1203_DATA 0x00000000
#define DDRSS_PHY_1204_DATA 0x00000000
#define DDRSS_PHY_1205_DATA 0x00000000
#define DDRSS_PHY_1206_DATA 0x00000000
#define DDRSS_PHY_1207_DATA 0x00000000
#define DDRSS_PHY_1208_DATA 0x00000000
#define DDRSS_PHY_1209_DATA 0x00000000
#define DDRSS_PHY_1210_DATA 0x00000000
#define DDRSS_PHY_1211_DATA 0x00000000
#define DDRSS_PHY_1212_DATA 0x00000000
#define DDRSS_PHY_1213_DATA 0x00000000
#define DDRSS_PHY_1214_DATA 0x00000000
#define DDRSS_PHY_1215_DATA 0x00000000
#define DDRSS_PHY_1216_DATA 0x00000000
#define DDRSS_PHY_1217_DATA 0x00000000
#define DDRSS_PHY_1218_DATA 0x00000000
#define DDRSS_PHY_1219_DATA 0x00000000
#define DDRSS_PHY_1220_DATA 0x00000000
#define DDRSS_PHY_1221_DATA 0x00000000
#define DDRSS_PHY_1222_DATA 0x00000000
#define DDRSS_PHY_1223_DATA 0x00000000
#define DDRSS_PHY_1224_DATA 0x00000000
#define DDRSS_PHY_1225_DATA 0x00000000
#define DDRSS_PHY_1226_DATA 0x00000000
#define DDRSS_PHY_1227_DATA 0x00000000
#define DDRSS_PHY_1228_DATA 0x00000000
#define DDRSS_PHY_1229_DATA 0x00000000
#define DDRSS_PHY_1230_DATA 0x00000000
#define DDRSS_PHY_1231_DATA 0x00000000
#define DDRSS_PHY_1232_DATA 0x00000000
#define DDRSS_PHY_1233_DATA 0x00000000
#define DDRSS_PHY_1234_DATA 0x00000000
#define DDRSS_PHY_1235_DATA 0x00000000
#define DDRSS_PHY_1236_DATA 0x00000000
#define DDRSS_PHY_1237_DATA 0x00000000
#define DDRSS_PHY_1238_DATA 0x00000000
#define DDRSS_PHY_1239_DATA 0x00000000
#define DDRSS_PHY_1240_DATA 0x00000000
#define DDRSS_PHY_1241_DATA 0x00000000
#define DDRSS_PHY_1242_DATA 0x00000000
#define DDRSS_PHY_1243_DATA 0x00000000
#define DDRSS_PHY_1244_DATA 0x00000000
#define DDRSS_PHY_1245_DATA 0x00000000
#define DDRSS_PHY_1246_DATA 0x00000000
#define DDRSS_PHY_1247_DATA 0x00000000
#define DDRSS_PHY_1248_DATA 0x00000000
#define DDRSS_PHY_1249_DATA 0x00000000
#define DDRSS_PHY_1250_DATA 0x00000000
#define DDRSS_PHY_1251_DATA 0x00000000
#define DDRSS_PHY_1252_DATA 0x00000000
#define DDRSS_PHY_1253_DATA 0x00000000
#define DDRSS_PHY_1254_DATA 0x00000000
#define DDRSS_PHY_1255_DATA 0x00000000
#define DDRSS_PHY_1256_DATA 0x00000000
#define DDRSS_PHY_1257_DATA 0x00000000
#define DDRSS_PHY_1258_DATA 0x00000000
#define DDRSS_PHY_1259_DATA 0x00000000
#define DDRSS_PHY_1260_DATA 0x00000000
#define DDRSS_PHY_1261_DATA 0x00000000
#define DDRSS_PHY_1262_DATA 0x00000000
#define DDRSS_PHY_1263_DATA 0x00000000
#define DDRSS_PHY_1264_DATA 0x00000000
#define DDRSS_PHY_1265_DATA 0x00000000
#define DDRSS_PHY_1266_DATA 0x00000000
#define DDRSS_PHY_1267_DATA 0x00000000
#define DDRSS_PHY_1268_DATA 0x00000000
#define DDRSS_PHY_1269_DATA 0x00000000
#define DDRSS_PHY_1270_DATA 0x00000000
#define DDRSS_PHY_1271_DATA 0x00000000
#define DDRSS_PHY_1272_DATA 0x00000000
#define DDRSS_PHY_1273_DATA 0x00000000
#define DDRSS_PHY_1274_DATA 0x00000000
#define DDRSS_PHY_1275_DATA 0x00000000
#define DDRSS_PHY_1276_DATA 0x00000000
#define DDRSS_PHY_1277_DATA 0x00000000
#define DDRSS_PHY_1278_DATA 0x00000000
#define DDRSS_PHY_1279_DATA 0x00000000
#define DDRSS_PHY_1280_DATA 0x00000000
#define DDRSS_PHY_1281_DATA 0x00000100
#define DDRSS_PHY_1282_DATA 0x00000000
#define DDRSS_PHY_1283_DATA 0x00000000
#define DDRSS_PHY_1284_DATA 0x00000000
#define DDRSS_PHY_1285_DATA 0x00000000
#define DDRSS_PHY_1286_DATA 0x00050000
#define DDRSS_PHY_1287_DATA 0x04000100
#define DDRSS_PHY_1288_DATA 0x00000055
#define DDRSS_PHY_1289_DATA 0x00000000
#define DDRSS_PHY_1290_DATA 0x00000000
#define DDRSS_PHY_1291_DATA 0x00000000
#define DDRSS_PHY_1292_DATA 0x00000000
#define DDRSS_PHY_1293_DATA 0x01002000
#define DDRSS_PHY_1294_DATA 0x00004001
#define DDRSS_PHY_1295_DATA 0x00020028
#define DDRSS_PHY_1296_DATA 0x00010100
#define DDRSS_PHY_1297_DATA 0x00000001
#define DDRSS_PHY_1298_DATA 0x00000000
#define DDRSS_PHY_1299_DATA 0x0F0F0E06
#define DDRSS_PHY_1300_DATA 0x00010101
#define DDRSS_PHY_1301_DATA 0x010F0004
#define DDRSS_PHY_1302_DATA 0x00000000
#define DDRSS_PHY_1303_DATA 0x00000000
#define DDRSS_PHY_1304_DATA 0x00000064
#define DDRSS_PHY_1305_DATA 0x00000000
#define DDRSS_PHY_1306_DATA 0x00000000
#define DDRSS_PHY_1307_DATA 0x01020103
#define DDRSS_PHY_1308_DATA 0x0F020102
#define DDRSS_PHY_1309_DATA 0x03030303
#define DDRSS_PHY_1310_DATA 0x03030303
#define DDRSS_PHY_1311_DATA 0x00040000
#define DDRSS_PHY_1312_DATA 0x00005201
#define DDRSS_PHY_1313_DATA 0x00000000
#define DDRSS_PHY_1314_DATA 0x00000000
#define DDRSS_PHY_1315_DATA 0x00000000
#define DDRSS_PHY_1316_DATA 0x00000000
#define DDRSS_PHY_1317_DATA 0x00000000
#define DDRSS_PHY_1318_DATA 0x00000000
#define DDRSS_PHY_1319_DATA 0x07070001
#define DDRSS_PHY_1320_DATA 0x00005400
#define DDRSS_PHY_1321_DATA 0x000040A2
#define DDRSS_PHY_1322_DATA 0x00024410
#define DDRSS_PHY_1323_DATA 0x00004410
#define DDRSS_PHY_1324_DATA 0x00004410
#define DDRSS_PHY_1325_DATA 0x00004410
#define DDRSS_PHY_1326_DATA 0x00004410
#define DDRSS_PHY_1327_DATA 0x00004410
#define DDRSS_PHY_1328_DATA 0x00004410
#define DDRSS_PHY_1329_DATA 0x00004410
#define DDRSS_PHY_1330_DATA 0x00004410
#define DDRSS_PHY_1331_DATA 0x00004410
#define DDRSS_PHY_1332_DATA 0x00000000
#define DDRSS_PHY_1333_DATA 0x00000046
#define DDRSS_PHY_1334_DATA 0x00000400
#define DDRSS_PHY_1335_DATA 0x00000008
#define DDRSS_PHY_1336_DATA 0x00000000
#define DDRSS_PHY_1337_DATA 0x00000000
#define DDRSS_PHY_1338_DATA 0x00000000
#define DDRSS_PHY_1339_DATA 0x00000000
#define DDRSS_PHY_1340_DATA 0x00000000
#define DDRSS_PHY_1341_DATA 0x03000000
#define DDRSS_PHY_1342_DATA 0x00000000
#define DDRSS_PHY_1343_DATA 0x00000000
#define DDRSS_PHY_1344_DATA 0x00000000
#define DDRSS_PHY_1345_DATA 0x04102006
#define DDRSS_PHY_1346_DATA 0x00041020
#define DDRSS_PHY_1347_DATA 0x01C98C98
#define DDRSS_PHY_1348_DATA 0x3F400000
#define DDRSS_PHY_1349_DATA 0x3F3F1F3F
#define DDRSS_PHY_1350_DATA 0x0000001F
#define DDRSS_PHY_1351_DATA 0x00000000
#define DDRSS_PHY_1352_DATA 0x00000000
#define DDRSS_PHY_1353_DATA 0x00000000
#define DDRSS_PHY_1354_DATA 0x00000001
#define DDRSS_PHY_1355_DATA 0x00000000
#define DDRSS_PHY_1356_DATA 0x00000000
#define DDRSS_PHY_1357_DATA 0x00000000
#define DDRSS_PHY_1358_DATA 0x00000000
#define DDRSS_PHY_1359_DATA 0x76543210
#define DDRSS_PHY_1360_DATA 0x00000098
#define DDRSS_PHY_1361_DATA 0x00000000
#define DDRSS_PHY_1362_DATA 0x00000000
#define DDRSS_PHY_1363_DATA 0x00000000
#define DDRSS_PHY_1364_DATA 0x00040700
#define DDRSS_PHY_1365_DATA 0x00000000
#define DDRSS_PHY_1366_DATA 0x00000000
#define DDRSS_PHY_1367_DATA 0x00000000
#define DDRSS_PHY_1368_DATA 0x00000002
#define DDRSS_PHY_1369_DATA 0x00000100
#define DDRSS_PHY_1370_DATA 0x00000000
#define DDRSS_PHY_1371_DATA 0x0001F7C0
#define DDRSS_PHY_1372_DATA 0x00020002
#define DDRSS_PHY_1373_DATA 0x00000000
#define DDRSS_PHY_1374_DATA 0x00001142
#define DDRSS_PHY_1375_DATA 0x03020400
#define DDRSS_PHY_1376_DATA 0x00000080
#define DDRSS_PHY_1377_DATA 0x03900390
#define DDRSS_PHY_1378_DATA 0x03900390
#define DDRSS_PHY_1379_DATA 0x03900390
#define DDRSS_PHY_1380_DATA 0x03900390
#define DDRSS_PHY_1381_DATA 0x03900390
#define DDRSS_PHY_1382_DATA 0x03900390
#define DDRSS_PHY_1383_DATA 0x00000300
#define DDRSS_PHY_1384_DATA 0x00000300
#define DDRSS_PHY_1385_DATA 0x00000300
#define DDRSS_PHY_1386_DATA 0x00000300
#define DDRSS_PHY_1387_DATA 0x31823FC7
#define DDRSS_PHY_1388_DATA 0x00000000
#define DDRSS_PHY_1389_DATA 0x0C000D3F
#define DDRSS_PHY_1390_DATA 0x30000D3F
#define DDRSS_PHY_1391_DATA 0x300D3F11
#define DDRSS_PHY_1392_DATA 0x01990000
#define DDRSS_PHY_1393_DATA 0x000D3FCC
#define DDRSS_PHY_1394_DATA 0x00000C11
#define DDRSS_PHY_1395_DATA 0x300D3F11
#define DDRSS_PHY_1396_DATA 0x01990000
#define DDRSS_PHY_1397_DATA 0x300C3F11
#define DDRSS_PHY_1398_DATA 0x01990000
#define DDRSS_PHY_1399_DATA 0x300C3F11
#define DDRSS_PHY_1400_DATA 0x01990000
#define DDRSS_PHY_1401_DATA 0x300D3F11
#define DDRSS_PHY_1402_DATA 0x01990000
#define DDRSS_PHY_1403_DATA 0x300D3F11
#define DDRSS_PHY_1404_DATA 0x01990000
#define DDRSS_PHY_1405_DATA 0x20040004

是的、我们的测试结果是您的观点。根据您的建议、我们更改了 dtsi。子板仍然存在 memcpy 测试失败现象，、但主板没有失败情况。我对这两个板的现象非常困惑，它们具有相同的 DDR 硬件设计和 DDR 配置代码，、但它们具有不同的行为。

[引用 userid="1187" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4428149 #4428149"]Jimin、您显示的两个差异不会影响您的结果。这些只是为了与最新建议保持一致而进行的一些小改动。[/引述]

谢谢、

jimin.Li

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

Jimin、您好！

是的、一个正常工作而另一个不工作毫无意义。每个电路板是否单独供电、它们是否可以单独运行而无需相互连接？还是电路板之间共享电源？两个板之间的 DDR 接口上是否有任何常见连接？

此致、

James

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好 JJD、

是的、主板和子板可以单独供电。两个板之间的 DDR 接口上没有公共连接。 DDR 接口在两个电路板上单独连接。我们单独供电并再次进行测试、子板仍然存在 DDR 测试失败的现象、但主板始终可以通过测试。

[报价 userid="1187" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4432327 #443227")每个板是否单独供电，它们是否可以单独操作而不相互连接？还是电路板之间共享电源？ [/报价]

谢谢、

jimin.Li

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

好的、在发生故障的子板上、当您的测试代码出现故障时、您可以通过 JTAG 进行连接、打开存储器窗口以及读取/写入值吗？问题是否仍然存在？如果是、您能否像以前那样发送寄存器转储？

此致、

James

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

当遇到故障时、请查看存储器浏览器、我们发现 DDR 读/写操作可以进行访问、然后转储寄存器。

但是、DDR 写入/读取操作是不可连接的、写入一个值、但读取 B。有两个现象。

第一种现象：

为子板上电。

系统挂起导致 DDR 测试失败、连接到 JTAG、然后查看 DDR 空间、如下所示：

在 DDR 地址0x80000000上写入0xffffffff、然后从 0x80000000中读取0x00000000。看起来该值不会写入这里。

在 DDR 地址0x800000c8上写入0x00000000、然后从地址0x800000c0、0x800000c4、0x800000c8和0x800000cc 读取0x00000000。只在一个地址上写入一个4字节值、但4个4字节值已更改。

5. 然后转储寄存器输出如下所示：

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MAIN_Cortex_R5_0_0: GEL Output: Running from R5
MAIN_Cortex_R5_0_0: GEL Output: 
DDR not initialized with R5 connect.
Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR.
====
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308000 0x10460A01  //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308004 0x5D1AF3C3  //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308008 0x0171A610  //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30800C 0x40020A11  //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308010 0x00052006  //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308014 0x02050020  //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308018 0x03070101  //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30801C 0x000890B8  //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308020 0x00000000  //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308024 0x00000000  //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308028 0x00000000  //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30802C 0x000890B8  //DDRSS_CTL_11_DATA
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

MAIN_Cortex_R5_0_0: GEL Output: Running from R5
MAIN_Cortex_R5_0_0: GEL Output: 

DDR not initialized with R5 connect.

Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR.

====

MAIN_Cortex_R5_0_0: GEL Output: 0x0F308000 0x10460A01  //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308004 0x5D1AF3C3  //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308008 0x0171A610  //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30800C 0x40020A11  //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308010 0x00052006  //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308014 0x02050020  //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308018 0x03070101  //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30801C 0x000890B8  //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308020 0x00000000  //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308024 0x00000000  //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308028 0x00000000  //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30802C 0x000890B8  //DDRSS_CTL_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308030 0x00000000  //DDRSS_CTL_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308034 0x00000000  //DDRSS_CTL_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308038 0x00000000  //DDRSS_CTL_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30803C 0x000890B8  //DDRSS_CTL_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308040 0x00000000  //DDRSS_CTL_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308044 0x00000000  //DDRSS_CTL_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308048 0x00000000  //DDRSS_CTL_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30804C 0x01010100  //DDRSS_CTL_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308050 0x01000101  //DDRSS_CTL_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308054 0x01000110  //DDRSS_CTL_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308058 0x02010002  //DDRSS_CTL_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30805C 0x00027100  //DDRSS_CTL_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308060 0x00061A80  //DDRSS_CTL_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308064 0x02550255  //DDRSS_CTL_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308068 0x00000255  //DDRSS_CTL_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30806C 0x00000000  //DDRSS_CTL_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308070 0x00000000  //DDRSS_CTL_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308074 0x00000000  //DDRSS_CTL_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308078 0x00000000  //DDRSS_CTL_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30807C 0x00000000  //DDRSS_CTL_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308080 0x00000000  //DDRSS_CTL_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308084 0x00000000  //DDRSS_CTL_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308088 0x00000000  //DDRSS_CTL_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30808C 0x00000000  //DDRSS_CTL_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308090 0x00000000  //DDRSS_CTL_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308094 0x00000000  //DDRSS_CTL_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308098 0x0400091C  //DDRSS_CTL_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30809C 0x1C1C1C1C  //DDRSS_CTL_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A0 0x0400091C  //DDRSS_CTL_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A4 0x1C1C1C1C  //DDRSS_CTL_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A8 0x0400091C  //DDRSS_CTL_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080AC 0x1C1C1C1C  //DDRSS_CTL_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B0 0x05050404  //DDRSS_CTL_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B4 0x00002706  //DDRSS_CTL_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B8 0x0602001D  //DDRSS_CTL_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080BC 0x05001D0B  //DDRSS_CTL_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C0 0x00270605  //DDRSS_CTL_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C4 0x0602001D  //DDRSS_CTL_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C8 0x05001D0B  //DDRSS_CTL_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080CC 0x00270605  //DDRSS_CTL_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D0 0x0602001D  //DDRSS_CTL_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D4 0x07001D0B  //DDRSS_CTL_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D8 0x00180807  //DDRSS_CTL_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080DC 0x0400DB60  //DDRSS_CTL_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E0 0x07070009  //DDRSS_CTL_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E4 0x00001808  //DDRSS_CTL_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E8 0x0400DB60  //DDRSS_CTL_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080EC 0x07070009  //DDRSS_CTL_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F0 0x00001808  //DDRSS_CTL_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F4 0x0400DB60  //DDRSS_CTL_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F8 0x03000009  //DDRSS_CTL_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080FC 0x0D0C0002  //DDRSS_CTL_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308100 0x0D0C0D0C  //DDRSS_CTL_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308104 0x01010000  //DDRSS_CTL_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308108 0x03191919  //DDRSS_CTL_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30810C 0x0B0B0B0B  //DDRSS_CTL_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308110 0x00000B0B  //DDRSS_CTL_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308114 0x00000101  //DDRSS_CTL_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308118 0x00000000  //DDRSS_CTL_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30811C 0x01000000  //DDRSS_CTL_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308120 0x01180803  //DDRSS_CTL_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308124 0x00001860  //DDRSS_CTL_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308128 0x00000118  //DDRSS_CTL_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30812C 0x00001860  //DDRSS_CTL_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308130 0x00000118  //DDRSS_CTL_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308134 0x00001860  //DDRSS_CTL_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308138 0x00000005  //DDRSS_CTL_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30813C 0x00000000  //DDRSS_CTL_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308140 0x00000000  //DDRSS_CTL_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308144 0x00000000  //DDRSS_CTL_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308148 0x00000000  //DDRSS_CTL_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30814C 0x00000000  //DDRSS_CTL_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308150 0x00000000  //DDRSS_CTL_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308154 0x00000000  //DDRSS_CTL_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308158 0x00000000  //DDRSS_CTL_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30815C 0x00090009  //DDRSS_CTL_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308160 0x00000009  //DDRSS_CTL_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308164 0x00000000  //DDRSS_CTL_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308168 0x00000000  //DDRSS_CTL_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30816C 0x00000000  //DDRSS_CTL_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308170 0x00000000  //DDRSS_CTL_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308174 0x00000000  //DDRSS_CTL_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308178 0x00010001  //DDRSS_CTL_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30817C 0x00025501  //DDRSS_CTL_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308180 0x02550120  //DDRSS_CTL_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308184 0x02550120  //DDRSS_CTL_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308188 0x01200120  //DDRSS_CTL_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30818C 0x01200120  //DDRSS_CTL_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308190 0x00000000  //DDRSS_CTL_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308194 0x00000000  //DDRSS_CTL_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308198 0x00000000  //DDRSS_CTL_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30819C 0x00000000  //DDRSS_CTL_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A0 0x00000000  //DDRSS_CTL_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A4 0x00000000  //DDRSS_CTL_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A8 0x03010000  //DDRSS_CTL_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081AC 0x00010000  //DDRSS_CTL_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B0 0x00000000  //DDRSS_CTL_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B4 0x01000000  //DDRSS_CTL_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B8 0x80104002  //DDRSS_CTL_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081BC 0x00040003  //DDRSS_CTL_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C0 0x00040005  //DDRSS_CTL_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C4 0x00030000  //DDRSS_CTL_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C8 0x00050004  //DDRSS_CTL_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081CC 0x00000004  //DDRSS_CTL_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D0 0x00040003  //DDRSS_CTL_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D4 0x00040005  //DDRSS_CTL_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D8 0x00000000  //DDRSS_CTL_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081DC 0x00061800  //DDRSS_CTL_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E0 0x00061800  //DDRSS_CTL_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E4 0x00061800  //DDRSS_CTL_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E8 0x00061800  //DDRSS_CTL_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081EC 0x00061800  //DDRSS_CTL_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F0 0x00000000  //DDRSS_CTL_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F4 0x0000AAA0  //DDRSS_CTL_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F8 0x00061800  //DDRSS_CTL_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081FC 0x00061800  //DDRSS_CTL_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308200 0x00061800  //DDRSS_CTL_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308204 0x00061800  //DDRSS_CTL_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308208 0x00061800  //DDRSS_CTL_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30820C 0x00000000  //DDRSS_CTL_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308210 0x0000AAA0  //DDRSS_CTL_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308214 0x00061800  //DDRSS_CTL_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308218 0x00061800  //DDRSS_CTL_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30821C 0x00061800  //DDRSS_CTL_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308220 0x00061800  //DDRSS_CTL_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308224 0x00061800  //DDRSS_CTL_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308228 0x00000000  //DDRSS_CTL_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30822C 0x0000AAA0  //DDRSS_CTL_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308230 0x00000000  //DDRSS_CTL_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308234 0x00000000  //DDRSS_CTL_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308238 0x00000000  //DDRSS_CTL_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30823C 0x00000000  //DDRSS_CTL_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308240 0x00000000  //DDRSS_CTL_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308244 0x00000000  //DDRSS_CTL_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308248 0x00000000  //DDRSS_CTL_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30824C 0x00000000  //DDRSS_CTL_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308250 0x00000000  //DDRSS_CTL_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308254 0x00000000  //DDRSS_CTL_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308258 0x00000000  //DDRSS_CTL_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30825C 0x00000000  //DDRSS_CTL_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308260 0x00000000  //DDRSS_CTL_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308264 0x00000000  //DDRSS_CTL_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308268 0x00000000  //DDRSS_CTL_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30826C 0x00000000  //DDRSS_CTL_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308270 0x080C0000  //DDRSS_CTL_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308274 0x080C080C  //DDRSS_CTL_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308278 0x00000000  //DDRSS_CTL_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30827C 0x07010A09  //DDRSS_CTL_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308280 0x000E0A09  //DDRSS_CTL_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308284 0x010A0900  //DDRSS_CTL_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308288 0x0E0A0907  //DDRSS_CTL_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30828C 0x0A090000  //DDRSS_CTL_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308290 0x0A090701  //DDRSS_CTL_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308294 0x0000000E  //DDRSS_CTL_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308298 0x00040003  //DDRSS_CTL_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30829C 0x00004007  //DDRSS_CTL_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A0 0x00000000  //DDRSS_CTL_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A4 0x00000000  //DDRSS_CTL_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A8 0x00000000  //DDRSS_CTL_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082AC 0x00000000  //DDRSS_CTL_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B0 0x00000000  //DDRSS_CTL_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B4 0x00000000  //DDRSS_CTL_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B8 0x01000000  //DDRSS_CTL_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082BC 0x00000000  //DDRSS_CTL_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C0 0x00001500  //DDRSS_CTL_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C4 0x0000100E  //DDRSS_CTL_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C8 0x00000000  //DDRSS_CTL_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082CC 0x00000000  //DDRSS_CTL_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D0 0x00000001  //DDRSS_CTL_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D4 0x00000002  //DDRSS_CTL_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D8 0x00000C00  //DDRSS_CTL_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082DC 0x00001000  //DDRSS_CTL_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E0 0x00000C00  //DDRSS_CTL_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E4 0x00001000  //DDRSS_CTL_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E8 0x00000C00  //DDRSS_CTL_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082EC 0x00001000  //DDRSS_CTL_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F0 0x00000000  //DDRSS_CTL_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F4 0x00000000  //DDRSS_CTL_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F8 0x00000000  //DDRSS_CTL_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082FC 0x00000000  //DDRSS_CTL_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308300 0x00000000  //DDRSS_CTL_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308304 0x00000000  //DDRSS_CTL_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308308 0x00000000  //DDRSS_CTL_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30830C 0x00000000  //DDRSS_CTL_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308310 0x00000000  //DDRSS_CTL_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308314 0x00000000  //DDRSS_CTL_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308318 0x00000000  //DDRSS_CTL_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30831C 0x00000000  //DDRSS_CTL_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308320 0x00000000  //DDRSS_CTL_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308324 0x00000000  //DDRSS_CTL_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308328 0x00000000  //DDRSS_CTL_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30832C 0x00000000  //DDRSS_CTL_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308330 0x00042400  //DDRSS_CTL_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308334 0x00000301  //DDRSS_CTL_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308338 0x00000000  //DDRSS_CTL_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30833C 0x00000424  //DDRSS_CTL_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308340 0x00000301  //DDRSS_CTL_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308344 0x00000000  //DDRSS_CTL_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308348 0x00000424  //DDRSS_CTL_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30834C 0x00000301  //DDRSS_CTL_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308350 0x00000000  //DDRSS_CTL_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308354 0x00000424  //DDRSS_CTL_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308358 0x00000301  //DDRSS_CTL_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30835C 0x00000000  //DDRSS_CTL_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308360 0x00000424  //DDRSS_CTL_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308364 0x00000301  //DDRSS_CTL_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308368 0x00000000  //DDRSS_CTL_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30836C 0x00000424  //DDRSS_CTL_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308370 0x00000301  //DDRSS_CTL_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308374 0x00000000  //DDRSS_CTL_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308378 0x00000000  //DDRSS_CTL_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30837C 0x00000000  //DDRSS_CTL_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308380 0x00000000  //DDRSS_CTL_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308384 0x00000000  //DDRSS_CTL_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308388 0x00000000  //DDRSS_CTL_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30838C 0x00000000  //DDRSS_CTL_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308390 0x00000000  //DDRSS_CTL_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308394 0x00000000  //DDRSS_CTL_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308398 0x00000000  //DDRSS_CTL_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30839C 0x00000000  //DDRSS_CTL_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A0 0x00000000  //DDRSS_CTL_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A4 0x00000000  //DDRSS_CTL_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A8 0x00000000  //DDRSS_CTL_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083AC 0x00000000  //DDRSS_CTL_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B0 0x00001401  //DDRSS_CTL_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B4 0x00001401  //DDRSS_CTL_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B8 0x00001401  //DDRSS_CTL_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083BC 0x00001401  //DDRSS_CTL_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C0 0x00001401  //DDRSS_CTL_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C4 0x00001401  //DDRSS_CTL_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C8 0x00000493  //DDRSS_CTL_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083CC 0x00000493  //DDRSS_CTL_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D0 0x00000493  //DDRSS_CTL_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D4 0x00000493  //DDRSS_CTL_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D8 0x00000493  //DDRSS_CTL_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083DC 0x00000493  //DDRSS_CTL_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E0 0x00000000  //DDRSS_CTL_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E4 0x00000000  //DDRSS_CTL_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E8 0x00000000  //DDRSS_CTL_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083EC 0x00000000  //DDRSS_CTL_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F0 0x00000000  //DDRSS_CTL_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F4 0x00000000  //DDRSS_CTL_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F8 0x00000000  //DDRSS_CTL_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083FC 0x00000000  //DDRSS_CTL_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308400 0x00000000  //DDRSS_CTL_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308404 0x00000000  //DDRSS_CTL_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308408 0x00000000  //DDRSS_CTL_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30840C 0x00000000  //DDRSS_CTL_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308410 0x00000000  //DDRSS_CTL_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308414 0x00000000  //DDRSS_CTL_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308418 0x00000000  //DDRSS_CTL_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30841C 0x00000000  //DDRSS_CTL_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308420 0x00000000  //DDRSS_CTL_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308424 0x00000000  //DDRSS_CTL_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308428 0x00000000  //DDRSS_CTL_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30842C 0x00000000  //DDRSS_CTL_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308430 0x00000000  //DDRSS_CTL_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308434 0x00000000  //DDRSS_CTL_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308438 0x00000000  //DDRSS_CTL_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30843C 0x00000000  //DDRSS_CTL_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308440 0x00000000  //DDRSS_CTL_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308444 0x00000000  //DDRSS_CTL_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308448 0x00000000  //DDRSS_CTL_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30844C 0x00000000  //DDRSS_CTL_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308450 0x00000000  //DDRSS_CTL_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308454 0x00010000  //DDRSS_CTL_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308458 0x00000000  //DDRSS_CTL_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30845C 0x00000100  //DDRSS_CTL_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308460 0x00000000  //DDRSS_CTL_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308464 0x00000101  //DDRSS_CTL_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308468 0x00000000  //DDRSS_CTL_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30846C 0x00000000  //DDRSS_CTL_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308470 0x00000000  //DDRSS_CTL_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308474 0x00000000  //DDRSS_CTL_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308478 0x00000000  //DDRSS_CTL_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30847C 0x00000000  //DDRSS_CTL_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308480 0x00000000  //DDRSS_CTL_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308484 0x00000051  //DDRSS_CTL_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308488 0x0C181511  //DDRSS_CTL_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30848C 0x00000304  //DDRSS_CTL_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308490 0x00000000  //DDRSS_CTL_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308494 0x00000000  //DDRSS_CTL_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308498 0x00000000  //DDRSS_CTL_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30849C 0x00000000  //DDRSS_CTL_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A0 0x00000000  //DDRSS_CTL_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A4 0x00000000  //DDRSS_CTL_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A8 0x00000000  //DDRSS_CTL_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084AC 0x00000000  //DDRSS_CTL_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B0 0x00000000  //DDRSS_CTL_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B4 0x00000000  //DDRSS_CTL_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B8 0x00000000  //DDRSS_CTL_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084BC 0x00000000  //DDRSS_CTL_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C0 0x00000000  //DDRSS_CTL_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C4 0x00040000  //DDRSS_CTL_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C8 0x00800200  //DDRSS_CTL_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084CC 0x00000000  //DDRSS_CTL_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D0 0x02000400  //DDRSS_CTL_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D4 0x00000080  //DDRSS_CTL_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D8 0x00040000  //DDRSS_CTL_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084DC 0x00800200  //DDRSS_CTL_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E0 0x00000000  //DDRSS_CTL_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E4 0x00000000  //DDRSS_CTL_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E8 0x00000000  //DDRSS_CTL_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084EC 0x00000100  //DDRSS_CTL_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F0 0x01010000  //DDRSS_CTL_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F4 0x00000000  //DDRSS_CTL_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F8 0x3FFF0000  //DDRSS_CTL_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084FC 0x000FFF00  //DDRSS_CTL_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308500 0xFFFFFFFF  //DDRSS_CTL_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308504 0x000FFF00  //DDRSS_CTL_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308508 0x0A000000  //DDRSS_CTL_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30850C 0x0001FFFF  //DDRSS_CTL_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308510 0x01010101  //DDRSS_CTL_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308514 0x01010101  //DDRSS_CTL_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308518 0x00000118  //DDRSS_CTL_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30851C 0x00000C01  //DDRSS_CTL_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308520 0x00000000  //DDRSS_CTL_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308524 0x00000000  //DDRSS_CTL_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308528 0x00000000  //DDRSS_CTL_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30852C 0x01000000  //DDRSS_CTL_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308530 0x00000100  //DDRSS_CTL_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308534 0x00010000  //DDRSS_CTL_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308538 0x00000000  //DDRSS_CTL_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30853C 0x00000000  //DDRSS_CTL_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308540 0x00000000  //DDRSS_CTL_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308544 0x00000000  //DDRSS_CTL_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308548 0x00000000  //DDRSS_CTL_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30854C 0x00000000  //DDRSS_CTL_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308550 0x00000000  //DDRSS_CTL_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308554 0x00000000  //DDRSS_CTL_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308558 0x00000000  //DDRSS_CTL_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30855C 0x00000000  //DDRSS_CTL_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308560 0x00000000  //DDRSS_CTL_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308564 0x00000000  //DDRSS_CTL_345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308568 0x00000000  //DDRSS_CTL_346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30856C 0x00000000  //DDRSS_CTL_347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308570 0x00000000  //DDRSS_CTL_348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308574 0x00000000  //DDRSS_CTL_349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308578 0x00000000  //DDRSS_CTL_350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30857C 0x00000000  //DDRSS_CTL_351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308580 0x00000000  //DDRSS_CTL_352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308584 0x00000000  //DDRSS_CTL_353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308588 0x00000000  //DDRSS_CTL_354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30858C 0x00000000  //DDRSS_CTL_355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308590 0x00000000  //DDRSS_CTL_356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308594 0x00000000  //DDRSS_CTL_357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308598 0x00000000  //DDRSS_CTL_358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30859C 0x00000000  //DDRSS_CTL_359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A0 0x00000000  //DDRSS_CTL_360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A4 0x00000000  //DDRSS_CTL_361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A8 0x00000000  //DDRSS_CTL_362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085AC 0x00000000  //DDRSS_CTL_363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B0 0x00000000  //DDRSS_CTL_364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B4 0x00000066  //DDRSS_CTL_365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B8 0x00000066  //DDRSS_CTL_366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085BC 0x000000E0  //DDRSS_CTL_367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C0 0x00000000  //DDRSS_CTL_368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C4 0x00000000  //DDRSS_CTL_369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C8 0x0C000000  //DDRSS_CTL_370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085CC 0x060C0606  //DDRSS_CTL_371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D0 0x06060C06  //DDRSS_CTL_372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D4 0x00010101  //DDRSS_CTL_373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D8 0x02000000  //DDRSS_CTL_374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085DC 0x05020101  //DDRSS_CTL_375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E0 0x00000505  //DDRSS_CTL_376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E4 0x02020200  //DDRSS_CTL_377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E8 0x02020202  //DDRSS_CTL_378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085EC 0x02020202  //DDRSS_CTL_379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F0 0x02020202  //DDRSS_CTL_380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F4 0x00000000  //DDRSS_CTL_381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F8 0x00000000  //DDRSS_CTL_382_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085FC 0x04000100  //DDRSS_CTL_383_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308600 0x1E000304  //DDRSS_CTL_384_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308604 0x000030C0  //DDRSS_CTL_385_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308608 0x00000200  //DDRSS_CTL_386_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30860C 0x00000200  //DDRSS_CTL_387_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308610 0x00000200  //DDRSS_CTL_388_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308614 0x00000200  //DDRSS_CTL_389_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308618 0x0000DB60  //DDRSS_CTL_390_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30861C 0x0001E780  //DDRSS_CTL_391_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308620 0x0C0D0302  //DDRSS_CTL_392_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308624 0x001E090A  //DDRSS_CTL_393_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308628 0x000030C0  //DDRSS_CTL_394_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30862C 0x00000200  //DDRSS_CTL_395_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308630 0x00000200  //DDRSS_CTL_396_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308634 0x00000200  //DDRSS_CTL_397_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308638 0x00000200  //DDRSS_CTL_398_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30863C 0x0000DB60  //DDRSS_CTL_399_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308640 0x0001E780  //DDRSS_CTL_400_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308644 0x0C0D0302  //DDRSS_CTL_401_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308648 0x001E090A  //DDRSS_CTL_402_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30864C 0x000030C0  //DDRSS_CTL_403_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308650 0x00000200  //DDRSS_CTL_404_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308654 0x00000200  //DDRSS_CTL_405_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308658 0x00000200  //DDRSS_CTL_406_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30865C 0x00000200  //DDRSS_CTL_407_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308660 0x0000DB60  //DDRSS_CTL_408_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308664 0x0001E780  //DDRSS_CTL_409_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308668 0x0C0D0302  //DDRSS_CTL_410_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30866C 0x0000090A  //DDRSS_CTL_411_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308670 0x00000000  //DDRSS_CTL_412_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308674 0x0302000A  //DDRSS_CTL_413_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308678 0x01000500  //DDRSS_CTL_414_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30867C 0x01010001  //DDRSS_CTL_415_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308680 0x00010001  //DDRSS_CTL_416_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308684 0x01010001  //DDRSS_CTL_417_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308688 0x02010000  //DDRSS_CTL_418_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30868C 0x00000200  //DDRSS_CTL_419_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308690 0x02000201  //DDRSS_CTL_420_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308694 0x00000000  //DDRSS_CTL_421_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308698 0x00202020  //DDRSS_CTL_422_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A000 0x00000A01  //DDRSS_PI_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A004 0xAE8D79E2  //DDRSS_PI_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A008 0x0714B570  //DDRSS_PI_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A00C 0x01011387  //DDRSS_PI_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A010 0x00000001  //DDRSS_PI_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A014 0x00010064  //DDRSS_PI_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A018 0x00000000  //DDRSS_PI_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A01C 0x00000000  //DDRSS_PI_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A020 0x00000000  //DDRSS_PI_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A024 0x00047CB2  //DDRSS_PI_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A028 0x0000000F  //DDRSS_PI_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A02C 0x00000000  //DDRSS_PI_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A030 0x00000000  //DDRSS_PI_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A034 0x00010001  //DDRSS_PI_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A038 0x00000000  //DDRSS_PI_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A03C 0x00010001  //DDRSS_PI_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A040 0x00000005  //DDRSS_PI_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A044 0x00010000  //DDRSS_PI_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A048 0x00000000  //DDRSS_PI_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A04C 0x00000000  //DDRSS_PI_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A050 0x00000000  //DDRSS_PI_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A054 0x00000000  //DDRSS_PI_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A058 0x00000000  //DDRSS_PI_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A05C 0x00000000  //DDRSS_PI_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A060 0x280D0001  //DDRSS_PI_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A064 0x00000000  //DDRSS_PI_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A068 0x00010000  //DDRSS_PI_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A06C 0x00003200  //DDRSS_PI_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A070 0x00000000  //DDRSS_PI_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A074 0x00000000  //DDRSS_PI_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A078 0x00060602  //DDRSS_PI_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A07C 0x00000000  //DDRSS_PI_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A080 0x00000000  //DDRSS_PI_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A084 0x00000000  //DDRSS_PI_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A088 0x00000001  //DDRSS_PI_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A08C 0x00000055  //DDRSS_PI_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A090 0x000000AA  //DDRSS_PI_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A094 0x000000AD  //DDRSS_PI_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A098 0x00000052  //DDRSS_PI_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A09C 0x0000006A  //DDRSS_PI_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A0 0x00000095  //DDRSS_PI_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A4 0x00000095  //DDRSS_PI_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A8 0x000000AD  //DDRSS_PI_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0AC 0x00000000  //DDRSS_PI_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B0 0x00000000  //DDRSS_PI_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B4 0x00010100  //DDRSS_PI_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B8 0x00000014  //DDRSS_PI_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0BC 0x000007D0  //DDRSS_PI_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C0 0x00000300  //DDRSS_PI_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C4 0x00000000  //DDRSS_PI_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C8 0x00000000  //DDRSS_PI_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0CC 0x01000000  //DDRSS_PI_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D0 0x00010101  //DDRSS_PI_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D4 0x0100090C  //DDRSS_PI_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D8 0x00000000  //DDRSS_PI_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0DC 0x00010000  //DDRSS_PI_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E0 0x00000000  //DDRSS_PI_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E4 0x00000000  //DDRSS_PI_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E8 0x00000000  //DDRSS_PI_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0EC 0x00000000  //DDRSS_PI_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F0 0x00001400  //DDRSS_PI_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F4 0x00000000  //DDRSS_PI_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F8 0x01000000  //DDRSS_PI_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0FC 0x00000404  //DDRSS_PI_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A100 0x00000001  //DDRSS_PI_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A104 0x0001010E  //DDRSS_PI_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A108 0x02040100  //DDRSS_PI_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A10C 0x00010000  //DDRSS_PI_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A110 0x00000034  //DDRSS_PI_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A114 0x00000000  //DDRSS_PI_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A118 0x00000000  //DDRSS_PI_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A11C 0x00000000  //DDRSS_PI_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A120 0x00000000  //DDRSS_PI_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A124 0x00000000  //DDRSS_PI_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A128 0x00000000  //DDRSS_PI_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A12C 0x00000005  //DDRSS_PI_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A130 0x01000000  //DDRSS_PI_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A134 0x04000100  //DDRSS_PI_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A138 0x00020000  //DDRSS_PI_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A13C 0x00010002  //DDRSS_PI_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A140 0x00000001  //DDRSS_PI_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A144 0x00020001  //DDRSS_PI_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A148 0x00020002  //DDRSS_PI_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A14C 0x29C02000  //DDRSS_PI_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A150 0x00000000  //DDRSS_PI_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A154 0x00000000  //DDRSS_PI_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A158 0x00000000  //DDRSS_PI_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A15C 0x00000000  //DDRSS_PI_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A160 0x00000000  //DDRSS_PI_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A164 0x00000000  //DDRSS_PI_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A168 0x00000000  //DDRSS_PI_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A16C 0x00000300  //DDRSS_PI_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A170 0x0A090B0C  //DDRSS_PI_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A174 0x04060708  //DDRSS_PI_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A178 0x01000005  //DDRSS_PI_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A17C 0x00000800  //DDRSS_PI_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A180 0x00000000  //DDRSS_PI_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A184 0x00010008  //DDRSS_PI_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A188 0x00000000  //DDRSS_PI_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A18C 0x0000AA00  //DDRSS_PI_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A190 0x00000000  //DDRSS_PI_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A194 0x00010000  //DDRSS_PI_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A198 0x00000000  //DDRSS_PI_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A19C 0x00000000  //DDRSS_PI_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A0 0x00000000  //DDRSS_PI_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A4 0x00000000  //DDRSS_PI_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A8 0x00000000  //DDRSS_PI_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1AC 0x00000000  //DDRSS_PI_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B0 0x00000000  //DDRSS_PI_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B4 0x00000000  //DDRSS_PI_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B8 0x00000000  //DDRSS_PI_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1BC 0x00000000  //DDRSS_PI_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C0 0x00000000  //DDRSS_PI_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C4 0x00000000  //DDRSS_PI_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C8 0x00000000  //DDRSS_PI_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1CC 0x00000000  //DDRSS_PI_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D0 0x00000000  //DDRSS_PI_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D4 0x00000000  //DDRSS_PI_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D8 0x00000000  //DDRSS_PI_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1DC 0x00000000  //DDRSS_PI_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E0 0x00000000  //DDRSS_PI_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E4 0x00000000  //DDRSS_PI_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E8 0x00000000  //DDRSS_PI_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1EC 0x00000000  //DDRSS_PI_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F0 0x00000008  //DDRSS_PI_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F4 0x00000000  //DDRSS_PI_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F8 0x00000000  //DDRSS_PI_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1FC 0x00000000  //DDRSS_PI_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A200 0x00000000  //DDRSS_PI_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A204 0x00000000  //DDRSS_PI_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A208 0x00000000  //DDRSS_PI_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A20C 0x00000000  //DDRSS_PI_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A210 0x00000000  //DDRSS_PI_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A214 0x00010100  //DDRSS_PI_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A218 0x00000000  //DDRSS_PI_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A21C 0x00000000  //DDRSS_PI_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A220 0x00027100  //DDRSS_PI_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A224 0x00061A80  //DDRSS_PI_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A228 0x00000100  //DDRSS_PI_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A22C 0x00000000  //DDRSS_PI_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A230 0x00000000  //DDRSS_PI_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A234 0x00000000  //DDRSS_PI_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A238 0x00000000  //DDRSS_PI_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A23C 0x00000000  //DDRSS_PI_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A240 0x01000000  //DDRSS_PI_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A244 0xC1010003  //DDRSS_PI_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A248 0x02000101  //DDRSS_PI_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A24C 0x01030101  //DDRSS_PI_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A250 0x00010400  //DDRSS_PI_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A254 0x06000105  //DDRSS_PI_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A258 0x01070001  //DDRSS_PI_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A25C 0x00000000  //DDRSS_PI_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A260 0x00000000  //DDRSS_PI_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A264 0x00000001  //DDRSS_PI_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A268 0x00010000  //DDRSS_PI_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A26C 0x00000000  //DDRSS_PI_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A270 0x00000000  //DDRSS_PI_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A274 0x00000000  //DDRSS_PI_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A278 0x00000000  //DDRSS_PI_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A27C 0x00010000  //DDRSS_PI_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A280 0x00000004  //DDRSS_PI_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A284 0x00000000  //DDRSS_PI_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A288 0x00000000  //DDRSS_PI_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A28C 0x00000000  //DDRSS_PI_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A290 0x00007800  //DDRSS_PI_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A294 0x00780078  //DDRSS_PI_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A298 0x00141414  //DDRSS_PI_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A29C 0x0000003A  //DDRSS_PI_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A0 0x0000003A  //DDRSS_PI_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A4 0x0004003A  //DDRSS_PI_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A8 0x04000400  //DDRSS_PI_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2AC 0xC8040009  //DDRSS_PI_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B0 0x0400091C  //DDRSS_PI_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B4 0x00091CC8  //DDRSS_PI_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B8 0x001CC804  //DDRSS_PI_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2BC 0x00000118  //DDRSS_PI_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C0 0x00001860  //DDRSS_PI_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C4 0x00000118  //DDRSS_PI_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C8 0x00001860  //DDRSS_PI_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2CC 0x00000118  //DDRSS_PI_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D0 0x04001860  //DDRSS_PI_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D4 0x01010404  //DDRSS_PI_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D8 0x00001901  //DDRSS_PI_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2DC 0x00190019  //DDRSS_PI_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E0 0x010C010C  //DDRSS_PI_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E4 0x0000010C  //DDRSS_PI_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E8 0x00000000  //DDRSS_PI_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2EC 0x05000000  //DDRSS_PI_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F0 0x01010505  //DDRSS_PI_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F4 0x01010101  //DDRSS_PI_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F8 0x00181818  //DDRSS_PI_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2FC 0x00000000  //DDRSS_PI_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A300 0x00000000  //DDRSS_PI_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A304 0x0D000000  //DDRSS_PI_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A308 0x0A0A0D0D  //DDRSS_PI_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A30C 0x0303030A  //DDRSS_PI_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A310 0x00000000  //DDRSS_PI_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A314 0x00000000  //DDRSS_PI_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A318 0x00000000  //DDRSS_PI_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A31C 0x00000000  //DDRSS_PI_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A320 0x00000000  //DDRSS_PI_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A324 0x00000000  //DDRSS_PI_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A328 0x00000000  //DDRSS_PI_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A32C 0x00000000  //DDRSS_PI_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A330 0x00000000  //DDRSS_PI_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A334 0x00000000  //DDRSS_PI_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A338 0x00000000  //DDRSS_PI_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A33C 0x00000000  //DDRSS_PI_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A340 0x00000000  //DDRSS_PI_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A344 0x0D090000  //DDRSS_PI_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A348 0x0D09000D  //DDRSS_PI_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A34C 0x0D09000D  //DDRSS_PI_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A350 0x0000000D  //DDRSS_PI_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A354 0x00000000  //DDRSS_PI_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A358 0x00000000  //DDRSS_PI_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A35C 0x00000000  //DDRSS_PI_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A360 0x00000000  //DDRSS_PI_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A364 0x16000000  //DDRSS_PI_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A368 0x001600C8  //DDRSS_PI_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A36C 0x001600C8  //DDRSS_PI_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A370 0x010100C8  //DDRSS_PI_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A374 0x00001B01  //DDRSS_PI_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A378 0x1F0F0053  //DDRSS_PI_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A37C 0x05000001  //DDRSS_PI_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A380 0x001B0A0D  //DDRSS_PI_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A384 0x1F0F0053  //DDRSS_PI_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A388 0x05000001  //DDRSS_PI_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A38C 0x001B0A0D  //DDRSS_PI_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A390 0x1F0F0053  //DDRSS_PI_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A394 0x05000001  //DDRSS_PI_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A398 0x00010A0D  //DDRSS_PI_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A39C 0x0C0B0700  //DDRSS_PI_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A0 0x000D0605  //DDRSS_PI_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A4 0x0000C570  //DDRSS_PI_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A8 0x0000001D  //DDRSS_PI_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3AC 0x180A0800  //DDRSS_PI_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B0 0x0B071C1C  //DDRSS_PI_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B4 0x0D06050C  //DDRSS_PI_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B8 0x0000C570  //DDRSS_PI_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3BC 0x0000001D  //DDRSS_PI_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C0 0x180A0800  //DDRSS_PI_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C4 0x0B071C1C  //DDRSS_PI_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C8 0x0D06050C  //DDRSS_PI_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3CC 0x0000C570  //DDRSS_PI_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D0 0x0000001D  //DDRSS_PI_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D4 0x180A0800  //DDRSS_PI_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D8 0x00001C1C  //DDRSS_PI_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3DC 0x000030C0  //DDRSS_PI_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E0 0x0001E780  //DDRSS_PI_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E4 0x000030C0  //DDRSS_PI_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E8 0x0001E780  //DDRSS_PI_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3EC 0x000030C0  //DDRSS_PI_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F0 0x0001E780  //DDRSS_PI_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F4 0x02550255  //DDRSS_PI_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F8 0x03030255  //DDRSS_PI_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3FC 0x00025503  //DDRSS_PI_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A400 0x02550255  //DDRSS_PI_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A404 0x0C080C08  //DDRSS_PI_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A408 0x00000C08  //DDRSS_PI_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A40C 0x000890B8  //DDRSS_PI_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A410 0x00000000  //DDRSS_PI_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A414 0x00000000  //DDRSS_PI_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A418 0x00000000  //DDRSS_PI_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A41C 0x00000120  //DDRSS_PI_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A420 0x000890B8  //DDRSS_PI_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A424 0x00000000  //DDRSS_PI_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A428 0x00000000  //DDRSS_PI_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A42C 0x00000000  //DDRSS_PI_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A430 0x00000120  //DDRSS_PI_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A434 0x000890B8  //DDRSS_PI_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A438 0x00000000  //DDRSS_PI_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A43C 0x00000000  //DDRSS_PI_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A440 0x00000000  //DDRSS_PI_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A444 0x02000120  //DDRSS_PI_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A448 0x00000080  //DDRSS_PI_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A44C 0x00020000  //DDRSS_PI_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A450 0x00000080  //DDRSS_PI_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A454 0x00020000  //DDRSS_PI_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A458 0x00000080  //DDRSS_PI_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A45C 0x00000000  //DDRSS_PI_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A460 0x00000000  //DDRSS_PI_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A464 0x00040404  //DDRSS_PI_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A468 0x00000000  //DDRSS_PI_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A46C 0x02010102  //DDRSS_PI_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A470 0x67676767  //DDRSS_PI_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A474 0x00000202  //DDRSS_PI_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A478 0x00000000  //DDRSS_PI_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A47C 0x00000000  //DDRSS_PI_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A480 0x00000000  //DDRSS_PI_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A484 0x00000000  //DDRSS_PI_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A488 0x00000000  //DDRSS_PI_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A48C 0x0D100F00  //DDRSS_PI_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A490 0x0003020E  //DDRSS_PI_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A494 0x00000001  //DDRSS_PI_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A498 0x01000000  //DDRSS_PI_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A49C 0x00020201  //DDRSS_PI_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A0 0x00000000  //DDRSS_PI_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A4 0x00000424  //DDRSS_PI_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A8 0x00000301  //DDRSS_PI_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4AC 0x00000000  //DDRSS_PI_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B0 0x00000000  //DDRSS_PI_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B4 0x00000000  //DDRSS_PI_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B8 0x00001401  //DDRSS_PI_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4BC 0x00000493  //DDRSS_PI_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C0 0x00000000  //DDRSS_PI_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C4 0x00000424  //DDRSS_PI_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C8 0x00000301  //DDRSS_PI_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4CC 0x00000000  //DDRSS_PI_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D0 0x00000000  //DDRSS_PI_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D4 0x00000000  //DDRSS_PI_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D8 0x00001401  //DDRSS_PI_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4DC 0x00000493  //DDRSS_PI_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E0 0x00000000  //DDRSS_PI_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E4 0x00000424  //DDRSS_PI_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E8 0x00000301  //DDRSS_PI_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4EC 0x00000000  //DDRSS_PI_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F0 0x00000000  //DDRSS_PI_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F4 0x00000000  //DDRSS_PI_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F8 0x00001401  //DDRSS_PI_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4FC 0x00000493  //DDRSS_PI_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A500 0x00000000  //DDRSS_PI_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A504 0x00000424  //DDRSS_PI_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A508 0x00000424  //DDRSS_PI_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A50C 0x00000301  //DDRSS_PI_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A510 0x00000000  //DDRSS_PI_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A514 0x00000000  //DDRSS_PI_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A518 0x00000000  //DDRSS_PI_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A51C 0x00001401  //DDRSS_PI_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A520 0x00000493  //DDRSS_PI_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A524 0x00000000  //DDRSS_PI_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A528 0x00000424  //DDRSS_PI_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A52C 0x00000301  //DDRSS_PI_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A530 0x00000000  //DDRSS_PI_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A534 0x00000000  //DDRSS_PI_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A538 0x00000000  //DDRSS_PI_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A53C 0x00001401  //DDRSS_PI_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A540 0x00000493  //DDRSS_PI_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A544 0x00000000  //DDRSS_PI_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A548 0x00000424  //DDRSS_PI_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A54C 0x00000301  //DDRSS_PI_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A550 0x00000000  //DDRSS_PI_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A554 0x00000000  //DDRSS_PI_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A558 0x00000000  //DDRSS_PI_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A55C 0x00001401  //DDRSS_PI_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A560 0x00000493  //DDRSS_PI_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C000 0x04C00000  //DDRSS_PHY_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C004 0x00000000  //DDRSS_PHY_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C008 0x00000200  //DDRSS_PHY_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C00C 0x00000000  //DDRSS_PHY_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C010 0x00000000  //DDRSS_PHY_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C014 0x00000000  //DDRSS_PHY_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C018 0x00000000  //DDRSS_PHY_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C01C 0x00000000  //DDRSS_PHY_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C020 0x00000001  //DDRSS_PHY_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C024 0x00000000  //DDRSS_PHY_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C028 0x000C0000  //DDRSS_PHY_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C02C 0x010101FF  //DDRSS_PHY_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C030 0x00010000  //DDRSS_PHY_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C034 0x00C02804  //DDRSS_PHY_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C038 0x00CC0008  //DDRSS_PHY_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C03C 0x00660201  //DDRSS_PHY_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C040 0x00000000  //DDRSS_PHY_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C044 0x00000000  //DDRSS_PHY_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C048 0x00000000  //DDRSS_PHY_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C04C 0x0000AAAA  //DDRSS_PHY_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C050 0x00005555  //DDRSS_PHY_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C054 0x0000B5B5  //DDRSS_PHY_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C058 0x00004A4A  //DDRSS_PHY_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C05C 0x00005656  //DDRSS_PHY_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C060 0x0000A9A9  //DDRSS_PHY_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C064 0x0000B7B7  //DDRSS_PHY_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C068 0x00004848  //DDRSS_PHY_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C06C 0x00000000  //DDRSS_PHY_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C070 0x00000000  //DDRSS_PHY_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C074 0x08000000  //DDRSS_PHY_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C078 0x0F000008  //DDRSS_PHY_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C07C 0x00000F0F  //DDRSS_PHY_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C080 0x00E4E400  //DDRSS_PHY_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C084 0x00070820  //DDRSS_PHY_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C088 0x000C0020  //DDRSS_PHY_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C08C 0x00062000  //DDRSS_PHY_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C090 0x00000000  //DDRSS_PHY_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C094 0x55555555  //DDRSS_PHY_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C098 0xAAAAAAAA  //DDRSS_PHY_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C09C 0x55555555  //DDRSS_PHY_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A0 0xAAAAAAAA  //DDRSS_PHY_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A4 0x00005555  //DDRSS_PHY_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A8 0x01000100  //DDRSS_PHY_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0AC 0x00800180  //DDRSS_PHY_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B0 0x00000000  //DDRSS_PHY_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B4 0x00100000  //DDRSS_PHY_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B8 0x00000000  //DDRSS_PHY_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0BC 0x140A000D  //DDRSS_PHY_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C0 0x00000009  //DDRSS_PHY_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C4 0x00020700  //DDRSS_PHY_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C8 0x019C0184  //DDRSS_PHY_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0CC 0x00000FFF  //DDRSS_PHY_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D0 0x00000000  //DDRSS_PHY_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D4 0x02640258  //DDRSS_PHY_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D8 0x00000030  //DDRSS_PHY_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0DC 0x012C003C  //DDRSS_PHY_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E0 0x00000000  //DDRSS_PHY_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E4 0x0C000000  //DDRSS_PHY_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E8 0x07FF0000  //DDRSS_PHY_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0EC 0x00000000  //DDRSS_PHY_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F0 0x00000000  //DDRSS_PHY_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F4 0x00000000  //DDRSS_PHY_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F8 0x00000000  //DDRSS_PHY_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0FC 0x00000000  //DDRSS_PHY_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C100 0x00000000  //DDRSS_PHY_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C104 0x00000004  //DDRSS_PHY_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C108 0x00000000  //DDRSS_PHY_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C10C 0x00000000  //DDRSS_PHY_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C110 0x00000000  //DDRSS_PHY_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C114 0x00000000  //DDRSS_PHY_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C118 0x00000000  //DDRSS_PHY_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C11C 0x00000000  //DDRSS_PHY_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C120 0x041F07FF  //DDRSS_PHY_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C124 0x00000000  //DDRSS_PHY_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C128 0x01CCB001  //DDRSS_PHY_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C12C 0x2000CCB0  //DDRSS_PHY_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C130 0x20000140  //DDRSS_PHY_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C134 0x07FF0200  //DDRSS_PHY_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C138 0x0000DD01  //DDRSS_PHY_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C13C 0x10100303  //DDRSS_PHY_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C140 0x10101010  //DDRSS_PHY_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C144 0x10101010  //DDRSS_PHY_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C148 0x00021010  //DDRSS_PHY_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C14C 0x00100010  //DDRSS_PHY_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C150 0x00100010  //DDRSS_PHY_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C154 0x00100010  //DDRSS_PHY_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C158 0x00100010  //DDRSS_PHY_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C15C 0x02020010  //DDRSS_PHY_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C160 0x51515041  //DDRSS_PHY_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C164 0x31804000  //DDRSS_PHY_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C168 0x04A80340  //DDRSS_PHY_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C16C 0x01008080  //DDRSS_PHY_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C170 0x04050001  //DDRSS_PHY_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C174 0x00000504  //DDRSS_PHY_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C178 0x42100010  //DDRSS_PHY_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C17C 0x010C053E  //DDRSS_PHY_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C180 0x000F0C14  //DDRSS_PHY_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C184 0x01000140  //DDRSS_PHY_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C188 0x007A0120  //DDRSS_PHY_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C18C 0x00000C00  //DDRSS_PHY_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C190 0x000001CC  //DDRSS_PHY_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C194 0x20100200  //DDRSS_PHY_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C198 0x00000005  //DDRSS_PHY_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C19C 0x76543210  //DDRSS_PHY_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A0 0x00000008  //DDRSS_PHY_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A4 0x02800280  //DDRSS_PHY_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A8 0x02800280  //DDRSS_PHY_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1AC 0x02800280  //DDRSS_PHY_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B0 0x02800280  //DDRSS_PHY_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B4 0x01900280  //DDRSS_PHY_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B8 0x0000B400  //DDRSS_PHY_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1BC 0x00B400A8  //DDRSS_PHY_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C0 0x00AE00A2  //DDRSS_PHY_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C4 0x00BA00A2  //DDRSS_PHY_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C8 0x00BA00A8  //DDRSS_PHY_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1CC 0x00AE00A8  //DDRSS_PHY_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D0 0x00AE00A2  //DDRSS_PHY_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D4 0x00B400A2  //DDRSS_PHY_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D8 0x00B400A2  //DDRSS_PHY_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1DC 0x015E00A8  //DDRSS_PHY_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E0 0x01A00000  //DDRSS_PHY_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E4 0x00000000  //DDRSS_PHY_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E8 0x00000000  //DDRSS_PHY_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1EC 0x00080200  //DDRSS_PHY_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F0 0x00000000  //DDRSS_PHY_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F4 0x00000000  //DDRSS_PHY_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C400 0x04C00000  //DDRSS_PHY_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C404 0x00000000  //DDRSS_PHY_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C408 0x00000200  //DDRSS_PHY_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C40C 0x00000000  //DDRSS_PHY_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C410 0x00000000  //DDRSS_PHY_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C414 0x00000000  //DDRSS_PHY_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C418 0x00000000  //DDRSS_PHY_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C41C 0x00000000  //DDRSS_PHY_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C420 0x00000001  //DDRSS_PHY_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C424 0x00000000  //DDRSS_PHY_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C428 0x000C0000  //DDRSS_PHY_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C42C 0x010101FF  //DDRSS_PHY_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C430 0x00010000  //DDRSS_PHY_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C434 0x00C02804  //DDRSS_PHY_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C438 0x00CC0008  //DDRSS_PHY_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C43C 0x00660201  //DDRSS_PHY_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C440 0x00000000  //DDRSS_PHY_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C444 0x00000000  //DDRSS_PHY_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C448 0x00000000  //DDRSS_PHY_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C44C 0x0000AAAA  //DDRSS_PHY_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C450 0x00005555  //DDRSS_PHY_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C454 0x0000B5B5  //DDRSS_PHY_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C458 0x00004A4A  //DDRSS_PHY_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C45C 0x00005656  //DDRSS_PHY_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C460 0x0000A9A9  //DDRSS_PHY_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C464 0x0000B7B7  //DDRSS_PHY_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C468 0x00004848  //DDRSS_PHY_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C46C 0x00000000  //DDRSS_PHY_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C470 0x00000000  //DDRSS_PHY_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C474 0x08000000  //DDRSS_PHY_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C478 0x0F000008  //DDRSS_PHY_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C47C 0x00000F0F  //DDRSS_PHY_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C480 0x00E4E400  //DDRSS_PHY_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C484 0x00070820  //DDRSS_PHY_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C488 0x000C0020  //DDRSS_PHY_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C48C 0x00062000  //DDRSS_PHY_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C490 0x00000000  //DDRSS_PHY_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C494 0x55555555  //DDRSS_PHY_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C498 0xAAAAAAAA  //DDRSS_PHY_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C49C 0x55555555  //DDRSS_PHY_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A0 0xAAAAAAAA  //DDRSS_PHY_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A4 0x00005555  //DDRSS_PHY_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A8 0x01000100  //DDRSS_PHY_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4AC 0x00800180  //DDRSS_PHY_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B0 0x00000000  //DDRSS_PHY_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B4 0x00100000  //DDRSS_PHY_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B8 0x00000000  //DDRSS_PHY_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4BC 0x160A000D  //DDRSS_PHY_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C0 0x0000000D  //DDRSS_PHY_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C4 0x00020200  //DDRSS_PHY_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C8 0x01A80190  //DDRSS_PHY_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4CC 0x00000FFF  //DDRSS_PHY_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D0 0x00000000  //DDRSS_PHY_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D4 0x02700264  //DDRSS_PHY_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D8 0x00000030  //DDRSS_PHY_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4DC 0x0120003C  //DDRSS_PHY_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E0 0x00000000  //DDRSS_PHY_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E4 0x0C000000  //DDRSS_PHY_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E8 0x07FF0000  //DDRSS_PHY_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4EC 0x00000000  //DDRSS_PHY_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F0 0x00000000  //DDRSS_PHY_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F4 0x00000000  //DDRSS_PHY_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F8 0x00000000  //DDRSS_PHY_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4FC 0x00000000  //DDRSS_PHY_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C500 0x00000000  //DDRSS_PHY_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C504 0x00000004  //DDRSS_PHY_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C508 0x00000000  //DDRSS_PHY_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C50C 0x00000000  //DDRSS_PHY_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C510 0x00000000  //DDRSS_PHY_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C514 0x00000000  //DDRSS_PHY_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C518 0x00000000  //DDRSS_PHY_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C51C 0x00000000  //DDRSS_PHY_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C520 0x041F07FF  //DDRSS_PHY_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C524 0x00000000  //DDRSS_PHY_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C528 0x01CCB001  //DDRSS_PHY_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C52C 0x2000CCB0  //DDRSS_PHY_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C530 0x20000140  //DDRSS_PHY_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C534 0x07FF0200  //DDRSS_PHY_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C538 0x0000DD01  //DDRSS_PHY_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C53C 0x10100303  //DDRSS_PHY_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C540 0x10101010  //DDRSS_PHY_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C544 0x10101010  //DDRSS_PHY_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C548 0x00021010  //DDRSS_PHY_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C54C 0x00100010  //DDRSS_PHY_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C550 0x00100010  //DDRSS_PHY_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C554 0x00100010  //DDRSS_PHY_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C558 0x00100010  //DDRSS_PHY_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C55C 0x02020010  //DDRSS_PHY_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C560 0x51515041  //DDRSS_PHY_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C564 0x31804000  //DDRSS_PHY_345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C568 0x04A80340  //DDRSS_PHY_346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C56C 0x01008080  //DDRSS_PHY_347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C570 0x04050001  //DDRSS_PHY_348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C574 0x00000504  //DDRSS_PHY_349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C578 0x42100010  //DDRSS_PHY_350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C57C 0x010C053E  //DDRSS_PHY_351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C580 0x000F0C14  //DDRSS_PHY_352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C584 0x01000140  //DDRSS_PHY_353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C588 0x007A0120  //DDRSS_PHY_354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C58C 0x00000C00  //DDRSS_PHY_355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C590 0x000001CC  //DDRSS_PHY_356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C594 0x20100200  //DDRSS_PHY_357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C598 0x00000005  //DDRSS_PHY_358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C59C 0x76543210  //DDRSS_PHY_359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A0 0x00000008  //DDRSS_PHY_360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A4 0x02800280  //DDRSS_PHY_361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A8 0x02800280  //DDRSS_PHY_362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5AC 0x02800280  //DDRSS_PHY_363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B0 0x02800280  //DDRSS_PHY_364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B4 0x019C0280  //DDRSS_PHY_365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B8 0x0000AE00  //DDRSS_PHY_366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5BC 0x00A800A2  //DDRSS_PHY_367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C0 0x00A8009C  //DDRSS_PHY_368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C4 0x00AE0096  //DDRSS_PHY_369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C8 0x00AE00A2  //DDRSS_PHY_370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5CC 0x00A800A2  //DDRSS_PHY_371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D0 0x00AE00A2  //DDRSS_PHY_372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D4 0x00A800A2  //DDRSS_PHY_373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D8 0x00AE0096  //DDRSS_PHY_374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5DC 0x016A00A2  //DDRSS_PHY_375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E0 0x01A00000  //DDRSS_PHY_376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E4 0x00000000  //DDRSS_PHY_377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E8 0x00000000  //DDRSS_PHY_378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5EC 0x00080200  //DDRSS_PHY_379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F0 0x00000000  //DDRSS_PHY_380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F4 0x00000000  //DDRSS_PHY_381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C800 0x00000100  //DDRSS_PHY_512_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C804 0x00001000  //DDRSS_PHY_513_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C808 0x000A0000  //DDRSS_PHY_514_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C80C 0x00000000  //DDRSS_PHY_515_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C810 0x00000000  //DDRSS_PHY_516_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C814 0x00000100  //DDRSS_PHY_517_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C818 0x00000000  //DDRSS_PHY_518_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C81C 0x00000000  //DDRSS_PHY_519_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C820 0x00000000  //DDRSS_PHY_520_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C824 0x00000000  //DDRSS_PHY_521_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C828 0x00000000  //DDRSS_PHY_522_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C82C 0x00000000  //DDRSS_PHY_523_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C830 0x00000000  //DDRSS_PHY_524_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C834 0x00DCBA98  //DDRSS_PHY_525_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C838 0x00000000  //DDRSS_PHY_526_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C83C 0x00000000  //DDRSS_PHY_527_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C840 0x00000000  //DDRSS_PHY_528_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C844 0x00000000  //DDRSS_PHY_529_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C848 0x00000000  //DDRSS_PHY_530_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C84C 0x00000100  //DDRSS_PHY_531_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C850 0x00000000  //DDRSS_PHY_532_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C854 0x00000000  //DDRSS_PHY_533_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C858 0x00000000  //DDRSS_PHY_534_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C85C 0x00000000  //DDRSS_PHY_535_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C860 0x00000000  //DDRSS_PHY_536_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C864 0x00000000  //DDRSS_PHY_537_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C868 0x00000000  //DDRSS_PHY_538_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C86C 0x00000000  //DDRSS_PHY_539_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C870 0x0A418820  //DDRSS_PHY_540_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C874 0x103F0000  //DDRSS_PHY_541_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C878 0x000F0100  //DDRSS_PHY_542_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C87C 0x0000000F  //DDRSS_PHY_543_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C880 0x020002CC  //DDRSS_PHY_544_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C884 0x00030000  //DDRSS_PHY_545_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C888 0x00000300  //DDRSS_PHY_546_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C88C 0x00000300  //DDRSS_PHY_547_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C890 0x00000300  //DDRSS_PHY_548_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C894 0x00000300  //DDRSS_PHY_549_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C898 0x00000300  //DDRSS_PHY_550_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C89C 0x42080010  //DDRSS_PHY_551_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A0 0x0000003E  //DDRSS_PHY_552_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A4 0x00000000  //DDRSS_PHY_553_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A8 0x00000000  //DDRSS_PHY_554_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC00 0x00000100  //DDRSS_PHY_768_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC04 0x00001000  //DDRSS_PHY_769_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC08 0x000A0000  //DDRSS_PHY_770_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC0C 0x00000000  //DDRSS_PHY_771_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC10 0x00000000  //DDRSS_PHY_772_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC14 0x00000100  //DDRSS_PHY_773_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC18 0x00000000  //DDRSS_PHY_774_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC1C 0x00000000  //DDRSS_PHY_775_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC20 0x00000000  //DDRSS_PHY_776_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC24 0x00000000  //DDRSS_PHY_777_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC28 0x00000000  //DDRSS_PHY_778_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC2C 0x00000000  //DDRSS_PHY_779_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC30 0x00000000  //DDRSS_PHY_780_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC34 0x00DCBA98  //DDRSS_PHY_781_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC38 0x00000000  //DDRSS_PHY_782_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC3C 0x00000000  //DDRSS_PHY_783_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC40 0x00000000  //DDRSS_PHY_784_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC44 0x00000000  //DDRSS_PHY_785_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC48 0x00000000  //DDRSS_PHY_786_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC4C 0x00000100  //DDRSS_PHY_787_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC50 0x00000000  //DDRSS_PHY_788_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC54 0x00000000  //DDRSS_PHY_789_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC58 0x00000000  //DDRSS_PHY_790_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC5C 0x00000000  //DDRSS_PHY_791_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC60 0x00000000  //DDRSS_PHY_792_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC64 0x00000000  //DDRSS_PHY_793_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC68 0x00000000  //DDRSS_PHY_794_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC6C 0x00000000  //DDRSS_PHY_795_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC70 0x16A4A0E6  //DDRSS_PHY_796_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC74 0x103F0000  //DDRSS_PHY_797_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC78 0x000F0000  //DDRSS_PHY_798_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC7C 0x0000000F  //DDRSS_PHY_799_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC80 0x020002CC  //DDRSS_PHY_800_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC84 0x00030000  //DDRSS_PHY_801_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC88 0x00000300  //DDRSS_PHY_802_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC8C 0x00000300  //DDRSS_PHY_803_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC90 0x00000300  //DDRSS_PHY_804_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC94 0x00000300  //DDRSS_PHY_805_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC98 0x00000300  //DDRSS_PHY_806_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC9C 0x42080010  //DDRSS_PHY_807_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA0 0x0000003E  //DDRSS_PHY_808_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA4 0x00000000  //DDRSS_PHY_809_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA8 0x00000000  //DDRSS_PHY_810_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D000 0x00000100  //DDRSS_PHY_1024_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D004 0x00001000  //DDRSS_PHY_1025_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D008 0x00090000  //DDRSS_PHY_1026_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D00C 0x00000000  //DDRSS_PHY_1027_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D010 0x00000000  //DDRSS_PHY_1028_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D014 0x00000100  //DDRSS_PHY_1029_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D018 0x00000000  //DDRSS_PHY_1030_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D01C 0x00000000  //DDRSS_PHY_1031_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D020 0x00000000  //DDRSS_PHY_1032_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D024 0x00000000  //DDRSS_PHY_1033_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D028 0x00000000  //DDRSS_PHY_1034_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D02C 0x00000000  //DDRSS_PHY_1035_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D030 0x00000000  //DDRSS_PHY_1036_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D034 0x00DCBA98  //DDRSS_PHY_1037_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D038 0x00000000  //DDRSS_PHY_1038_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D03C 0x00000000  //DDRSS_PHY_1039_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D040 0x00000000  //DDRSS_PHY_1040_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D044 0x00000000  //DDRSS_PHY_1041_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D048 0x00000000  //DDRSS_PHY_1042_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D04C 0x00000100  //DDRSS_PHY_1043_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D050 0x00000000  //DDRSS_PHY_1044_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D054 0x00000000  //DDRSS_PHY_1045_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D058 0x00000000  //DDRSS_PHY_1046_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D05C 0x00000000  //DDRSS_PHY_1047_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D060 0x00000000  //DDRSS_PHY_1048_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D064 0x00000000  //DDRSS_PHY_1049_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D068 0x00000000  //DDRSS_PHY_1050_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D06C 0x00000000  //DDRSS_PHY_1051_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D070 0x2307B9AC  //DDRSS_PHY_1052_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D074 0x10030000  //DDRSS_PHY_1053_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D078 0x000F0000  //DDRSS_PHY_1054_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D07C 0x0000000F  //DDRSS_PHY_1055_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D080 0x020002CC  //DDRSS_PHY_1056_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D084 0x00030000  //DDRSS_PHY_1057_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D088 0x00000300  //DDRSS_PHY_1058_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D08C 0x00000300  //DDRSS_PHY_1059_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D090 0x00000300  //DDRSS_PHY_1060_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D094 0x00000300  //DDRSS_PHY_1061_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D098 0x00000300  //DDRSS_PHY_1062_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D09C 0x42080010  //DDRSS_PHY_1063_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A0 0x0000003E  //DDRSS_PHY_1064_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A4 0x00000000  //DDRSS_PHY_1065_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A8 0x00000000  //DDRSS_PHY_1066_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D400 0x00000000  //DDRSS_PHY_1280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D404 0x00000100  //DDRSS_PHY_1281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D408 0x00000000  //DDRSS_PHY_1282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D40C 0x00000000  //DDRSS_PHY_1283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D410 0x00000000  //DDRSS_PHY_1284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D414 0x00000000  //DDRSS_PHY_1285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D418 0x00050000  //DDRSS_PHY_1286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D41C 0x04000100  //DDRSS_PHY_1287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D420 0x00000055  //DDRSS_PHY_1288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D424 0x00000000  //DDRSS_PHY_1289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D428 0x06800000  //DDRSS_PHY_1290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D42C 0x00000000  //DDRSS_PHY_1291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D430 0x00000000  //DDRSS_PHY_1292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D434 0x01002000  //DDRSS_PHY_1293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D438 0x00004001  //DDRSS_PHY_1294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D43C 0x00020028  //DDRSS_PHY_1295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D440 0x00010100  //DDRSS_PHY_1296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D444 0x00000001  //DDRSS_PHY_1297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D448 0x00000000  //DDRSS_PHY_1298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D44C 0x0F0F0E06  //DDRSS_PHY_1299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D450 0x00010101  //DDRSS_PHY_1300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D454 0x010F0004  //DDRSS_PHY_1301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D458 0x00000000  //DDRSS_PHY_1302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D45C 0x20125770  //DDRSS_PHY_1303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D460 0x00000064  //DDRSS_PHY_1304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D464 0x00000000  //DDRSS_PHY_1305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D468 0x00000000  //DDRSS_PHY_1306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D46C 0x01020103  //DDRSS_PHY_1307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D470 0x03020102  //DDRSS_PHY_1308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D474 0x03030303  //DDRSS_PHY_1309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D478 0x03030303  //DDRSS_PHY_1310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D47C 0x00040000  //DDRSS_PHY_1311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D480 0x00005201  //DDRSS_PHY_1312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D484 0x00000003  //DDRSS_PHY_1313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D488 0x00010000  //DDRSS_PHY_1314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D48C 0x00000000  //DDRSS_PHY_1315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D490 0x00000003  //DDRSS_PHY_1316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D494 0x00010000  //DDRSS_PHY_1317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D498 0x00000000  //DDRSS_PHY_1318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D49C 0x07070001  //DDRSS_PHY_1319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A0 0x00005400  //DDRSS_PHY_1320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A4 0x000040A2  //DDRSS_PHY_1321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A8 0x00038952  //DDRSS_PHY_1322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4AC 0x00018952  //DDRSS_PHY_1323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B0 0x00018952  //DDRSS_PHY_1324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B4 0x00017952  //DDRSS_PHY_1325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B8 0x00018952  //DDRSS_PHY_1326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4BC 0x00017952  //DDRSS_PHY_1327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C0 0x00018962  //DDRSS_PHY_1328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C4 0x00018962  //DDRSS_PHY_1329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C8 0x00017952  //DDRSS_PHY_1330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4CC 0x00017952  //DDRSS_PHY_1331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D0 0x00000000  //DDRSS_PHY_1332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D4 0x00000046  //DDRSS_PHY_1333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D8 0x00000400  //DDRSS_PHY_1334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4DC 0x00000008  //DDRSS_PHY_1335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E0 0x00817952  //DDRSS_PHY_1336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E4 0x00818962  //DDRSS_PHY_1337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E8 0x00179520  //DDRSS_PHY_1338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4EC 0x00189628  //DDRSS_PHY_1339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F0 0x00F7952F  //DDRSS_PHY_1340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F4 0x03F8962F  //DDRSS_PHY_1341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F8 0x00000000  //DDRSS_PHY_1342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4FC 0x00000000  //DDRSS_PHY_1343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D500 0xB3000000  //DDRSS_PHY_1344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D504 0x04102006  //DDRSS_PHY_1345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D508 0x00041020  //DDRSS_PHY_1346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D50C 0x01C98C98  //DDRSS_PHY_1347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D510 0x3F400000  //DDRSS_PHY_1348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D514 0x3F3F1F3F  //DDRSS_PHY_1349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D518 0x0000001F  //DDRSS_PHY_1350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D51C 0x00000000  //DDRSS_PHY_1351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D520 0x00000000  //DDRSS_PHY_1352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D524 0x00000000  //DDRSS_PHY_1353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D528 0x00000001  //DDRSS_PHY_1354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D52C 0x00000000  //DDRSS_PHY_1355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D530 0x00000000  //DDRSS_PHY_1356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D534 0x00000000  //DDRSS_PHY_1357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D538 0x00000000  //DDRSS_PHY_1358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D53C 0x76543210  //DDRSS_PHY_1359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D540 0x00000098  //DDRSS_PHY_1360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D544 0x00000000  //DDRSS_PHY_1361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D548 0x00000000  //DDRSS_PHY_1362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D54C 0x00000000  //DDRSS_PHY_1363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D550 0x00040700  //DDRSS_PHY_1364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D554 0x00000000  //DDRSS_PHY_1365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D558 0x00000000  //DDRSS_PHY_1366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D55C 0x00000000  //DDRSS_PHY_1367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D560 0x030F7102  //DDRSS_PHY_1368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D564 0x00000100  //DDRSS_PHY_1369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D568 0x00000000  //DDRSS_PHY_1370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D56C 0x0001F7C0  //DDRSS_PHY_1371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D570 0x00020002  //DDRSS_PHY_1372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D574 0x00000000  //DDRSS_PHY_1373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D578 0x00001142  //DDRSS_PHY_1374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D57C 0x03020400  //DDRSS_PHY_1375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D580 0x00000080  //DDRSS_PHY_1376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D584 0x03900390  //DDRSS_PHY_1377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D588 0x03900390  //DDRSS_PHY_1378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D58C 0x03900390  //DDRSS_PHY_1379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D590 0x03900390  //DDRSS_PHY_1380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D594 0x03900390  //DDRSS_PHY_1381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D598 0x03900390  //DDRSS_PHY_1382_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D59C 0x00000300  //DDRSS_PHY_1383_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A0 0x00000300  //DDRSS_PHY_1384_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A4 0x00000300  //DDRSS_PHY_1385_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A8 0x00000300  //DDRSS_PHY_1386_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5AC 0x31823FC7  //DDRSS_PHY_1387_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B0 0x00000000  //DDRSS_PHY_1388_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B4 0x0C000D3F  //DDRSS_PHY_1389_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B8 0x30000D3F  //DDRSS_PHY_1390_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5BC 0x300D3F11  //DDRSS_PHY_1391_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C0 0x01990000  //DDRSS_PHY_1392_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C4 0x000D3FCC  //DDRSS_PHY_1393_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C8 0x00000C11  //DDRSS_PHY_1394_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5CC 0x300D3F11  //DDRSS_PHY_1395_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D0 0x01990000  //DDRSS_PHY_1396_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D4 0x300C3F11  //DDRSS_PHY_1397_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D8 0x01990000  //DDRSS_PHY_1398_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5DC 0x300C3F11  //DDRSS_PHY_1399_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E0 0x01990000  //DDRSS_PHY_1400_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E4 0x300D3F11  //DDRSS_PHY_1401_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E8 0x01990000  //DDRSS_PHY_1402_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5EC 0x300D3F11  //DDRSS_PHY_1403_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F0 0x01990000  //DDRSS_PHY_1404_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F4 0x20040004  //DDRSS_PHY_1405_DATA

第二种现象：

为子板上电。

系统挂起导致 DDR 测试失败、连接到 JTAG、然后查看 DDR 空间、如下所示：

将0x00000000写入 DDR 地址0x8000000、然后从0x8000000读取0x00000000。读取和写入操作看起来是可纠正的。

将0xffffffff 写入 DDR 地址0x80000000、然后从0x80000000读取0x000000。

在 DDR 地址0x800000c8上写入0x00000000、然后从地址0x800000c8读取0x00000000。读取和写入操作看起来是可纠正的。

6.在 DDR 地址0x800000c8上写入0xffffffff、然后从地址0x800000c8中读取0x0000ff00。

7. 然后转储寄存器输出如下所示：

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
MAIN_Cortex_R5_0_0: GEL Output: Running from R5
MAIN_Cortex_R5_0_0: GEL Output: 
DDR not initialized with R5 connect.
Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR.
====
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308000 0x10460A01  //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308004 0x5D1AF3C3  //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308008 0x0171A610  //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30800C 0x40020A11  //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308010 0x00052006  //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308014 0x02050020  //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308018 0x03070101  //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30801C 0x000890B8  //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308020 0x00000000  //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308024 0x00000000  //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308028 0x00000000  //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30802C 0x000890B8  //DDRSS_CTL_11_DATA
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

MAIN_Cortex_R5_0_0: GEL Output: Running from R5
MAIN_Cortex_R5_0_0: GEL Output: 

DDR not initialized with R5 connect.

Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR.

====

MAIN_Cortex_R5_0_0: GEL Output: 0x0F308000 0x10460A01  //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308004 0x5D1AF3C3  //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308008 0x0171A610  //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30800C 0x40020A11  //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308010 0x00052006  //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308014 0x02050020  //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308018 0x03070101  //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30801C 0x000890B8  //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308020 0x00000000  //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308024 0x00000000  //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308028 0x00000000  //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30802C 0x000890B8  //DDRSS_CTL_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308030 0x00000000  //DDRSS_CTL_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308034 0x00000000  //DDRSS_CTL_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308038 0x00000000  //DDRSS_CTL_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30803C 0x000890B8  //DDRSS_CTL_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308040 0x00000000  //DDRSS_CTL_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308044 0x00000000  //DDRSS_CTL_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308048 0x00000000  //DDRSS_CTL_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30804C 0x01010100  //DDRSS_CTL_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308050 0x01000101  //DDRSS_CTL_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308054 0x01000110  //DDRSS_CTL_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308058 0x02010002  //DDRSS_CTL_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30805C 0x00027100  //DDRSS_CTL_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308060 0x00061A80  //DDRSS_CTL_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308064 0x02550255  //DDRSS_CTL_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308068 0x00000255  //DDRSS_CTL_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30806C 0x00000000  //DDRSS_CTL_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308070 0x00000000  //DDRSS_CTL_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308074 0x00000000  //DDRSS_CTL_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308078 0x00000000  //DDRSS_CTL_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30807C 0x00000000  //DDRSS_CTL_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308080 0x00000000  //DDRSS_CTL_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308084 0x00000000  //DDRSS_CTL_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308088 0x00000000  //DDRSS_CTL_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30808C 0x00000000  //DDRSS_CTL_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308090 0x00000000  //DDRSS_CTL_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308094 0x00000000  //DDRSS_CTL_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308098 0x0400091C  //DDRSS_CTL_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30809C 0x1C1C1C1C  //DDRSS_CTL_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A0 0x0400091C  //DDRSS_CTL_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A4 0x1C1C1C1C  //DDRSS_CTL_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A8 0x0400091C  //DDRSS_CTL_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080AC 0x1C1C1C1C  //DDRSS_CTL_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B0 0x05050404  //DDRSS_CTL_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B4 0x00002706  //DDRSS_CTL_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B8 0x0602001D  //DDRSS_CTL_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080BC 0x05001D0B  //DDRSS_CTL_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C0 0x00270605  //DDRSS_CTL_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C4 0x0602001D  //DDRSS_CTL_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C8 0x05001D0B  //DDRSS_CTL_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080CC 0x00270605  //DDRSS_CTL_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D0 0x0602001D  //DDRSS_CTL_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D4 0x07001D0B  //DDRSS_CTL_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D8 0x00180807  //DDRSS_CTL_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080DC 0x0400DB60  //DDRSS_CTL_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E0 0x07070009  //DDRSS_CTL_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E4 0x00001808  //DDRSS_CTL_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E8 0x0400DB60  //DDRSS_CTL_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080EC 0x07070009  //DDRSS_CTL_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F0 0x00001808  //DDRSS_CTL_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F4 0x0400DB60  //DDRSS_CTL_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F8 0x03000009  //DDRSS_CTL_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080FC 0x0D0C0002  //DDRSS_CTL_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308100 0x0D0C0D0C  //DDRSS_CTL_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308104 0x01010000  //DDRSS_CTL_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308108 0x03191919  //DDRSS_CTL_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30810C 0x0B0B0B0B  //DDRSS_CTL_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308110 0x00000B0B  //DDRSS_CTL_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308114 0x00000101  //DDRSS_CTL_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308118 0x00000000  //DDRSS_CTL_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30811C 0x01000000  //DDRSS_CTL_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308120 0x01180803  //DDRSS_CTL_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308124 0x00001860  //DDRSS_CTL_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308128 0x00000118  //DDRSS_CTL_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30812C 0x00001860  //DDRSS_CTL_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308130 0x00000118  //DDRSS_CTL_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308134 0x00001860  //DDRSS_CTL_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308138 0x00000005  //DDRSS_CTL_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30813C 0x00000000  //DDRSS_CTL_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308140 0x00000000  //DDRSS_CTL_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308144 0x00000000  //DDRSS_CTL_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308148 0x00000000  //DDRSS_CTL_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30814C 0x00000000  //DDRSS_CTL_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308150 0x00000000  //DDRSS_CTL_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308154 0x00000000  //DDRSS_CTL_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308158 0x00000000  //DDRSS_CTL_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30815C 0x00090009  //DDRSS_CTL_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308160 0x00000009  //DDRSS_CTL_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308164 0x00000000  //DDRSS_CTL_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308168 0x00000000  //DDRSS_CTL_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30816C 0x00000000  //DDRSS_CTL_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308170 0x00000000  //DDRSS_CTL_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308174 0x00000000  //DDRSS_CTL_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308178 0x00010001  //DDRSS_CTL_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30817C 0x00025501  //DDRSS_CTL_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308180 0x02550120  //DDRSS_CTL_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308184 0x02550120  //DDRSS_CTL_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308188 0x01200120  //DDRSS_CTL_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30818C 0x01200120  //DDRSS_CTL_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308190 0x00000000  //DDRSS_CTL_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308194 0x00000000  //DDRSS_CTL_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308198 0x00000000  //DDRSS_CTL_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30819C 0x00000000  //DDRSS_CTL_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A0 0x00000000  //DDRSS_CTL_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A4 0x00000000  //DDRSS_CTL_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A8 0x03010000  //DDRSS_CTL_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081AC 0x00010000  //DDRSS_CTL_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B0 0x00000000  //DDRSS_CTL_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B4 0x01000000  //DDRSS_CTL_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B8 0x80104002  //DDRSS_CTL_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081BC 0x00040003  //DDRSS_CTL_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C0 0x00040005  //DDRSS_CTL_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C4 0x00030000  //DDRSS_CTL_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C8 0x00050004  //DDRSS_CTL_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081CC 0x00000004  //DDRSS_CTL_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D0 0x00040003  //DDRSS_CTL_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D4 0x00040005  //DDRSS_CTL_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D8 0x00000000  //DDRSS_CTL_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081DC 0x00061800  //DDRSS_CTL_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E0 0x00061800  //DDRSS_CTL_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E4 0x00061800  //DDRSS_CTL_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E8 0x00061800  //DDRSS_CTL_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081EC 0x00061800  //DDRSS_CTL_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F0 0x00000000  //DDRSS_CTL_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F4 0x0000AAA0  //DDRSS_CTL_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F8 0x00061800  //DDRSS_CTL_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081FC 0x00061800  //DDRSS_CTL_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308200 0x00061800  //DDRSS_CTL_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308204 0x00061800  //DDRSS_CTL_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308208 0x00061800  //DDRSS_CTL_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30820C 0x00000000  //DDRSS_CTL_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308210 0x0000AAA0  //DDRSS_CTL_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308214 0x00061800  //DDRSS_CTL_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308218 0x00061800  //DDRSS_CTL_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30821C 0x00061800  //DDRSS_CTL_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308220 0x00061800  //DDRSS_CTL_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308224 0x00061800  //DDRSS_CTL_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308228 0x00000000  //DDRSS_CTL_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30822C 0x0000AAA0  //DDRSS_CTL_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308230 0x00000000  //DDRSS_CTL_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308234 0x00000000  //DDRSS_CTL_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308238 0x00000000  //DDRSS_CTL_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30823C 0x00000000  //DDRSS_CTL_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308240 0x00000000  //DDRSS_CTL_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308244 0x00000000  //DDRSS_CTL_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308248 0x00000000  //DDRSS_CTL_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30824C 0x00000000  //DDRSS_CTL_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308250 0x00000000  //DDRSS_CTL_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308254 0x00000000  //DDRSS_CTL_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308258 0x00000000  //DDRSS_CTL_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30825C 0x00000000  //DDRSS_CTL_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308260 0x00000000  //DDRSS_CTL_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308264 0x00000000  //DDRSS_CTL_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308268 0x00000000  //DDRSS_CTL_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30826C 0x00000000  //DDRSS_CTL_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308270 0x080C0000  //DDRSS_CTL_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308274 0x080C080C  //DDRSS_CTL_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308278 0x00000000  //DDRSS_CTL_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30827C 0x07010A09  //DDRSS_CTL_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308280 0x000E0A09  //DDRSS_CTL_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308284 0x010A0900  //DDRSS_CTL_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308288 0x0E0A0907  //DDRSS_CTL_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30828C 0x0A090000  //DDRSS_CTL_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308290 0x0A090701  //DDRSS_CTL_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308294 0x0000000E  //DDRSS_CTL_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308298 0x00040003  //DDRSS_CTL_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30829C 0x00004007  //DDRSS_CTL_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A0 0x00000000  //DDRSS_CTL_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A4 0x00000000  //DDRSS_CTL_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A8 0x00000000  //DDRSS_CTL_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082AC 0x00000000  //DDRSS_CTL_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B0 0x00000000  //DDRSS_CTL_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B4 0x00000000  //DDRSS_CTL_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B8 0x01000000  //DDRSS_CTL_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082BC 0x00000000  //DDRSS_CTL_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C0 0x00001500  //DDRSS_CTL_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C4 0x0000100E  //DDRSS_CTL_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C8 0x00000000  //DDRSS_CTL_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082CC 0x00000000  //DDRSS_CTL_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D0 0x00000001  //DDRSS_CTL_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D4 0x00000002  //DDRSS_CTL_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D8 0x00000C00  //DDRSS_CTL_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082DC 0x00001000  //DDRSS_CTL_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E0 0x00000C00  //DDRSS_CTL_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E4 0x00001000  //DDRSS_CTL_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E8 0x00000C00  //DDRSS_CTL_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082EC 0x00001000  //DDRSS_CTL_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F0 0x00000000  //DDRSS_CTL_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F4 0x00000000  //DDRSS_CTL_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F8 0x00000000  //DDRSS_CTL_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082FC 0x00000000  //DDRSS_CTL_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308300 0x00000000  //DDRSS_CTL_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308304 0x00000000  //DDRSS_CTL_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308308 0x00000000  //DDRSS_CTL_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30830C 0x00000000  //DDRSS_CTL_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308310 0x00000000  //DDRSS_CTL_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308314 0x00000000  //DDRSS_CTL_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308318 0x00000000  //DDRSS_CTL_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30831C 0x00000000  //DDRSS_CTL_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308320 0x00000000  //DDRSS_CTL_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308324 0x00000000  //DDRSS_CTL_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308328 0x00000000  //DDRSS_CTL_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30832C 0x00000000  //DDRSS_CTL_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308330 0x00042400  //DDRSS_CTL_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308334 0x00000301  //DDRSS_CTL_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308338 0x00000000  //DDRSS_CTL_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30833C 0x00000424  //DDRSS_CTL_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308340 0x00000301  //DDRSS_CTL_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308344 0x00000000  //DDRSS_CTL_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308348 0x00000424  //DDRSS_CTL_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30834C 0x00000301  //DDRSS_CTL_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308350 0x00000000  //DDRSS_CTL_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308354 0x00000424  //DDRSS_CTL_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308358 0x00000301  //DDRSS_CTL_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30835C 0x00000000  //DDRSS_CTL_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308360 0x00000424  //DDRSS_CTL_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308364 0x00000301  //DDRSS_CTL_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308368 0x00000000  //DDRSS_CTL_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30836C 0x00000424  //DDRSS_CTL_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308370 0x00000301  //DDRSS_CTL_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308374 0x00000000  //DDRSS_CTL_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308378 0x00000000  //DDRSS_CTL_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30837C 0x00000000  //DDRSS_CTL_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308380 0x00000000  //DDRSS_CTL_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308384 0x00000000  //DDRSS_CTL_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308388 0x00000000  //DDRSS_CTL_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30838C 0x00000000  //DDRSS_CTL_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308390 0x00000000  //DDRSS_CTL_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308394 0x00000000  //DDRSS_CTL_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308398 0x00000000  //DDRSS_CTL_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30839C 0x00000000  //DDRSS_CTL_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A0 0x00000000  //DDRSS_CTL_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A4 0x00000000  //DDRSS_CTL_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A8 0x00000000  //DDRSS_CTL_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083AC 0x00000000  //DDRSS_CTL_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B0 0x00001401  //DDRSS_CTL_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B4 0x00001401  //DDRSS_CTL_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B8 0x00001401  //DDRSS_CTL_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083BC 0x00001401  //DDRSS_CTL_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C0 0x00001401  //DDRSS_CTL_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C4 0x00001401  //DDRSS_CTL_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C8 0x00000493  //DDRSS_CTL_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083CC 0x00000493  //DDRSS_CTL_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D0 0x00000493  //DDRSS_CTL_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D4 0x00000493  //DDRSS_CTL_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D8 0x00000493  //DDRSS_CTL_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083DC 0x00000493  //DDRSS_CTL_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E0 0x00000000  //DDRSS_CTL_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E4 0x00000000  //DDRSS_CTL_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E8 0x00000000  //DDRSS_CTL_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083EC 0x00000000  //DDRSS_CTL_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F0 0x00000000  //DDRSS_CTL_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F4 0x00000000  //DDRSS_CTL_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F8 0x00000000  //DDRSS_CTL_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083FC 0x00000000  //DDRSS_CTL_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308400 0x00000000  //DDRSS_CTL_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308404 0x00000000  //DDRSS_CTL_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308408 0x00000000  //DDRSS_CTL_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30840C 0x00000000  //DDRSS_CTL_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308410 0x00000000  //DDRSS_CTL_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308414 0x00000000  //DDRSS_CTL_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308418 0x00000000  //DDRSS_CTL_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30841C 0x00000000  //DDRSS_CTL_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308420 0x00000000  //DDRSS_CTL_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308424 0x00000000  //DDRSS_CTL_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308428 0x00000000  //DDRSS_CTL_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30842C 0x00000000  //DDRSS_CTL_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308430 0x00000000  //DDRSS_CTL_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308434 0x00000000  //DDRSS_CTL_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308438 0x00000000  //DDRSS_CTL_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30843C 0x00000000  //DDRSS_CTL_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308440 0x00000000  //DDRSS_CTL_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308444 0x00000000  //DDRSS_CTL_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308448 0x00000000  //DDRSS_CTL_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30844C 0x00000000  //DDRSS_CTL_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308450 0x00000000  //DDRSS_CTL_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308454 0x00010000  //DDRSS_CTL_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308458 0x00000000  //DDRSS_CTL_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30845C 0x00000100  //DDRSS_CTL_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308460 0x00000000  //DDRSS_CTL_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308464 0x00000101  //DDRSS_CTL_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308468 0x00000000  //DDRSS_CTL_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30846C 0x00000000  //DDRSS_CTL_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308470 0x00000000  //DDRSS_CTL_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308474 0x00000000  //DDRSS_CTL_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308478 0x00000000  //DDRSS_CTL_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30847C 0x00000000  //DDRSS_CTL_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308480 0x00000000  //DDRSS_CTL_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308484 0x00000050  //DDRSS_CTL_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308488 0x0C181511  //DDRSS_CTL_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30848C 0x00000304  //DDRSS_CTL_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308490 0x00000000  //DDRSS_CTL_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308494 0x00000000  //DDRSS_CTL_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308498 0x00000000  //DDRSS_CTL_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30849C 0x00000000  //DDRSS_CTL_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A0 0x00000000  //DDRSS_CTL_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A4 0x00000000  //DDRSS_CTL_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A8 0x00000000  //DDRSS_CTL_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084AC 0x00000000  //DDRSS_CTL_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B0 0x00000000  //DDRSS_CTL_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B4 0x00000000  //DDRSS_CTL_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B8 0x00000000  //DDRSS_CTL_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084BC 0x00000000  //DDRSS_CTL_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C0 0x00000000  //DDRSS_CTL_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C4 0x00040000  //DDRSS_CTL_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C8 0x00800200  //DDRSS_CTL_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084CC 0x00000000  //DDRSS_CTL_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D0 0x02000400  //DDRSS_CTL_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D4 0x00000080  //DDRSS_CTL_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D8 0x00040000  //DDRSS_CTL_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084DC 0x00800200  //DDRSS_CTL_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E0 0x00000000  //DDRSS_CTL_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E4 0x00000000  //DDRSS_CTL_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E8 0x00000000  //DDRSS_CTL_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084EC 0x00000100  //DDRSS_CTL_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F0 0x01010000  //DDRSS_CTL_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F4 0x00000000  //DDRSS_CTL_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F8 0x3FFF0000  //DDRSS_CTL_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084FC 0x000FFF00  //DDRSS_CTL_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308500 0xFFFFFFFF  //DDRSS_CTL_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308504 0x000FFF00  //DDRSS_CTL_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308508 0x0A000000  //DDRSS_CTL_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30850C 0x0001FFFF  //DDRSS_CTL_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308510 0x01010101  //DDRSS_CTL_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308514 0x01010101  //DDRSS_CTL_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308518 0x00000118  //DDRSS_CTL_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30851C 0x00000C01  //DDRSS_CTL_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308520 0x00000000  //DDRSS_CTL_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308524 0x00000000  //DDRSS_CTL_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308528 0x00000000  //DDRSS_CTL_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30852C 0x01000000  //DDRSS_CTL_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308530 0x00000100  //DDRSS_CTL_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308534 0x00010000  //DDRSS_CTL_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308538 0x00000000  //DDRSS_CTL_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30853C 0x00000000  //DDRSS_CTL_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308540 0x00000000  //DDRSS_CTL_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308544 0x00000000  //DDRSS_CTL_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308548 0x00000000  //DDRSS_CTL_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30854C 0x00000000  //DDRSS_CTL_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308550 0x00000000  //DDRSS_CTL_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308554 0x00000000  //DDRSS_CTL_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308558 0x00000000  //DDRSS_CTL_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30855C 0x00000000  //DDRSS_CTL_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308560 0x00000000  //DDRSS_CTL_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308564 0x00000000  //DDRSS_CTL_345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308568 0x00000000  //DDRSS_CTL_346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30856C 0x00000000  //DDRSS_CTL_347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308570 0x00000000  //DDRSS_CTL_348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308574 0x00000000  //DDRSS_CTL_349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308578 0x00000000  //DDRSS_CTL_350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30857C 0x00000000  //DDRSS_CTL_351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308580 0x00000000  //DDRSS_CTL_352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308584 0x00000000  //DDRSS_CTL_353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308588 0x00000000  //DDRSS_CTL_354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30858C 0x00000000  //DDRSS_CTL_355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308590 0x00000000  //DDRSS_CTL_356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308594 0x00000000  //DDRSS_CTL_357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308598 0x00000000  //DDRSS_CTL_358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30859C 0x00000000  //DDRSS_CTL_359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A0 0x00000000  //DDRSS_CTL_360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A4 0x00000000  //DDRSS_CTL_361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A8 0x00000000  //DDRSS_CTL_362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085AC 0x00000000  //DDRSS_CTL_363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B0 0x00000000  //DDRSS_CTL_364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B4 0x00000066  //DDRSS_CTL_365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B8 0x00000066  //DDRSS_CTL_366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085BC 0x000000E0  //DDRSS_CTL_367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C0 0x00000000  //DDRSS_CTL_368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C4 0x00000000  //DDRSS_CTL_369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C8 0x0C000000  //DDRSS_CTL_370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085CC 0x060C0606  //DDRSS_CTL_371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D0 0x06060C06  //DDRSS_CTL_372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D4 0x00010101  //DDRSS_CTL_373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D8 0x02000000  //DDRSS_CTL_374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085DC 0x05020101  //DDRSS_CTL_375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E0 0x00000505  //DDRSS_CTL_376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E4 0x02020200  //DDRSS_CTL_377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E8 0x02020202  //DDRSS_CTL_378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085EC 0x02020202  //DDRSS_CTL_379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F0 0x02020202  //DDRSS_CTL_380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F4 0x00000000  //DDRSS_CTL_381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F8 0x00000000  //DDRSS_CTL_382_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085FC 0x04000100  //DDRSS_CTL_383_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308600 0x1E000304  //DDRSS_CTL_384_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308604 0x000030C0  //DDRSS_CTL_385_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308608 0x00000200  //DDRSS_CTL_386_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30860C 0x00000200  //DDRSS_CTL_387_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308610 0x00000200  //DDRSS_CTL_388_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308614 0x00000200  //DDRSS_CTL_389_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308618 0x0000DB60  //DDRSS_CTL_390_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30861C 0x0001E780  //DDRSS_CTL_391_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308620 0x0C0D0302  //DDRSS_CTL_392_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308624 0x001E090A  //DDRSS_CTL_393_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308628 0x000030C0  //DDRSS_CTL_394_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30862C 0x00000200  //DDRSS_CTL_395_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308630 0x00000200  //DDRSS_CTL_396_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308634 0x00000200  //DDRSS_CTL_397_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308638 0x00000200  //DDRSS_CTL_398_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30863C 0x0000DB60  //DDRSS_CTL_399_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308640 0x0001E780  //DDRSS_CTL_400_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308644 0x0C0D0302  //DDRSS_CTL_401_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308648 0x001E090A  //DDRSS_CTL_402_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30864C 0x000030C0  //DDRSS_CTL_403_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308650 0x00000200  //DDRSS_CTL_404_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308654 0x00000200  //DDRSS_CTL_405_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308658 0x00000200  //DDRSS_CTL_406_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30865C 0x00000200  //DDRSS_CTL_407_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308660 0x0000DB60  //DDRSS_CTL_408_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308664 0x0001E780  //DDRSS_CTL_409_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308668 0x0C0D0302  //DDRSS_CTL_410_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30866C 0x0000090A  //DDRSS_CTL_411_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308670 0x00000000  //DDRSS_CTL_412_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308674 0x0302000A  //DDRSS_CTL_413_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308678 0x01000500  //DDRSS_CTL_414_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30867C 0x01010001  //DDRSS_CTL_415_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308680 0x00010001  //DDRSS_CTL_416_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308684 0x01010001  //DDRSS_CTL_417_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308688 0x02010000  //DDRSS_CTL_418_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30868C 0x00000200  //DDRSS_CTL_419_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308690 0x02000201  //DDRSS_CTL_420_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308694 0x00000000  //DDRSS_CTL_421_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308698 0x00202020  //DDRSS_CTL_422_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A000 0x00000A01  //DDRSS_PI_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A004 0xAE8D79E2  //DDRSS_PI_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A008 0x0714B570  //DDRSS_PI_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A00C 0x01011387  //DDRSS_PI_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A010 0x00000001  //DDRSS_PI_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A014 0x00010064  //DDRSS_PI_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A018 0x00000000  //DDRSS_PI_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A01C 0x00000000  //DDRSS_PI_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A020 0x00000000  //DDRSS_PI_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A024 0x00001132  //DDRSS_PI_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A028 0x0000000F  //DDRSS_PI_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A02C 0x00000000  //DDRSS_PI_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A030 0x00000000  //DDRSS_PI_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A034 0x00010001  //DDRSS_PI_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A038 0x00000000  //DDRSS_PI_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A03C 0x00010001  //DDRSS_PI_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A040 0x00000005  //DDRSS_PI_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A044 0x00010000  //DDRSS_PI_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A048 0x00000000  //DDRSS_PI_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A04C 0x00000000  //DDRSS_PI_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A050 0x00000000  //DDRSS_PI_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A054 0x00000000  //DDRSS_PI_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A058 0x00000000  //DDRSS_PI_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A05C 0x00000000  //DDRSS_PI_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A060 0x280D0001  //DDRSS_PI_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A064 0x00000000  //DDRSS_PI_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A068 0x00010000  //DDRSS_PI_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A06C 0x00003200  //DDRSS_PI_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A070 0x00000000  //DDRSS_PI_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A074 0x00000000  //DDRSS_PI_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A078 0x00060602  //DDRSS_PI_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A07C 0x00000000  //DDRSS_PI_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A080 0x00000000  //DDRSS_PI_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A084 0x00000000  //DDRSS_PI_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A088 0x00000001  //DDRSS_PI_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A08C 0x00000055  //DDRSS_PI_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A090 0x000000AA  //DDRSS_PI_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A094 0x000000AD  //DDRSS_PI_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A098 0x00000052  //DDRSS_PI_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A09C 0x0000006A  //DDRSS_PI_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A0 0x00000095  //DDRSS_PI_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A4 0x00000095  //DDRSS_PI_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A8 0x000000AD  //DDRSS_PI_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0AC 0x00000000  //DDRSS_PI_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B0 0x00000000  //DDRSS_PI_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B4 0x00010100  //DDRSS_PI_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B8 0x00000014  //DDRSS_PI_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0BC 0x000007D0  //DDRSS_PI_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C0 0x00000300  //DDRSS_PI_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C4 0x00000000  //DDRSS_PI_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C8 0x00000000  //DDRSS_PI_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0CC 0x01000000  //DDRSS_PI_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D0 0x00010101  //DDRSS_PI_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D4 0x0100090C  //DDRSS_PI_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D8 0x00000000  //DDRSS_PI_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0DC 0x00010000  //DDRSS_PI_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E0 0x00000000  //DDRSS_PI_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E4 0x00000000  //DDRSS_PI_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E8 0x00000000  //DDRSS_PI_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0EC 0x00000000  //DDRSS_PI_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F0 0x00001400  //DDRSS_PI_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F4 0x00000000  //DDRSS_PI_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F8 0x01000000  //DDRSS_PI_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0FC 0x00000404  //DDRSS_PI_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A100 0x00000001  //DDRSS_PI_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A104 0x0001010E  //DDRSS_PI_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A108 0x02040100  //DDRSS_PI_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A10C 0x00010000  //DDRSS_PI_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A110 0x00000034  //DDRSS_PI_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A114 0x00000000  //DDRSS_PI_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A118 0x00000000  //DDRSS_PI_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A11C 0x00000000  //DDRSS_PI_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A120 0x00000000  //DDRSS_PI_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A124 0x00000000  //DDRSS_PI_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A128 0x00000000  //DDRSS_PI_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A12C 0x00000005  //DDRSS_PI_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A130 0x01000000  //DDRSS_PI_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A134 0x04000100  //DDRSS_PI_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A138 0x00020000  //DDRSS_PI_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A13C 0x00010002  //DDRSS_PI_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A140 0x00000001  //DDRSS_PI_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A144 0x00020001  //DDRSS_PI_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A148 0x00020002  //DDRSS_PI_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A14C 0x29C02000  //DDRSS_PI_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A150 0x00000000  //DDRSS_PI_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A154 0x00000000  //DDRSS_PI_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A158 0x00000000  //DDRSS_PI_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A15C 0x00000000  //DDRSS_PI_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A160 0x00000000  //DDRSS_PI_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A164 0x00000000  //DDRSS_PI_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A168 0x00000000  //DDRSS_PI_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A16C 0x00000300  //DDRSS_PI_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A170 0x0A090B0C  //DDRSS_PI_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A174 0x04060708  //DDRSS_PI_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A178 0x01000005  //DDRSS_PI_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A17C 0x00000800  //DDRSS_PI_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A180 0x00000000  //DDRSS_PI_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A184 0x00010008  //DDRSS_PI_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A188 0x00000000  //DDRSS_PI_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A18C 0x0000AA00  //DDRSS_PI_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A190 0x00000000  //DDRSS_PI_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A194 0x00010000  //DDRSS_PI_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A198 0x00000000  //DDRSS_PI_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A19C 0x00000000  //DDRSS_PI_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A0 0x00000000  //DDRSS_PI_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A4 0x00000000  //DDRSS_PI_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A8 0x00000000  //DDRSS_PI_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1AC 0x00000000  //DDRSS_PI_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B0 0x00000000  //DDRSS_PI_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B4 0x00000000  //DDRSS_PI_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B8 0x00000000  //DDRSS_PI_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1BC 0x00000000  //DDRSS_PI_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C0 0x00000000  //DDRSS_PI_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C4 0x00000000  //DDRSS_PI_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C8 0x00000000  //DDRSS_PI_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1CC 0x00000000  //DDRSS_PI_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D0 0x00000000  //DDRSS_PI_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D4 0x00000000  //DDRSS_PI_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D8 0x00000000  //DDRSS_PI_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1DC 0x00000000  //DDRSS_PI_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E0 0x00000000  //DDRSS_PI_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E4 0x00000000  //DDRSS_PI_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E8 0x00000000  //DDRSS_PI_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1EC 0x00000000  //DDRSS_PI_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F0 0x00000008  //DDRSS_PI_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F4 0x00000000  //DDRSS_PI_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F8 0x00000000  //DDRSS_PI_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1FC 0x00000000  //DDRSS_PI_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A200 0x00000000  //DDRSS_PI_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A204 0x00000000  //DDRSS_PI_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A208 0x00000000  //DDRSS_PI_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A20C 0x00000000  //DDRSS_PI_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A210 0x00000000  //DDRSS_PI_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A214 0x00010100  //DDRSS_PI_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A218 0x00000000  //DDRSS_PI_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A21C 0x00000000  //DDRSS_PI_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A220 0x00027100  //DDRSS_PI_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A224 0x00061A80  //DDRSS_PI_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A228 0x00000100  //DDRSS_PI_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A22C 0x00000000  //DDRSS_PI_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A230 0x00000000  //DDRSS_PI_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A234 0x00000000  //DDRSS_PI_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A238 0x00000000  //DDRSS_PI_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A23C 0x00000000  //DDRSS_PI_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A240 0x01000000  //DDRSS_PI_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A244 0xC1010003  //DDRSS_PI_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A248 0x02000101  //DDRSS_PI_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A24C 0x01030101  //DDRSS_PI_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A250 0x00010400  //DDRSS_PI_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A254 0x06000105  //DDRSS_PI_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A258 0x01070001  //DDRSS_PI_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A25C 0x00000000  //DDRSS_PI_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A260 0x00000000  //DDRSS_PI_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A264 0x00000001  //DDRSS_PI_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A268 0x00010000  //DDRSS_PI_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A26C 0x00000000  //DDRSS_PI_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A270 0x00000000  //DDRSS_PI_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A274 0x00000000  //DDRSS_PI_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A278 0x00000000  //DDRSS_PI_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A27C 0x00010000  //DDRSS_PI_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A280 0x00000004  //DDRSS_PI_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A284 0x00000000  //DDRSS_PI_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A288 0x00000000  //DDRSS_PI_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A28C 0x00000000  //DDRSS_PI_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A290 0x00007800  //DDRSS_PI_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A294 0x00780078  //DDRSS_PI_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A298 0x00141414  //DDRSS_PI_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A29C 0x0000003A  //DDRSS_PI_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A0 0x0000003A  //DDRSS_PI_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A4 0x0004003A  //DDRSS_PI_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A8 0x04000400  //DDRSS_PI_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2AC 0xC8040009  //DDRSS_PI_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B0 0x0400091C  //DDRSS_PI_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B4 0x00091CC8  //DDRSS_PI_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B8 0x001CC804  //DDRSS_PI_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2BC 0x00000118  //DDRSS_PI_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C0 0x00001860  //DDRSS_PI_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C4 0x00000118  //DDRSS_PI_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C8 0x00001860  //DDRSS_PI_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2CC 0x00000118  //DDRSS_PI_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D0 0x04001860  //DDRSS_PI_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D4 0x01010404  //DDRSS_PI_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D8 0x00001901  //DDRSS_PI_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2DC 0x00190019  //DDRSS_PI_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E0 0x010C010C  //DDRSS_PI_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E4 0x0000010C  //DDRSS_PI_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E8 0x00000000  //DDRSS_PI_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2EC 0x05000000  //DDRSS_PI_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F0 0x01010505  //DDRSS_PI_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F4 0x01010101  //DDRSS_PI_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F8 0x00181818  //DDRSS_PI_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2FC 0x00000000  //DDRSS_PI_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A300 0x00000000  //DDRSS_PI_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A304 0x0D000000  //DDRSS_PI_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A308 0x0A0A0D0D  //DDRSS_PI_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A30C 0x0303030A  //DDRSS_PI_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A310 0x00000000  //DDRSS_PI_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A314 0x00000000  //DDRSS_PI_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A318 0x00000000  //DDRSS_PI_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A31C 0x00000000  //DDRSS_PI_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A320 0x00000000  //DDRSS_PI_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A324 0x00000000  //DDRSS_PI_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A328 0x00000000  //DDRSS_PI_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A32C 0x00000000  //DDRSS_PI_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A330 0x00000000  //DDRSS_PI_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A334 0x00000000  //DDRSS_PI_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A338 0x00000000  //DDRSS_PI_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A33C 0x00000000  //DDRSS_PI_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A340 0x00000000  //DDRSS_PI_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A344 0x0D090000  //DDRSS_PI_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A348 0x0D09000D  //DDRSS_PI_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A34C 0x0D09000D  //DDRSS_PI_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A350 0x0000000D  //DDRSS_PI_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A354 0x00000000  //DDRSS_PI_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A358 0x00000000  //DDRSS_PI_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A35C 0x00000000  //DDRSS_PI_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A360 0x00000000  //DDRSS_PI_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A364 0x16000000  //DDRSS_PI_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A368 0x001600C8  //DDRSS_PI_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A36C 0x001600C8  //DDRSS_PI_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A370 0x010100C8  //DDRSS_PI_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A374 0x00001B01  //DDRSS_PI_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A378 0x1F0F0053  //DDRSS_PI_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A37C 0x05000001  //DDRSS_PI_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A380 0x001B0A0D  //DDRSS_PI_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A384 0x1F0F0053  //DDRSS_PI_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A388 0x05000001  //DDRSS_PI_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A38C 0x001B0A0D  //DDRSS_PI_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A390 0x1F0F0053  //DDRSS_PI_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A394 0x05000001  //DDRSS_PI_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A398 0x00010A0D  //DDRSS_PI_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A39C 0x0C0B0700  //DDRSS_PI_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A0 0x000D0605  //DDRSS_PI_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A4 0x0000C570  //DDRSS_PI_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A8 0x0000001D  //DDRSS_PI_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3AC 0x180A0800  //DDRSS_PI_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B0 0x0B071C1C  //DDRSS_PI_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B4 0x0D06050C  //DDRSS_PI_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B8 0x0000C570  //DDRSS_PI_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3BC 0x0000001D  //DDRSS_PI_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C0 0x180A0800  //DDRSS_PI_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C4 0x0B071C1C  //DDRSS_PI_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C8 0x0D06050C  //DDRSS_PI_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3CC 0x0000C570  //DDRSS_PI_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D0 0x0000001D  //DDRSS_PI_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D4 0x180A0800  //DDRSS_PI_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D8 0x00001C1C  //DDRSS_PI_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3DC 0x000030C0  //DDRSS_PI_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E0 0x0001E780  //DDRSS_PI_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E4 0x000030C0  //DDRSS_PI_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E8 0x0001E780  //DDRSS_PI_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3EC 0x000030C0  //DDRSS_PI_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F0 0x0001E780  //DDRSS_PI_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F4 0x02550255  //DDRSS_PI_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F8 0x03030255  //DDRSS_PI_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3FC 0x00025503  //DDRSS_PI_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A400 0x02550255  //DDRSS_PI_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A404 0x0C080C08  //DDRSS_PI_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A408 0x00000C08  //DDRSS_PI_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A40C 0x000890B8  //DDRSS_PI_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A410 0x00000000  //DDRSS_PI_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A414 0x00000000  //DDRSS_PI_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A418 0x00000000  //DDRSS_PI_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A41C 0x00000120  //DDRSS_PI_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A420 0x000890B8  //DDRSS_PI_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A424 0x00000000  //DDRSS_PI_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A428 0x00000000  //DDRSS_PI_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A42C 0x00000000  //DDRSS_PI_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A430 0x00000120  //DDRSS_PI_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A434 0x000890B8  //DDRSS_PI_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A438 0x00000000  //DDRSS_PI_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A43C 0x00000000  //DDRSS_PI_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A440 0x00000000  //DDRSS_PI_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A444 0x02000120  //DDRSS_PI_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A448 0x00000080  //DDRSS_PI_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A44C 0x00020000  //DDRSS_PI_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A450 0x00000080  //DDRSS_PI_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A454 0x00020000  //DDRSS_PI_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A458 0x00000080  //DDRSS_PI_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A45C 0x00000000  //DDRSS_PI_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A460 0x00000000  //DDRSS_PI_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A464 0x00040404  //DDRSS_PI_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A468 0x00000000  //DDRSS_PI_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A46C 0x02010102  //DDRSS_PI_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A470 0x67676767  //DDRSS_PI_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A474 0x00000202  //DDRSS_PI_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A478 0x00000000  //DDRSS_PI_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A47C 0x00000000  //DDRSS_PI_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A480 0x00000000  //DDRSS_PI_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A484 0x00000000  //DDRSS_PI_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A488 0x00000000  //DDRSS_PI_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A48C 0x0D100F00  //DDRSS_PI_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A490 0x0003020E  //DDRSS_PI_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A494 0x00000001  //DDRSS_PI_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A498 0x01000000  //DDRSS_PI_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A49C 0x00020201  //DDRSS_PI_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A0 0x00000000  //DDRSS_PI_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A4 0x00000424  //DDRSS_PI_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A8 0x00000301  //DDRSS_PI_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4AC 0x00000000  //DDRSS_PI_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B0 0x00000000  //DDRSS_PI_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B4 0x00000000  //DDRSS_PI_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B8 0x00001401  //DDRSS_PI_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4BC 0x00000493  //DDRSS_PI_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C0 0x00000000  //DDRSS_PI_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C4 0x00000424  //DDRSS_PI_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C8 0x00000301  //DDRSS_PI_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4CC 0x00000000  //DDRSS_PI_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D0 0x00000000  //DDRSS_PI_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D4 0x00000000  //DDRSS_PI_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D8 0x00001401  //DDRSS_PI_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4DC 0x00000493  //DDRSS_PI_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E0 0x00000000  //DDRSS_PI_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E4 0x00000424  //DDRSS_PI_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E8 0x00000301  //DDRSS_PI_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4EC 0x00000000  //DDRSS_PI_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F0 0x00000000  //DDRSS_PI_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F4 0x00000000  //DDRSS_PI_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F8 0x00001401  //DDRSS_PI_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4FC 0x00000493  //DDRSS_PI_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A500 0x00000000  //DDRSS_PI_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A504 0x00000424  //DDRSS_PI_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A508 0x00000424  //DDRSS_PI_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A50C 0x00000301  //DDRSS_PI_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A510 0x00000000  //DDRSS_PI_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A514 0x00000000  //DDRSS_PI_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A518 0x00000000  //DDRSS_PI_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A51C 0x00001401  //DDRSS_PI_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A520 0x00000493  //DDRSS_PI_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A524 0x00000000  //DDRSS_PI_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A528 0x00000424  //DDRSS_PI_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A52C 0x00000301  //DDRSS_PI_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A530 0x00000000  //DDRSS_PI_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A534 0x00000000  //DDRSS_PI_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A538 0x00000000  //DDRSS_PI_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A53C 0x00001401  //DDRSS_PI_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A540 0x00000493  //DDRSS_PI_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A544 0x00000000  //DDRSS_PI_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A548 0x00000424  //DDRSS_PI_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A54C 0x00000301  //DDRSS_PI_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A550 0x00000000  //DDRSS_PI_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A554 0x00000000  //DDRSS_PI_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A558 0x00000000  //DDRSS_PI_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A55C 0x00001401  //DDRSS_PI_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A560 0x00000493  //DDRSS_PI_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C000 0x04C00000  //DDRSS_PHY_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C004 0x00000000  //DDRSS_PHY_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C008 0x00000200  //DDRSS_PHY_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C00C 0x00000000  //DDRSS_PHY_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C010 0x00000000  //DDRSS_PHY_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C014 0x00000000  //DDRSS_PHY_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C018 0x00000000  //DDRSS_PHY_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C01C 0x00000000  //DDRSS_PHY_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C020 0x00000001  //DDRSS_PHY_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C024 0x00000000  //DDRSS_PHY_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C028 0x094C0000  //DDRSS_PHY_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C02C 0x010101FF  //DDRSS_PHY_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C030 0x00010000  //DDRSS_PHY_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C034 0x00C02004  //DDRSS_PHY_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C038 0x00CC0008  //DDRSS_PHY_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C03C 0x00660201  //DDRSS_PHY_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C040 0x00000000  //DDRSS_PHY_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C044 0x00000000  //DDRSS_PHY_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C048 0x00000000  //DDRSS_PHY_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C04C 0x0000AAAA  //DDRSS_PHY_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C050 0x00005555  //DDRSS_PHY_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C054 0x0000B5B5  //DDRSS_PHY_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C058 0x00004A4A  //DDRSS_PHY_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C05C 0x00005656  //DDRSS_PHY_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C060 0x0000A9A9  //DDRSS_PHY_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C064 0x0000B7B7  //DDRSS_PHY_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C068 0x00004848  //DDRSS_PHY_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C06C 0x00000000  //DDRSS_PHY_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C070 0x00000000  //DDRSS_PHY_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C074 0x08000000  //DDRSS_PHY_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C078 0x0F000008  //DDRSS_PHY_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C07C 0x00000F0F  //DDRSS_PHY_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C080 0x00E4E400  //DDRSS_PHY_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C084 0x00070820  //DDRSS_PHY_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C088 0x000C0020  //DDRSS_PHY_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C08C 0x00062000  //DDRSS_PHY_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C090 0x00000000  //DDRSS_PHY_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C094 0x55555555  //DDRSS_PHY_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C098 0xAAAAAAAA  //DDRSS_PHY_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C09C 0x55555555  //DDRSS_PHY_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A0 0xAAAAAAAA  //DDRSS_PHY_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A4 0x00005555  //DDRSS_PHY_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A8 0x01000100  //DDRSS_PHY_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0AC 0x00800180  //DDRSS_PHY_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B0 0x00000000  //DDRSS_PHY_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B4 0x00100000  //DDRSS_PHY_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B8 0x00000000  //DDRSS_PHY_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0BC 0x190A000C  //DDRSS_PHY_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C0 0x00000002  //DDRSS_PHY_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C4 0x00020400  //DDRSS_PHY_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C8 0x019C0190  //DDRSS_PHY_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0CC 0x00000FFF  //DDRSS_PHY_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D0 0x00000000  //DDRSS_PHY_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D4 0x024C0240  //DDRSS_PHY_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D8 0x00000031  //DDRSS_PHY_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0DC 0x0144003C  //DDRSS_PHY_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E0 0x00000000  //DDRSS_PHY_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E4 0x0C000000  //DDRSS_PHY_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E8 0x07FF0000  //DDRSS_PHY_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0EC 0x00000000  //DDRSS_PHY_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F0 0x00000000  //DDRSS_PHY_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F4 0x00000000  //DDRSS_PHY_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F8 0x00000000  //DDRSS_PHY_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0FC 0x00000000  //DDRSS_PHY_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C100 0x00000000  //DDRSS_PHY_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C104 0x00000004  //DDRSS_PHY_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C108 0x00000000  //DDRSS_PHY_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C10C 0x00000000  //DDRSS_PHY_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C110 0x00000000  //DDRSS_PHY_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C114 0x00000000  //DDRSS_PHY_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C118 0x00000000  //DDRSS_PHY_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C11C 0x00000000  //DDRSS_PHY_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C120 0x041F07FF  //DDRSS_PHY_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C124 0x00000000  //DDRSS_PHY_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C128 0x01CCB001  //DDRSS_PHY_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C12C 0x2000CCB0  //DDRSS_PHY_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C130 0x20000140  //DDRSS_PHY_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C134 0x07FF0200  //DDRSS_PHY_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C138 0x0000DD01  //DDRSS_PHY_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C13C 0x10100303  //DDRSS_PHY_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C140 0x10101010  //DDRSS_PHY_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C144 0x10101010  //DDRSS_PHY_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C148 0x00021010  //DDRSS_PHY_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C14C 0x00100010  //DDRSS_PHY_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C150 0x00100010  //DDRSS_PHY_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C154 0x00100010  //DDRSS_PHY_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C158 0x00100010  //DDRSS_PHY_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C15C 0x02020010  //DDRSS_PHY_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C160 0x51515041  //DDRSS_PHY_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C164 0x31804000  //DDRSS_PHY_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C168 0x04A00340  //DDRSS_PHY_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C16C 0x01008080  //DDRSS_PHY_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C170 0x04050001  //DDRSS_PHY_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C174 0x00000504  //DDRSS_PHY_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C178 0x42100010  //DDRSS_PHY_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C17C 0x010C053E  //DDRSS_PHY_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C180 0x000F0C14  //DDRSS_PHY_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C184 0x01000140  //DDRSS_PHY_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C188 0x007A0120  //DDRSS_PHY_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C18C 0x00000C00  //DDRSS_PHY_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C190 0x000001CC  //DDRSS_PHY_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C194 0x20100200  //DDRSS_PHY_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C198 0x00000005  //DDRSS_PHY_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C19C 0x76543210  //DDRSS_PHY_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A0 0x00000008  //DDRSS_PHY_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A4 0x02800280  //DDRSS_PHY_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A8 0x02800280  //DDRSS_PHY_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1AC 0x02800280  //DDRSS_PHY_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B0 0x02800280  //DDRSS_PHY_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B4 0x01960280  //DDRSS_PHY_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B8 0x0000C000  //DDRSS_PHY_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1BC 0x00BA00A8  //DDRSS_PHY_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C0 0x00BA00A8  //DDRSS_PHY_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C4 0x00C600A8  //DDRSS_PHY_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C8 0x00C600AE  //DDRSS_PHY_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1CC 0x00BA00A8  //DDRSS_PHY_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D0 0x00BA00A8  //DDRSS_PHY_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D4 0x00BA00A8  //DDRSS_PHY_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D8 0x00C000A8  //DDRSS_PHY_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1DC 0x014600A8  //DDRSS_PHY_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E0 0x01A00000  //DDRSS_PHY_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E4 0x00000000  //DDRSS_PHY_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E8 0x00000000  //DDRSS_PHY_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1EC 0x00080200  //DDRSS_PHY_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F0 0x00000000  //DDRSS_PHY_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F4 0x00000000  //DDRSS_PHY_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C400 0x04C00000  //DDRSS_PHY_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C404 0x00000000  //DDRSS_PHY_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C408 0x00000200  //DDRSS_PHY_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C40C 0x00000000  //DDRSS_PHY_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C410 0x00000000  //DDRSS_PHY_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C414 0x00000000  //DDRSS_PHY_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C418 0x00000000  //DDRSS_PHY_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C41C 0x00000000  //DDRSS_PHY_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C420 0x00000001  //DDRSS_PHY_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C424 0x00000000  //DDRSS_PHY_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C428 0x094C0000  //DDRSS_PHY_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C42C 0x010101FF  //DDRSS_PHY_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C430 0x00010000  //DDRSS_PHY_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C434 0x00C02C04  //DDRSS_PHY_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C438 0x00CC0008  //DDRSS_PHY_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C43C 0x00660201  //DDRSS_PHY_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C440 0x00000000  //DDRSS_PHY_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C444 0x00000000  //DDRSS_PHY_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C448 0x00000000  //DDRSS_PHY_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C44C 0x0000AAAA  //DDRSS_PHY_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C450 0x00005555  //DDRSS_PHY_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C454 0x0000B5B5  //DDRSS_PHY_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C458 0x00004A4A  //DDRSS_PHY_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C45C 0x00005656  //DDRSS_PHY_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C460 0x0000A9A9  //DDRSS_PHY_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C464 0x0000B7B7  //DDRSS_PHY_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C468 0x00004848  //DDRSS_PHY_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C46C 0x00000000  //DDRSS_PHY_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C470 0x00000000  //DDRSS_PHY_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C474 0x08000000  //DDRSS_PHY_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C478 0x0F000008  //DDRSS_PHY_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C47C 0x00000F0F  //DDRSS_PHY_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C480 0x00E4E400  //DDRSS_PHY_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C484 0x00070820  //DDRSS_PHY_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C488 0x000C0020  //DDRSS_PHY_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C48C 0x00062000  //DDRSS_PHY_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C490 0x00000000  //DDRSS_PHY_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C494 0x55555555  //DDRSS_PHY_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C498 0xAAAAAAAA  //DDRSS_PHY_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C49C 0x55555555  //DDRSS_PHY_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A0 0xAAAAAAAA  //DDRSS_PHY_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A4 0x00005555  //DDRSS_PHY_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A8 0x01000100  //DDRSS_PHY_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4AC 0x00800180  //DDRSS_PHY_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B0 0x00000000  //DDRSS_PHY_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B4 0x00100000  //DDRSS_PHY_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B8 0x00000000  //DDRSS_PHY_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4BC 0x1C0A000C  //DDRSS_PHY_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C0 0x0000000F  //DDRSS_PHY_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C4 0x00020700  //DDRSS_PHY_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C8 0x01A8019C  //DDRSS_PHY_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4CC 0x00000F5F  //DDRSS_PHY_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D0 0x00000000  //DDRSS_PHY_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D4 0x0258024C  //DDRSS_PHY_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D8 0x00000031  //DDRSS_PHY_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4DC 0x0138003C  //DDRSS_PHY_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E0 0x00000000  //DDRSS_PHY_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E4 0x0C000000  //DDRSS_PHY_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E8 0x07FF0000  //DDRSS_PHY_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4EC 0x00000000  //DDRSS_PHY_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F0 0x00000000  //DDRSS_PHY_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F4 0x00000000  //DDRSS_PHY_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F8 0x00000000  //DDRSS_PHY_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4FC 0x00000000  //DDRSS_PHY_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C500 0x00000000  //DDRSS_PHY_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C504 0x00000004  //DDRSS_PHY_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C508 0x00000000  //DDRSS_PHY_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C50C 0x00000000  //DDRSS_PHY_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C510 0x00000000  //DDRSS_PHY_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C514 0x00000000  //DDRSS_PHY_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C518 0x00000000  //DDRSS_PHY_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C51C 0x00000000  //DDRSS_PHY_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C520 0x041F07FF  //DDRSS_PHY_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C524 0x00000000  //DDRSS_PHY_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C528 0x01CCB001  //DDRSS_PHY_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C52C 0x2000CCB0  //DDRSS_PHY_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C530 0x20000140  //DDRSS_PHY_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C534 0x07FF0200  //DDRSS_PHY_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C538 0x0000DD01  //DDRSS_PHY_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C53C 0x10100303  //DDRSS_PHY_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C540 0x10101010  //DDRSS_PHY_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C544 0x10101010  //DDRSS_PHY_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C548 0x00021010  //DDRSS_PHY_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C54C 0x00100010  //DDRSS_PHY_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C550 0x00100010  //DDRSS_PHY_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C554 0x00100010  //DDRSS_PHY_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C558 0x00100010  //DDRSS_PHY_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C55C 0x02020010  //DDRSS_PHY_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C560 0x51515041  //DDRSS_PHY_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C564 0x31804000  //DDRSS_PHY_345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C568 0x04AC0340  //DDRSS_PHY_346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C56C 0x01008080  //DDRSS_PHY_347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C570 0x04050001  //DDRSS_PHY_348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C574 0x00000504  //DDRSS_PHY_349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C578 0x42100010  //DDRSS_PHY_350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C57C 0x010C053E  //DDRSS_PHY_351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C580 0x000F0C14  //DDRSS_PHY_352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C584 0x01000140  //DDRSS_PHY_353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C588 0x007A0120  //DDRSS_PHY_354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C58C 0x00000C00  //DDRSS_PHY_355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C590 0x000001CC  //DDRSS_PHY_356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C594 0x20100200  //DDRSS_PHY_357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C598 0x00000005  //DDRSS_PHY_358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C59C 0x76543210  //DDRSS_PHY_359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A0 0x00000008  //DDRSS_PHY_360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A4 0x02800280  //DDRSS_PHY_361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A8 0x02800280  //DDRSS_PHY_362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5AC 0x02800280  //DDRSS_PHY_363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B0 0x02800280  //DDRSS_PHY_364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B4 0x01A20280  //DDRSS_PHY_365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B8 0x0000BA02  //DDRSS_PHY_366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5BC 0x00B400A2  //DDRSS_PHY_367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C0 0x00AE00A2  //DDRSS_PHY_368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C4 0x00BA0096  //DDRSS_PHY_369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C8 0x00B400A8  //DDRSS_PHY_370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5CC 0x00B400A2  //DDRSS_PHY_371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D0 0x00B400A2  //DDRSS_PHY_372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D4 0x00B400A2  //DDRSS_PHY_373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D8 0x00BA00A2  //DDRSS_PHY_374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5DC 0x015200A2  //DDRSS_PHY_375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E0 0x01A00000  //DDRSS_PHY_376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E4 0x00000000  //DDRSS_PHY_377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E8 0x00000000  //DDRSS_PHY_378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5EC 0x00080200  //DDRSS_PHY_379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F0 0x00000000  //DDRSS_PHY_380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F4 0x00000000  //DDRSS_PHY_381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C800 0x00000100  //DDRSS_PHY_512_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C804 0x00001000  //DDRSS_PHY_513_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C808 0x000A0000  //DDRSS_PHY_514_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C80C 0x00000000  //DDRSS_PHY_515_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C810 0x00000000  //DDRSS_PHY_516_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C814 0x00000100  //DDRSS_PHY_517_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C818 0x00000000  //DDRSS_PHY_518_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C81C 0x00000000  //DDRSS_PHY_519_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C820 0x00000000  //DDRSS_PHY_520_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C824 0x00000000  //DDRSS_PHY_521_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C828 0x00000000  //DDRSS_PHY_522_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C82C 0x00000000  //DDRSS_PHY_523_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C830 0x00000000  //DDRSS_PHY_524_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C834 0x00DCBA98  //DDRSS_PHY_525_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C838 0x00000000  //DDRSS_PHY_526_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C83C 0x00000000  //DDRSS_PHY_527_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C840 0x00000000  //DDRSS_PHY_528_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C844 0x00000000  //DDRSS_PHY_529_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C848 0x00000000  //DDRSS_PHY_530_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C84C 0x00000100  //DDRSS_PHY_531_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C850 0x00000000  //DDRSS_PHY_532_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C854 0x00000000  //DDRSS_PHY_533_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C858 0x00000000  //DDRSS_PHY_534_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C85C 0x00000000  //DDRSS_PHY_535_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C860 0x00000000  //DDRSS_PHY_536_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C864 0x00000000  //DDRSS_PHY_537_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C868 0x00000000  //DDRSS_PHY_538_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C86C 0x00000000  //DDRSS_PHY_539_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C870 0x0A418820  //DDRSS_PHY_540_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C874 0x103F0000  //DDRSS_PHY_541_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C878 0x000F0100  //DDRSS_PHY_542_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C87C 0x0000000F  //DDRSS_PHY_543_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C880 0x020002CC  //DDRSS_PHY_544_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C884 0x00030000  //DDRSS_PHY_545_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C888 0x00000300  //DDRSS_PHY_546_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C88C 0x00000300  //DDRSS_PHY_547_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C890 0x00000300  //DDRSS_PHY_548_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C894 0x00000300  //DDRSS_PHY_549_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C898 0x00000300  //DDRSS_PHY_550_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C89C 0x42080010  //DDRSS_PHY_551_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A0 0x0000003E  //DDRSS_PHY_552_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A4 0x00000000  //DDRSS_PHY_553_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A8 0x00000000  //DDRSS_PHY_554_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC00 0x00000100  //DDRSS_PHY_768_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC04 0x00001000  //DDRSS_PHY_769_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC08 0x000A0000  //DDRSS_PHY_770_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC0C 0x00000000  //DDRSS_PHY_771_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC10 0x00000000  //DDRSS_PHY_772_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC14 0x00000100  //DDRSS_PHY_773_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC18 0x00000000  //DDRSS_PHY_774_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC1C 0x00000000  //DDRSS_PHY_775_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC20 0x00000000  //DDRSS_PHY_776_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC24 0x00000000  //DDRSS_PHY_777_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC28 0x00000000  //DDRSS_PHY_778_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC2C 0x00000000  //DDRSS_PHY_779_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC30 0x00000000  //DDRSS_PHY_780_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC34 0x00DCBA98  //DDRSS_PHY_781_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC38 0x00000000  //DDRSS_PHY_782_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC3C 0x00000000  //DDRSS_PHY_783_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC40 0x00000000  //DDRSS_PHY_784_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC44 0x00000000  //DDRSS_PHY_785_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC48 0x00000000  //DDRSS_PHY_786_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC4C 0x00000100  //DDRSS_PHY_787_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC50 0x00000000  //DDRSS_PHY_788_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC54 0x00000000  //DDRSS_PHY_789_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC58 0x00000000  //DDRSS_PHY_790_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC5C 0x00000000  //DDRSS_PHY_791_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC60 0x00000000  //DDRSS_PHY_792_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC64 0x00000000  //DDRSS_PHY_793_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC68 0x00000000  //DDRSS_PHY_794_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC6C 0x00000000  //DDRSS_PHY_795_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC70 0x16A4A0E6  //DDRSS_PHY_796_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC74 0x103F0000  //DDRSS_PHY_797_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC78 0x000F0000  //DDRSS_PHY_798_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC7C 0x0000000F  //DDRSS_PHY_799_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC80 0x020002CC  //DDRSS_PHY_800_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC84 0x00030000  //DDRSS_PHY_801_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC88 0x00000300  //DDRSS_PHY_802_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC8C 0x00000300  //DDRSS_PHY_803_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC90 0x00000300  //DDRSS_PHY_804_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC94 0x00000300  //DDRSS_PHY_805_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC98 0x00000300  //DDRSS_PHY_806_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC9C 0x42080010  //DDRSS_PHY_807_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA0 0x0000003E  //DDRSS_PHY_808_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA4 0x00000000  //DDRSS_PHY_809_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA8 0x00000000  //DDRSS_PHY_810_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D000 0x00000100  //DDRSS_PHY_1024_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D004 0x00001000  //DDRSS_PHY_1025_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D008 0x000A0000  //DDRSS_PHY_1026_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D00C 0x00000000  //DDRSS_PHY_1027_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D010 0x00000000  //DDRSS_PHY_1028_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D014 0x00000100  //DDRSS_PHY_1029_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D018 0x00000000  //DDRSS_PHY_1030_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D01C 0x00000000  //DDRSS_PHY_1031_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D020 0x00000000  //DDRSS_PHY_1032_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D024 0x00000000  //DDRSS_PHY_1033_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D028 0x00000000  //DDRSS_PHY_1034_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D02C 0x00000000  //DDRSS_PHY_1035_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D030 0x00000000  //DDRSS_PHY_1036_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D034 0x00DCBA98  //DDRSS_PHY_1037_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D038 0x00000000  //DDRSS_PHY_1038_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D03C 0x00000000  //DDRSS_PHY_1039_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D040 0x00000000  //DDRSS_PHY_1040_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D044 0x00000000  //DDRSS_PHY_1041_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D048 0x00000000  //DDRSS_PHY_1042_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D04C 0x00000100  //DDRSS_PHY_1043_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D050 0x00000000  //DDRSS_PHY_1044_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D054 0x00000000  //DDRSS_PHY_1045_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D058 0x00000000  //DDRSS_PHY_1046_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D05C 0x00000000  //DDRSS_PHY_1047_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D060 0x00000000  //DDRSS_PHY_1048_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D064 0x00000000  //DDRSS_PHY_1049_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D068 0x00000000  //DDRSS_PHY_1050_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D06C 0x00000000  //DDRSS_PHY_1051_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D070 0x2307B9AC  //DDRSS_PHY_1052_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D074 0x10030000  //DDRSS_PHY_1053_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D078 0x000F0000  //DDRSS_PHY_1054_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D07C 0x0000000F  //DDRSS_PHY_1055_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D080 0x020002CC  //DDRSS_PHY_1056_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D084 0x00030000  //DDRSS_PHY_1057_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D088 0x00000300  //DDRSS_PHY_1058_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D08C 0x00000300  //DDRSS_PHY_1059_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D090 0x00000300  //DDRSS_PHY_1060_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D094 0x00000300  //DDRSS_PHY_1061_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D098 0x00000300  //DDRSS_PHY_1062_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D09C 0x42080010  //DDRSS_PHY_1063_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A0 0x0000003E  //DDRSS_PHY_1064_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A4 0x00000000  //DDRSS_PHY_1065_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A8 0x00000000  //DDRSS_PHY_1066_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D400 0x00000000  //DDRSS_PHY_1280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D404 0x00000100  //DDRSS_PHY_1281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D408 0x00000000  //DDRSS_PHY_1282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D40C 0x00000000  //DDRSS_PHY_1283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D410 0x00000000  //DDRSS_PHY_1284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D414 0x00000000  //DDRSS_PHY_1285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D418 0x00050000  //DDRSS_PHY_1286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D41C 0x04000100  //DDRSS_PHY_1287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D420 0x00000055  //DDRSS_PHY_1288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D424 0x00000000  //DDRSS_PHY_1289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D428 0x06800000  //DDRSS_PHY_1290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D42C 0x00000000  //DDRSS_PHY_1291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D430 0x00000000  //DDRSS_PHY_1292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D434 0x01002000  //DDRSS_PHY_1293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D438 0x00004001  //DDRSS_PHY_1294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D43C 0x00020028  //DDRSS_PHY_1295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D440 0x00010100  //DDRSS_PHY_1296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D444 0x00000001  //DDRSS_PHY_1297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D448 0x00000000  //DDRSS_PHY_1298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D44C 0x0F0F0E06  //DDRSS_PHY_1299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D450 0x00010101  //DDRSS_PHY_1300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D454 0x010F0004  //DDRSS_PHY_1301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D458 0x00000000  //DDRSS_PHY_1302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D45C 0x20125770  //DDRSS_PHY_1303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D460 0x00000064  //DDRSS_PHY_1304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D464 0x00000000  //DDRSS_PHY_1305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D468 0x00000000  //DDRSS_PHY_1306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D46C 0x01020103  //DDRSS_PHY_1307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D470 0x03020102  //DDRSS_PHY_1308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D474 0x03030303  //DDRSS_PHY_1309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D478 0x03030303  //DDRSS_PHY_1310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D47C 0x00040000  //DDRSS_PHY_1311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D480 0x00005201  //DDRSS_PHY_1312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D484 0x00000003  //DDRSS_PHY_1313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D488 0x00010000  //DDRSS_PHY_1314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D48C 0x00000000  //DDRSS_PHY_1315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D490 0x00000003  //DDRSS_PHY_1316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D494 0x00010000  //DDRSS_PHY_1317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D498 0x00000000  //DDRSS_PHY_1318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D49C 0x07070001  //DDRSS_PHY_1319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A0 0x00005400  //DDRSS_PHY_1320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A4 0x000040A2  //DDRSS_PHY_1321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A8 0x00038952  //DDRSS_PHY_1322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4AC 0x00018952  //DDRSS_PHY_1323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B0 0x00018952  //DDRSS_PHY_1324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B4 0x00018952  //DDRSS_PHY_1325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B8 0x00017952  //DDRSS_PHY_1326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4BC 0x00018952  //DDRSS_PHY_1327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C0 0x00018962  //DDRSS_PHY_1328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C4 0x00018962  //DDRSS_PHY_1329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C8 0x00018952  //DDRSS_PHY_1330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4CC 0x00018952  //DDRSS_PHY_1331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D0 0x00000000  //DDRSS_PHY_1332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D4 0x00000046  //DDRSS_PHY_1333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D8 0x00000400  //DDRSS_PHY_1334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4DC 0x00000008  //DDRSS_PHY_1335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E0 0x00818952  //DDRSS_PHY_1336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E4 0x00818962  //DDRSS_PHY_1337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E8 0x00189520  //DDRSS_PHY_1338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4EC 0x00189628  //DDRSS_PHY_1339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F0 0x00F8952F  //DDRSS_PHY_1340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F4 0x03F8962F  //DDRSS_PHY_1341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F8 0x00000000  //DDRSS_PHY_1342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4FC 0x00000000  //DDRSS_PHY_1343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D500 0xB3000000  //DDRSS_PHY_1344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D504 0x04102006  //DDRSS_PHY_1345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D508 0x00041020  //DDRSS_PHY_1346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D50C 0x01C98C98  //DDRSS_PHY_1347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D510 0x3F400000  //DDRSS_PHY_1348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D514 0x3F3F1F3F  //DDRSS_PHY_1349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D518 0x0000001F  //DDRSS_PHY_1350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D51C 0x00000000  //DDRSS_PHY_1351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D520 0x00000000  //DDRSS_PHY_1352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D524 0x00000000  //DDRSS_PHY_1353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D528 0x00000001  //DDRSS_PHY_1354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D52C 0x00000000  //DDRSS_PHY_1355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D530 0x00000000  //DDRSS_PHY_1356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D534 0x00000000  //DDRSS_PHY_1357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D538 0x00000000  //DDRSS_PHY_1358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D53C 0x76543210  //DDRSS_PHY_1359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D540 0x00000098  //DDRSS_PHY_1360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D544 0x00000000  //DDRSS_PHY_1361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D548 0x00000000  //DDRSS_PHY_1362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D54C 0x00000000  //DDRSS_PHY_1363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D550 0x00040700  //DDRSS_PHY_1364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D554 0x00000000  //DDRSS_PHY_1365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D558 0x00000000  //DDRSS_PHY_1366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D55C 0x00000000  //DDRSS_PHY_1367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D560 0x030F7102  //DDRSS_PHY_1368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D564 0x00000100  //DDRSS_PHY_1369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D568 0x00000000  //DDRSS_PHY_1370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D56C 0x0001F7C0  //DDRSS_PHY_1371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D570 0x00020002  //DDRSS_PHY_1372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D574 0x00000000  //DDRSS_PHY_1373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D578 0x00001142  //DDRSS_PHY_1374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D57C 0x03020400  //DDRSS_PHY_1375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D580 0x00000080  //DDRSS_PHY_1376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D584 0x03900390  //DDRSS_PHY_1377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D588 0x03900390  //DDRSS_PHY_1378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D58C 0x03900390  //DDRSS_PHY_1379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D590 0x03900390  //DDRSS_PHY_1380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D594 0x03900390  //DDRSS_PHY_1381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D598 0x03900390  //DDRSS_PHY_1382_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D59C 0x00000300  //DDRSS_PHY_1383_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A0 0x00000300  //DDRSS_PHY_1384_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A4 0x00000300  //DDRSS_PHY_1385_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A8 0x00000300  //DDRSS_PHY_1386_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5AC 0x31823FC7  //DDRSS_PHY_1387_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B0 0x00000000  //DDRSS_PHY_1388_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B4 0x0C000D3F  //DDRSS_PHY_1389_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B8 0x30000D3F  //DDRSS_PHY_1390_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5BC 0x300D3F11  //DDRSS_PHY_1391_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C0 0x01990000  //DDRSS_PHY_1392_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C4 0x000D3FCC  //DDRSS_PHY_1393_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C8 0x00000C11  //DDRSS_PHY_1394_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5CC 0x300D3F11  //DDRSS_PHY_1395_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D0 0x01990000  //DDRSS_PHY_1396_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D4 0x300C3F11  //DDRSS_PHY_1397_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D8 0x01990000  //DDRSS_PHY_1398_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5DC 0x300C3F11  //DDRSS_PHY_1399_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E0 0x01990000  //DDRSS_PHY_1400_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E4 0x300D3F11  //DDRSS_PHY_1401_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E8 0x01990000  //DDRSS_PHY_1402_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5EC 0x300D3F11  //DDRSS_PHY_1403_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F0 0x01990000  //DDRSS_PHY_1404_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F4 0x20040004  //DDRSS_PHY_1405_DATA

谢谢、

jimin.Li

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

jimin、您好、感谢您提供寄存器转储。在出现故障的寄存器转储中、培训似乎没有完成、这就是数据不正确的原因。我不知道为什么培训此时失败、在您发送的 regdump 中不清楚。我需要考虑如何进行调试。

您能否为您的电路板提供布线长度报告？这应包括所有 DDR 信号的布线长度、包括 clk、addr/Ctrl 和数据总线。您是否还可以提供通过主板的 regdump 以及该主板的布线长度报告？

我不知道为什么培训未能成功完成、但希望通过这些附加信息、我可以找到一些线索。

此致、

James

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好 JJD、

感谢您的回复。很抱歉更新晚了。

子板和主板的 DDR 信号布线长度如下：

e2e.ti.com/.../DDR4TraceLength.xlsx

主板 regdump 如下所示：

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MAIN_Cortex_R5_0_0: GEL Output: Running from R5
MAIN_Cortex_R5_0_0: GEL Output: 
DDR not initialized with R5 connect.
Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR.
====
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308000 0x10460A01  //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308004 0x5D1AF3C3  //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308008 0x0171A610  //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30800C 0x40020A11  //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308010 0x00052006  //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308014 0x02050020  //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308018 0x03070101  //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30801C 0x000890B8  //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308020 0x00000000  //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308024 0x00000000  //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308028 0x00000000  //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30802C 0x000890B8  //DDRSS_CTL_11_DATA
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

MAIN_Cortex_R5_0_0: GEL Output: Running from R5
MAIN_Cortex_R5_0_0: GEL Output: 

DDR not initialized with R5 connect.

Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR.

====

MAIN_Cortex_R5_0_0: GEL Output: 0x0F308000 0x10460A01  //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308004 0x5D1AF3C3  //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308008 0x0171A610  //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30800C 0x40020A11  //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308010 0x00052006  //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308014 0x02050020  //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308018 0x03070101  //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30801C 0x000890B8  //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308020 0x00000000  //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308024 0x00000000  //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308028 0x00000000  //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30802C 0x000890B8  //DDRSS_CTL_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308030 0x00000000  //DDRSS_CTL_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308034 0x00000000  //DDRSS_CTL_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308038 0x00000000  //DDRSS_CTL_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30803C 0x000890B8  //DDRSS_CTL_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308040 0x00000000  //DDRSS_CTL_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308044 0x00000000  //DDRSS_CTL_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308048 0x00000000  //DDRSS_CTL_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30804C 0x01010100  //DDRSS_CTL_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308050 0x01000101  //DDRSS_CTL_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308054 0x01000110  //DDRSS_CTL_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308058 0x02010002  //DDRSS_CTL_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30805C 0x00027100  //DDRSS_CTL_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308060 0x00061A80  //DDRSS_CTL_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308064 0x02550255  //DDRSS_CTL_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308068 0x00000255  //DDRSS_CTL_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30806C 0x00000000  //DDRSS_CTL_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308070 0x00000000  //DDRSS_CTL_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308074 0x00000000  //DDRSS_CTL_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308078 0x00000000  //DDRSS_CTL_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30807C 0x00000000  //DDRSS_CTL_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308080 0x00000000  //DDRSS_CTL_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308084 0x00000000  //DDRSS_CTL_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308088 0x00000000  //DDRSS_CTL_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30808C 0x00000000  //DDRSS_CTL_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308090 0x00000000  //DDRSS_CTL_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308094 0x00000000  //DDRSS_CTL_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308098 0x0400091C  //DDRSS_CTL_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30809C 0x1C1C1C1C  //DDRSS_CTL_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A0 0x0400091C  //DDRSS_CTL_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A4 0x1C1C1C1C  //DDRSS_CTL_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A8 0x0400091C  //DDRSS_CTL_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080AC 0x1C1C1C1C  //DDRSS_CTL_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B0 0x05050404  //DDRSS_CTL_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B4 0x00002706  //DDRSS_CTL_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B8 0x0602001D  //DDRSS_CTL_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080BC 0x05001D0B  //DDRSS_CTL_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C0 0x00270605  //DDRSS_CTL_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C4 0x0602001D  //DDRSS_CTL_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C8 0x05001D0B  //DDRSS_CTL_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080CC 0x00270605  //DDRSS_CTL_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D0 0x0602001D  //DDRSS_CTL_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D4 0x07001D0B  //DDRSS_CTL_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D8 0x00180807  //DDRSS_CTL_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080DC 0x0400DB60  //DDRSS_CTL_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E0 0x07070009  //DDRSS_CTL_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E4 0x00001808  //DDRSS_CTL_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E8 0x0400DB60  //DDRSS_CTL_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080EC 0x07070009  //DDRSS_CTL_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F0 0x00001808  //DDRSS_CTL_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F4 0x0400DB60  //DDRSS_CTL_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F8 0x03000009  //DDRSS_CTL_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080FC 0x0D0C0002  //DDRSS_CTL_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308100 0x0D0C0D0C  //DDRSS_CTL_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308104 0x01010000  //DDRSS_CTL_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308108 0x03191919  //DDRSS_CTL_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30810C 0x0B0B0B0B  //DDRSS_CTL_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308110 0x00000B0B  //DDRSS_CTL_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308114 0x00000101  //DDRSS_CTL_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308118 0x00000000  //DDRSS_CTL_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30811C 0x01000000  //DDRSS_CTL_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308120 0x01180803  //DDRSS_CTL_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308124 0x00001860  //DDRSS_CTL_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308128 0x00000118  //DDRSS_CTL_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30812C 0x00001860  //DDRSS_CTL_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308130 0x00000118  //DDRSS_CTL_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308134 0x00001860  //DDRSS_CTL_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308138 0x00000005  //DDRSS_CTL_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30813C 0x00000000  //DDRSS_CTL_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308140 0x00000000  //DDRSS_CTL_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308144 0x00000000  //DDRSS_CTL_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308148 0x00000000  //DDRSS_CTL_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30814C 0x00000000  //DDRSS_CTL_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308150 0x00000000  //DDRSS_CTL_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308154 0x00000000  //DDRSS_CTL_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308158 0x00000000  //DDRSS_CTL_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30815C 0x00090009  //DDRSS_CTL_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308160 0x00000009  //DDRSS_CTL_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308164 0x00000000  //DDRSS_CTL_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308168 0x00000000  //DDRSS_CTL_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30816C 0x00000000  //DDRSS_CTL_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308170 0x00000000  //DDRSS_CTL_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308174 0x00000000  //DDRSS_CTL_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308178 0x00010001  //DDRSS_CTL_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30817C 0x00025501  //DDRSS_CTL_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308180 0x02550120  //DDRSS_CTL_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308184 0x02550120  //DDRSS_CTL_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308188 0x01200120  //DDRSS_CTL_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30818C 0x01200120  //DDRSS_CTL_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308190 0x00000000  //DDRSS_CTL_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308194 0x00000000  //DDRSS_CTL_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308198 0x00000000  //DDRSS_CTL_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30819C 0x00000000  //DDRSS_CTL_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A0 0x00000000  //DDRSS_CTL_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A4 0x00000000  //DDRSS_CTL_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A8 0x03010000  //DDRSS_CTL_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081AC 0x00010000  //DDRSS_CTL_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B0 0x00000000  //DDRSS_CTL_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B4 0x01000000  //DDRSS_CTL_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B8 0x80104002  //DDRSS_CTL_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081BC 0x00040003  //DDRSS_CTL_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C0 0x00040005  //DDRSS_CTL_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C4 0x00030000  //DDRSS_CTL_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C8 0x00050004  //DDRSS_CTL_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081CC 0x00000004  //DDRSS_CTL_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D0 0x00040003  //DDRSS_CTL_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D4 0x00040005  //DDRSS_CTL_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D8 0x00000000  //DDRSS_CTL_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081DC 0x00061800  //DDRSS_CTL_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E0 0x00061800  //DDRSS_CTL_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E4 0x00061800  //DDRSS_CTL_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E8 0x00061800  //DDRSS_CTL_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081EC 0x00061800  //DDRSS_CTL_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F0 0x00000000  //DDRSS_CTL_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F4 0x0000AAA0  //DDRSS_CTL_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F8 0x00061800  //DDRSS_CTL_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081FC 0x00061800  //DDRSS_CTL_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308200 0x00061800  //DDRSS_CTL_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308204 0x00061800  //DDRSS_CTL_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308208 0x00061800  //DDRSS_CTL_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30820C 0x00000000  //DDRSS_CTL_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308210 0x0000AAA0  //DDRSS_CTL_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308214 0x00061800  //DDRSS_CTL_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308218 0x00061800  //DDRSS_CTL_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30821C 0x00061800  //DDRSS_CTL_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308220 0x00061800  //DDRSS_CTL_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308224 0x00061800  //DDRSS_CTL_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308228 0x00000000  //DDRSS_CTL_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30822C 0x0000AAA0  //DDRSS_CTL_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308230 0x00000000  //DDRSS_CTL_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308234 0x00000000  //DDRSS_CTL_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308238 0x00000000  //DDRSS_CTL_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30823C 0x00000000  //DDRSS_CTL_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308240 0x00000000  //DDRSS_CTL_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308244 0x00000000  //DDRSS_CTL_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308248 0x00000000  //DDRSS_CTL_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30824C 0x00000000  //DDRSS_CTL_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308250 0x00000000  //DDRSS_CTL_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308254 0x00000000  //DDRSS_CTL_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308258 0x00000000  //DDRSS_CTL_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30825C 0x00000000  //DDRSS_CTL_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308260 0x00000000  //DDRSS_CTL_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308264 0x00000000  //DDRSS_CTL_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308268 0x00000000  //DDRSS_CTL_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30826C 0x00000000  //DDRSS_CTL_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308270 0x080C0000  //DDRSS_CTL_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308274 0x080C080C  //DDRSS_CTL_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308278 0x00000000  //DDRSS_CTL_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30827C 0x07010A09  //DDRSS_CTL_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308280 0x000E0A09  //DDRSS_CTL_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308284 0x010A0900  //DDRSS_CTL_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308288 0x0E0A0907  //DDRSS_CTL_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30828C 0x0A090000  //DDRSS_CTL_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308290 0x0A090701  //DDRSS_CTL_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308294 0x0000000E  //DDRSS_CTL_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308298 0x00040003  //DDRSS_CTL_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30829C 0x00004007  //DDRSS_CTL_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A0 0x00000000  //DDRSS_CTL_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A4 0x00000000  //DDRSS_CTL_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A8 0x00000000  //DDRSS_CTL_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082AC 0x00000000  //DDRSS_CTL_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B0 0x00000000  //DDRSS_CTL_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B4 0x00000000  //DDRSS_CTL_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B8 0x01000000  //DDRSS_CTL_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082BC 0x00000000  //DDRSS_CTL_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C0 0x00001500  //DDRSS_CTL_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C4 0x0000100E  //DDRSS_CTL_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C8 0x00000000  //DDRSS_CTL_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082CC 0x00000000  //DDRSS_CTL_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D0 0x00000001  //DDRSS_CTL_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D4 0x00000002  //DDRSS_CTL_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D8 0x00000C00  //DDRSS_CTL_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082DC 0x00001000  //DDRSS_CTL_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E0 0x00000C00  //DDRSS_CTL_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E4 0x00001000  //DDRSS_CTL_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E8 0x00000C00  //DDRSS_CTL_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082EC 0x00001000  //DDRSS_CTL_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F0 0x00000000  //DDRSS_CTL_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F4 0x00000000  //DDRSS_CTL_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F8 0x00000000  //DDRSS_CTL_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082FC 0x00000000  //DDRSS_CTL_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308300 0x00000000  //DDRSS_CTL_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308304 0x00000000  //DDRSS_CTL_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308308 0x00000000  //DDRSS_CTL_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30830C 0x00000000  //DDRSS_CTL_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308310 0x00000000  //DDRSS_CTL_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308314 0x00000000  //DDRSS_CTL_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308318 0x00000000  //DDRSS_CTL_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30831C 0x00000000  //DDRSS_CTL_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308320 0x00000000  //DDRSS_CTL_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308324 0x00000000  //DDRSS_CTL_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308328 0x00000000  //DDRSS_CTL_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30832C 0x00000000  //DDRSS_CTL_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308330 0x00042400  //DDRSS_CTL_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308334 0x00000301  //DDRSS_CTL_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308338 0x00000000  //DDRSS_CTL_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30833C 0x00000424  //DDRSS_CTL_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308340 0x00000301  //DDRSS_CTL_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308344 0x00000000  //DDRSS_CTL_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308348 0x00000424  //DDRSS_CTL_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30834C 0x00000301  //DDRSS_CTL_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308350 0x00000000  //DDRSS_CTL_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308354 0x00000424  //DDRSS_CTL_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308358 0x00000301  //DDRSS_CTL_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30835C 0x00000000  //DDRSS_CTL_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308360 0x00000424  //DDRSS_CTL_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308364 0x00000301  //DDRSS_CTL_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308368 0x00000000  //DDRSS_CTL_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30836C 0x00000424  //DDRSS_CTL_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308370 0x00000301  //DDRSS_CTL_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308374 0x00000000  //DDRSS_CTL_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308378 0x00000000  //DDRSS_CTL_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30837C 0x00000000  //DDRSS_CTL_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308380 0x00000000  //DDRSS_CTL_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308384 0x00000000  //DDRSS_CTL_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308388 0x00000000  //DDRSS_CTL_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30838C 0x00000000  //DDRSS_CTL_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308390 0x00000000  //DDRSS_CTL_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308394 0x00000000  //DDRSS_CTL_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308398 0x00000000  //DDRSS_CTL_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30839C 0x00000000  //DDRSS_CTL_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A0 0x00000000  //DDRSS_CTL_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A4 0x00000000  //DDRSS_CTL_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A8 0x00000000  //DDRSS_CTL_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083AC 0x00000000  //DDRSS_CTL_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B0 0x00001401  //DDRSS_CTL_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B4 0x00001401  //DDRSS_CTL_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B8 0x00001401  //DDRSS_CTL_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083BC 0x00001401  //DDRSS_CTL_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C0 0x00001401  //DDRSS_CTL_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C4 0x00001401  //DDRSS_CTL_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C8 0x00000493  //DDRSS_CTL_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083CC 0x00000493  //DDRSS_CTL_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D0 0x00000493  //DDRSS_CTL_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D4 0x00000493  //DDRSS_CTL_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D8 0x00000493  //DDRSS_CTL_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083DC 0x00000493  //DDRSS_CTL_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E0 0x00000000  //DDRSS_CTL_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E4 0x00000000  //DDRSS_CTL_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E8 0x00000000  //DDRSS_CTL_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083EC 0x00000000  //DDRSS_CTL_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F0 0x00000000  //DDRSS_CTL_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F4 0x00000000  //DDRSS_CTL_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F8 0x00000000  //DDRSS_CTL_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083FC 0x00000000  //DDRSS_CTL_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308400 0x00000000  //DDRSS_CTL_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308404 0x00000000  //DDRSS_CTL_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308408 0x00000000  //DDRSS_CTL_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30840C 0x00000000  //DDRSS_CTL_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308410 0x00000000  //DDRSS_CTL_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308414 0x00000000  //DDRSS_CTL_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308418 0x00000000  //DDRSS_CTL_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30841C 0x00000000  //DDRSS_CTL_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308420 0x00000000  //DDRSS_CTL_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308424 0x00000000  //DDRSS_CTL_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308428 0x00000000  //DDRSS_CTL_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30842C 0x00000000  //DDRSS_CTL_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308430 0x00000000  //DDRSS_CTL_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308434 0x00000000  //DDRSS_CTL_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308438 0x00000000  //DDRSS_CTL_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30843C 0x00000000  //DDRSS_CTL_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308440 0x00000000  //DDRSS_CTL_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308444 0x00000000  //DDRSS_CTL_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308448 0x00000000  //DDRSS_CTL_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30844C 0x00000000  //DDRSS_CTL_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308450 0x00000000  //DDRSS_CTL_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308454 0x00010000  //DDRSS_CTL_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308458 0x00000000  //DDRSS_CTL_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30845C 0x00000100  //DDRSS_CTL_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308460 0x00000000  //DDRSS_CTL_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308464 0x00000101  //DDRSS_CTL_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308468 0x00000000  //DDRSS_CTL_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30846C 0x00000000  //DDRSS_CTL_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308470 0x00000000  //DDRSS_CTL_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308474 0x00000000  //DDRSS_CTL_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308478 0x00000000  //DDRSS_CTL_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30847C 0x00000000  //DDRSS_CTL_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308480 0x00000000  //DDRSS_CTL_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308484 0x00000FFF  //DDRSS_CTL_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308488 0x0C181511  //DDRSS_CTL_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30848C 0x00000304  //DDRSS_CTL_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308490 0x00000000  //DDRSS_CTL_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308494 0x00000000  //DDRSS_CTL_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308498 0x00000000  //DDRSS_CTL_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30849C 0x00000000  //DDRSS_CTL_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A0 0x00000000  //DDRSS_CTL_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A4 0x00000000  //DDRSS_CTL_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A8 0x00000000  //DDRSS_CTL_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084AC 0x00000000  //DDRSS_CTL_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B0 0x00000000  //DDRSS_CTL_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B4 0x00000000  //DDRSS_CTL_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B8 0x00000000  //DDRSS_CTL_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084BC 0x00000000  //DDRSS_CTL_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C0 0x00000000  //DDRSS_CTL_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C4 0x00040000  //DDRSS_CTL_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C8 0x00800200  //DDRSS_CTL_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084CC 0x00000000  //DDRSS_CTL_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D0 0x02000400  //DDRSS_CTL_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D4 0x00000080  //DDRSS_CTL_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D8 0x00040000  //DDRSS_CTL_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084DC 0x00800200  //DDRSS_CTL_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E0 0x00000000  //DDRSS_CTL_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E4 0x00000000  //DDRSS_CTL_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E8 0x00000000  //DDRSS_CTL_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084EC 0x00000100  //DDRSS_CTL_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F0 0x01010000  //DDRSS_CTL_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F4 0x00000000  //DDRSS_CTL_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F8 0x3FFF0000  //DDRSS_CTL_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084FC 0x000FFF00  //DDRSS_CTL_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308500 0xFFFFFFFF  //DDRSS_CTL_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308504 0x000FFF00  //DDRSS_CTL_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308508 0x0A000000  //DDRSS_CTL_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30850C 0x0001FFFF  //DDRSS_CTL_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308510 0x01010101  //DDRSS_CTL_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308514 0x01010101  //DDRSS_CTL_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308518 0x00000118  //DDRSS_CTL_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30851C 0x00000C01  //DDRSS_CTL_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308520 0x00000000  //DDRSS_CTL_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308524 0x00000000  //DDRSS_CTL_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308528 0x00000000  //DDRSS_CTL_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30852C 0x01000000  //DDRSS_CTL_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308530 0x00000100  //DDRSS_CTL_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308534 0x00010000  //DDRSS_CTL_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308538 0x00000000  //DDRSS_CTL_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30853C 0x00000000  //DDRSS_CTL_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308540 0x00000000  //DDRSS_CTL_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308544 0x00000000  //DDRSS_CTL_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308548 0x00000000  //DDRSS_CTL_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30854C 0x00000000  //DDRSS_CTL_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308550 0x00000000  //DDRSS_CTL_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308554 0x00000000  //DDRSS_CTL_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308558 0x00000000  //DDRSS_CTL_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30855C 0x00000000  //DDRSS_CTL_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308560 0x00000000  //DDRSS_CTL_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308564 0x00000000  //DDRSS_CTL_345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308568 0x00000000  //DDRSS_CTL_346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30856C 0x00000000  //DDRSS_CTL_347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308570 0x00000000  //DDRSS_CTL_348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308574 0x00000000  //DDRSS_CTL_349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308578 0x00000000  //DDRSS_CTL_350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30857C 0x00000000  //DDRSS_CTL_351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308580 0x00000000  //DDRSS_CTL_352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308584 0x00000000  //DDRSS_CTL_353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308588 0x00000000  //DDRSS_CTL_354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30858C 0x00000000  //DDRSS_CTL_355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308590 0x00000000  //DDRSS_CTL_356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308594 0x00000000  //DDRSS_CTL_357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308598 0x00000000  //DDRSS_CTL_358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30859C 0x00000000  //DDRSS_CTL_359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A0 0x00000000  //DDRSS_CTL_360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A4 0x00000000  //DDRSS_CTL_361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A8 0x00000000  //DDRSS_CTL_362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085AC 0x00000000  //DDRSS_CTL_363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B0 0x00000000  //DDRSS_CTL_364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B4 0x00000000  //DDRSS_CTL_365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B8 0x7000A8FB  //DDRSS_CTL_366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085BC 0x01FFFE60  //DDRSS_CTL_367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C0 0x00000000  //DDRSS_CTL_368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C4 0x00000000  //DDRSS_CTL_369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C8 0x0C000000  //DDRSS_CTL_370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085CC 0x060C0606  //DDRSS_CTL_371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D0 0x06060C06  //DDRSS_CTL_372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D4 0x00010101  //DDRSS_CTL_373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D8 0x02000000  //DDRSS_CTL_374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085DC 0x05020101  //DDRSS_CTL_375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E0 0x00000505  //DDRSS_CTL_376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E4 0x02020200  //DDRSS_CTL_377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E8 0x02020202  //DDRSS_CTL_378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085EC 0x02020202  //DDRSS_CTL_379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F0 0x02020202  //DDRSS_CTL_380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F4 0x00000000  //DDRSS_CTL_381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F8 0x00000000  //DDRSS_CTL_382_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085FC 0x04000100  //DDRSS_CTL_383_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308600 0x1E000304  //DDRSS_CTL_384_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308604 0x000030C0  //DDRSS_CTL_385_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308608 0x00000200  //DDRSS_CTL_386_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30860C 0x00000200  //DDRSS_CTL_387_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308610 0x00000200  //DDRSS_CTL_388_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308614 0x00000200  //DDRSS_CTL_389_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308618 0x0000DB60  //DDRSS_CTL_390_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30861C 0x0001E780  //DDRSS_CTL_391_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308620 0x0C0D0302  //DDRSS_CTL_392_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308624 0x001E090A  //DDRSS_CTL_393_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308628 0x000030C0  //DDRSS_CTL_394_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30862C 0x00000200  //DDRSS_CTL_395_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308630 0x00000200  //DDRSS_CTL_396_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308634 0x00000200  //DDRSS_CTL_397_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308638 0x00000200  //DDRSS_CTL_398_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30863C 0x0000DB60  //DDRSS_CTL_399_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308640 0x0001E780  //DDRSS_CTL_400_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308644 0x0C0D0302  //DDRSS_CTL_401_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308648 0x001E090A  //DDRSS_CTL_402_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30864C 0x000030C0  //DDRSS_CTL_403_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308650 0x00000200  //DDRSS_CTL_404_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308654 0x00000200  //DDRSS_CTL_405_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308658 0x00000200  //DDRSS_CTL_406_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30865C 0x00000200  //DDRSS_CTL_407_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308660 0x0000DB60  //DDRSS_CTL_408_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308664 0x0001E780  //DDRSS_CTL_409_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308668 0x0C0D0302  //DDRSS_CTL_410_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30866C 0x0000090A  //DDRSS_CTL_411_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308670 0x00000000  //DDRSS_CTL_412_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308674 0x0302000A  //DDRSS_CTL_413_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308678 0x01000500  //DDRSS_CTL_414_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30867C 0x01010001  //DDRSS_CTL_415_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308680 0x00010001  //DDRSS_CTL_416_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308684 0x01010001  //DDRSS_CTL_417_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308688 0x02010000  //DDRSS_CTL_418_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30868C 0x00000200  //DDRSS_CTL_419_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308690 0x02000201  //DDRSS_CTL_420_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308694 0x00000000  //DDRSS_CTL_421_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308698 0x00202020  //DDRSS_CTL_422_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A000 0x00000A01  //DDRSS_PI_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A004 0xAE8D79E2  //DDRSS_PI_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A008 0x0714B570  //DDRSS_PI_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A00C 0x01011387  //DDRSS_PI_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A010 0x00000001  //DDRSS_PI_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A014 0x00010064  //DDRSS_PI_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A018 0x00000000  //DDRSS_PI_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A01C 0x00000000  //DDRSS_PI_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A020 0x00000000  //DDRSS_PI_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A024 0x00000000  //DDRSS_PI_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A028 0x00000000  //DDRSS_PI_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A02C 0x00000000  //DDRSS_PI_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A030 0x00000000  //DDRSS_PI_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A034 0x00010001  //DDRSS_PI_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A038 0x00000000  //DDRSS_PI_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A03C 0x00010001  //DDRSS_PI_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A040 0x00000005  //DDRSS_PI_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A044 0x00010000  //DDRSS_PI_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A048 0x00000000  //DDRSS_PI_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A04C 0x00000000  //DDRSS_PI_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A050 0x00000000  //DDRSS_PI_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A054 0x00000000  //DDRSS_PI_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A058 0x00000000  //DDRSS_PI_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A05C 0x00000000  //DDRSS_PI_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A060 0x280D0001  //DDRSS_PI_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A064 0x00000000  //DDRSS_PI_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A068 0x00010000  //DDRSS_PI_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A06C 0x00003200  //DDRSS_PI_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A070 0x00000000  //DDRSS_PI_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A074 0x00000000  //DDRSS_PI_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A078 0x00060602  //DDRSS_PI_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A07C 0x00000000  //DDRSS_PI_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A080 0x00000000  //DDRSS_PI_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A084 0x00000000  //DDRSS_PI_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A088 0x00000001  //DDRSS_PI_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A08C 0x00000055  //DDRSS_PI_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A090 0x000000AA  //DDRSS_PI_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A094 0x000000AD  //DDRSS_PI_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A098 0x00000052  //DDRSS_PI_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A09C 0x0000006A  //DDRSS_PI_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A0 0x00000095  //DDRSS_PI_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A4 0x00000095  //DDRSS_PI_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A8 0x000000AD  //DDRSS_PI_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0AC 0x00000000  //DDRSS_PI_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B0 0x00000000  //DDRSS_PI_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B4 0x00010100  //DDRSS_PI_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B8 0x00000014  //DDRSS_PI_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0BC 0x000007D0  //DDRSS_PI_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C0 0x00000300  //DDRSS_PI_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C4 0x00000000  //DDRSS_PI_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C8 0x00000000  //DDRSS_PI_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0CC 0x01000000  //DDRSS_PI_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D0 0x00010101  //DDRSS_PI_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D4 0x0100090C  //DDRSS_PI_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D8 0x00000000  //DDRSS_PI_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0DC 0x00010000  //DDRSS_PI_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E0 0x00000000  //DDRSS_PI_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E4 0x00000000  //DDRSS_PI_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E8 0x00000000  //DDRSS_PI_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0EC 0x00000000  //DDRSS_PI_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F0 0x00001400  //DDRSS_PI_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F4 0x00000000  //DDRSS_PI_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F8 0x01000000  //DDRSS_PI_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0FC 0x00000404  //DDRSS_PI_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A100 0x00000001  //DDRSS_PI_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A104 0x0001010E  //DDRSS_PI_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A108 0x02040100  //DDRSS_PI_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A10C 0x00010000  //DDRSS_PI_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A110 0x00000034  //DDRSS_PI_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A114 0x00000000  //DDRSS_PI_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A118 0x00000000  //DDRSS_PI_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A11C 0x00000000  //DDRSS_PI_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A120 0x00000000  //DDRSS_PI_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A124 0x00000000  //DDRSS_PI_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A128 0x00000000  //DDRSS_PI_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A12C 0x00000005  //DDRSS_PI_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A130 0x01000000  //DDRSS_PI_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A134 0x04000100  //DDRSS_PI_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A138 0x00020000  //DDRSS_PI_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A13C 0x00010002  //DDRSS_PI_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A140 0x00000001  //DDRSS_PI_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A144 0x00020001  //DDRSS_PI_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A148 0x00020002  //DDRSS_PI_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A14C 0x29C02000  //DDRSS_PI_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A150 0x00000000  //DDRSS_PI_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A154 0x00000000  //DDRSS_PI_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A158 0x00000000  //DDRSS_PI_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A15C 0x00000000  //DDRSS_PI_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A160 0x00000000  //DDRSS_PI_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A164 0x00000000  //DDRSS_PI_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A168 0x00000000  //DDRSS_PI_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A16C 0x00000300  //DDRSS_PI_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A170 0x0A090B0C  //DDRSS_PI_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A174 0x04060708  //DDRSS_PI_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A178 0x01000005  //DDRSS_PI_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A17C 0x00000800  //DDRSS_PI_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A180 0x00000000  //DDRSS_PI_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A184 0x00010008  //DDRSS_PI_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A188 0x00000000  //DDRSS_PI_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A18C 0x0000AA00  //DDRSS_PI_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A190 0x00000000  //DDRSS_PI_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A194 0x00010000  //DDRSS_PI_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A198 0x00000000  //DDRSS_PI_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A19C 0x00000000  //DDRSS_PI_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A0 0x00000000  //DDRSS_PI_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A4 0x00000000  //DDRSS_PI_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A8 0x00000000  //DDRSS_PI_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1AC 0x00000000  //DDRSS_PI_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B0 0x00000000  //DDRSS_PI_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B4 0x00000000  //DDRSS_PI_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B8 0x00000000  //DDRSS_PI_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1BC 0x00000000  //DDRSS_PI_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C0 0x00000000  //DDRSS_PI_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C4 0x00000000  //DDRSS_PI_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C8 0x00000000  //DDRSS_PI_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1CC 0x00000000  //DDRSS_PI_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D0 0x00000000  //DDRSS_PI_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D4 0x00000000  //DDRSS_PI_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D8 0x00000000  //DDRSS_PI_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1DC 0x00000000  //DDRSS_PI_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E0 0x00000000  //DDRSS_PI_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E4 0x00000000  //DDRSS_PI_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E8 0x00000000  //DDRSS_PI_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1EC 0x00000000  //DDRSS_PI_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F0 0x00000008  //DDRSS_PI_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F4 0x00000000  //DDRSS_PI_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F8 0x00000000  //DDRSS_PI_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1FC 0x00000000  //DDRSS_PI_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A200 0x00000000  //DDRSS_PI_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A204 0x00000000  //DDRSS_PI_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A208 0x00000000  //DDRSS_PI_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A20C 0x00000000  //DDRSS_PI_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A210 0x00000000  //DDRSS_PI_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A214 0x00010100  //DDRSS_PI_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A218 0x00000000  //DDRSS_PI_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A21C 0x00000000  //DDRSS_PI_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A220 0x00027100  //DDRSS_PI_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A224 0x00061A80  //DDRSS_PI_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A228 0x00000100  //DDRSS_PI_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A22C 0x00000000  //DDRSS_PI_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A230 0x00000000  //DDRSS_PI_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A234 0x00000000  //DDRSS_PI_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A238 0x00000000  //DDRSS_PI_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A23C 0x00000000  //DDRSS_PI_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A240 0x01000000  //DDRSS_PI_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A244 0xC1010003  //DDRSS_PI_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A248 0x02000101  //DDRSS_PI_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A24C 0x01030101  //DDRSS_PI_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A250 0x00010400  //DDRSS_PI_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A254 0x06000105  //DDRSS_PI_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A258 0x01070001  //DDRSS_PI_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A25C 0x00000000  //DDRSS_PI_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A260 0x00000000  //DDRSS_PI_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A264 0x00000001  //DDRSS_PI_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A268 0x00010000  //DDRSS_PI_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A26C 0x00000000  //DDRSS_PI_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A270 0x00000000  //DDRSS_PI_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A274 0x00000000  //DDRSS_PI_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A278 0x00000000  //DDRSS_PI_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A27C 0x00010000  //DDRSS_PI_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A280 0x00000004  //DDRSS_PI_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A284 0x00000000  //DDRSS_PI_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A288 0x00000000  //DDRSS_PI_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A28C 0x00000000  //DDRSS_PI_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A290 0x00007800  //DDRSS_PI_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A294 0x00780078  //DDRSS_PI_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A298 0x00141414  //DDRSS_PI_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A29C 0x0000003A  //DDRSS_PI_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A0 0x0000003A  //DDRSS_PI_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A4 0x0004003A  //DDRSS_PI_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A8 0x04000400  //DDRSS_PI_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2AC 0xC8040009  //DDRSS_PI_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B0 0x0400091C  //DDRSS_PI_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B4 0x00091CC8  //DDRSS_PI_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B8 0x001CC804  //DDRSS_PI_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2BC 0x00000118  //DDRSS_PI_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C0 0x00001860  //DDRSS_PI_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C4 0x00000118  //DDRSS_PI_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C8 0x00001860  //DDRSS_PI_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2CC 0x00000118  //DDRSS_PI_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D0 0x04001860  //DDRSS_PI_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D4 0x01010404  //DDRSS_PI_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D8 0x00001901  //DDRSS_PI_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2DC 0x00190019  //DDRSS_PI_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E0 0x010C010C  //DDRSS_PI_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E4 0x0000010C  //DDRSS_PI_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E8 0x00000000  //DDRSS_PI_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2EC 0x05000000  //DDRSS_PI_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F0 0x01010505  //DDRSS_PI_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F4 0x01010101  //DDRSS_PI_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F8 0x00181818  //DDRSS_PI_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2FC 0x00000000  //DDRSS_PI_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A300 0x00000000  //DDRSS_PI_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A304 0x0D000000  //DDRSS_PI_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A308 0x0A0A0D0D  //DDRSS_PI_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A30C 0x0303030A  //DDRSS_PI_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A310 0x00000000  //DDRSS_PI_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A314 0x00000000  //DDRSS_PI_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A318 0x00000000  //DDRSS_PI_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A31C 0x00000000  //DDRSS_PI_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A320 0x00000000  //DDRSS_PI_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A324 0x00000000  //DDRSS_PI_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A328 0x00000000  //DDRSS_PI_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A32C 0x00000000  //DDRSS_PI_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A330 0x00000000  //DDRSS_PI_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A334 0x00000000  //DDRSS_PI_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A338 0x00000000  //DDRSS_PI_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A33C 0x00000000  //DDRSS_PI_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A340 0x00000000  //DDRSS_PI_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A344 0x0D090000  //DDRSS_PI_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A348 0x0D09000D  //DDRSS_PI_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A34C 0x0D09000D  //DDRSS_PI_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A350 0x0000000D  //DDRSS_PI_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A354 0x00000000  //DDRSS_PI_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A358 0x00000000  //DDRSS_PI_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A35C 0x00000000  //DDRSS_PI_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A360 0x00000000  //DDRSS_PI_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A364 0x16000000  //DDRSS_PI_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A368 0x001600C8  //DDRSS_PI_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A36C 0x001600C8  //DDRSS_PI_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A370 0x010100C8  //DDRSS_PI_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A374 0x00001B01  //DDRSS_PI_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A378 0x1F0F0053  //DDRSS_PI_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A37C 0x05000001  //DDRSS_PI_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A380 0x001B0A0D  //DDRSS_PI_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A384 0x1F0F0053  //DDRSS_PI_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A388 0x05000001  //DDRSS_PI_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A38C 0x001B0A0D  //DDRSS_PI_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A390 0x1F0F0053  //DDRSS_PI_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A394 0x05000001  //DDRSS_PI_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A398 0x00010A0D  //DDRSS_PI_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A39C 0x0C0B0700  //DDRSS_PI_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A0 0x000D0605  //DDRSS_PI_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A4 0x0000C570  //DDRSS_PI_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A8 0x0000001D  //DDRSS_PI_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3AC 0x180A0800  //DDRSS_PI_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B0 0x0B071C1C  //DDRSS_PI_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B4 0x0D06050C  //DDRSS_PI_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B8 0x0000C570  //DDRSS_PI_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3BC 0x0000001D  //DDRSS_PI_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C0 0x180A0800  //DDRSS_PI_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C4 0x0B071C1C  //DDRSS_PI_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C8 0x0D06050C  //DDRSS_PI_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3CC 0x0000C570  //DDRSS_PI_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D0 0x0000001D  //DDRSS_PI_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D4 0x180A0800  //DDRSS_PI_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D8 0x00001C1C  //DDRSS_PI_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3DC 0x000030C0  //DDRSS_PI_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E0 0x0001E780  //DDRSS_PI_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E4 0x000030C0  //DDRSS_PI_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E8 0x0001E780  //DDRSS_PI_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3EC 0x000030C0  //DDRSS_PI_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F0 0x0001E780  //DDRSS_PI_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F4 0x02550255  //DDRSS_PI_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F8 0x03030255  //DDRSS_PI_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3FC 0x00025503  //DDRSS_PI_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A400 0x02550255  //DDRSS_PI_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A404 0x0C080C08  //DDRSS_PI_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A408 0x00000C08  //DDRSS_PI_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A40C 0x000890B8  //DDRSS_PI_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A410 0x00000000  //DDRSS_PI_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A414 0x00000000  //DDRSS_PI_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A418 0x00000000  //DDRSS_PI_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A41C 0x00000120  //DDRSS_PI_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A420 0x000890B8  //DDRSS_PI_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A424 0x00000000  //DDRSS_PI_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A428 0x00000000  //DDRSS_PI_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A42C 0x00000000  //DDRSS_PI_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A430 0x00000120  //DDRSS_PI_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A434 0x000890B8  //DDRSS_PI_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A438 0x00000000  //DDRSS_PI_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A43C 0x00000000  //DDRSS_PI_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A440 0x00000000  //DDRSS_PI_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A444 0x02000120  //DDRSS_PI_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A448 0x00000080  //DDRSS_PI_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A44C 0x00020000  //DDRSS_PI_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A450 0x00000080  //DDRSS_PI_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A454 0x00020000  //DDRSS_PI_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A458 0x00000080  //DDRSS_PI_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A45C 0x00000000  //DDRSS_PI_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A460 0x00000000  //DDRSS_PI_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A464 0x00040404  //DDRSS_PI_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A468 0x00000000  //DDRSS_PI_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A46C 0x02010102  //DDRSS_PI_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A470 0x67676767  //DDRSS_PI_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A474 0x00000202  //DDRSS_PI_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A478 0x00000000  //DDRSS_PI_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A47C 0x00000000  //DDRSS_PI_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A480 0x00000000  //DDRSS_PI_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A484 0x00000000  //DDRSS_PI_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A488 0x00000000  //DDRSS_PI_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A48C 0x0D100F00  //DDRSS_PI_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A490 0x0003020E  //DDRSS_PI_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A494 0x00000001  //DDRSS_PI_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A498 0x01000000  //DDRSS_PI_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A49C 0x00020201  //DDRSS_PI_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A0 0x00000000  //DDRSS_PI_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A4 0x00000424  //DDRSS_PI_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A8 0x00000301  //DDRSS_PI_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4AC 0x00000000  //DDRSS_PI_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B0 0x00000000  //DDRSS_PI_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B4 0x00000000  //DDRSS_PI_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B8 0x00001401  //DDRSS_PI_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4BC 0x00000493  //DDRSS_PI_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C0 0x00000000  //DDRSS_PI_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C4 0x00000424  //DDRSS_PI_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C8 0x00000301  //DDRSS_PI_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4CC 0x00000000  //DDRSS_PI_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D0 0x00000000  //DDRSS_PI_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D4 0x00000000  //DDRSS_PI_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D8 0x00001401  //DDRSS_PI_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4DC 0x00000493  //DDRSS_PI_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E0 0x00000000  //DDRSS_PI_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E4 0x00000424  //DDRSS_PI_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E8 0x00000301  //DDRSS_PI_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4EC 0x00000000  //DDRSS_PI_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F0 0x00000000  //DDRSS_PI_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F4 0x00000000  //DDRSS_PI_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F8 0x00001401  //DDRSS_PI_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4FC 0x00000493  //DDRSS_PI_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A500 0x00000000  //DDRSS_PI_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A504 0x00000424  //DDRSS_PI_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A508 0x00000301  //DDRSS_PI_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A50C 0x00000000  //DDRSS_PI_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A510 0x00000000  //DDRSS_PI_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A514 0x00000000  //DDRSS_PI_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A518 0x00001401  //DDRSS_PI_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A51C 0x00000493  //DDRSS_PI_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A520 0x00000000  //DDRSS_PI_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A524 0x00000424  //DDRSS_PI_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A528 0x00000301  //DDRSS_PI_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A52C 0x00000000  //DDRSS_PI_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A530 0x00000000  //DDRSS_PI_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A534 0x00000000  //DDRSS_PI_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A538 0x00001401  //DDRSS_PI_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A53C 0x00000493  //DDRSS_PI_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A540 0x00000000  //DDRSS_PI_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A544 0x00000424  //DDRSS_PI_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A548 0x00000301  //DDRSS_PI_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A54C 0x00000000  //DDRSS_PI_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A550 0x00000000  //DDRSS_PI_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A554 0x00000000  //DDRSS_PI_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A558 0x00001401  //DDRSS_PI_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A55C 0x00000493  //DDRSS_PI_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A560 0x00000000  //DDRSS_PI_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C000 0x04C00000  //DDRSS_PHY_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C004 0x00000000  //DDRSS_PHY_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C008 0x00000200  //DDRSS_PHY_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C00C 0x00000000  //DDRSS_PHY_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C010 0x00000000  //DDRSS_PHY_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C014 0x00000000  //DDRSS_PHY_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C018 0x00000000  //DDRSS_PHY_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C01C 0x00000000  //DDRSS_PHY_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C020 0x00000001  //DDRSS_PHY_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C024 0x00000000  //DDRSS_PHY_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C028 0x094C0000  //DDRSS_PHY_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C02C 0x010101FF  //DDRSS_PHY_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C030 0x00010000  //DDRSS_PHY_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C034 0x00C02004  //DDRSS_PHY_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C038 0x00CC0008  //DDRSS_PHY_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C03C 0x00660201  //DDRSS_PHY_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C040 0x00000000  //DDRSS_PHY_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C044 0x00000000  //DDRSS_PHY_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C048 0x00000000  //DDRSS_PHY_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C04C 0x0000AAAA  //DDRSS_PHY_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C050 0x00005555  //DDRSS_PHY_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C054 0x0000B5B5  //DDRSS_PHY_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C058 0x00004A4A  //DDRSS_PHY_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C05C 0x00005656  //DDRSS_PHY_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C060 0x0000A9A9  //DDRSS_PHY_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C064 0x0000B7B7  //DDRSS_PHY_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C068 0x00004848  //DDRSS_PHY_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C06C 0x00000000  //DDRSS_PHY_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C070 0x00000000  //DDRSS_PHY_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C074 0x08000000  //DDRSS_PHY_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C078 0x0F000008  //DDRSS_PHY_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C07C 0x00000F0F  //DDRSS_PHY_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C080 0x00E4E400  //DDRSS_PHY_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C084 0x00070820  //DDRSS_PHY_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C088 0x000C0020  //DDRSS_PHY_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C08C 0x00062000  //DDRSS_PHY_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C090 0x00000000  //DDRSS_PHY_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C094 0x55555555  //DDRSS_PHY_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C098 0xAAAAAAAA  //DDRSS_PHY_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C09C 0x55555555  //DDRSS_PHY_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A0 0xAAAAAAAA  //DDRSS_PHY_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A4 0x00005555  //DDRSS_PHY_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A8 0x01000100  //DDRSS_PHY_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0AC 0x00800180  //DDRSS_PHY_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B0 0x00000000  //DDRSS_PHY_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B4 0x00100000  //DDRSS_PHY_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B8 0x00000000  //DDRSS_PHY_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0BC 0x1E080010  //DDRSS_PHY_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C0 0x00000012  //DDRSS_PHY_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C4 0x00020400  //DDRSS_PHY_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C8 0x01D801C0  //DDRSS_PHY_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0CC 0x00000F00  //DDRSS_PHY_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D0 0x00000000  //DDRSS_PHY_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D4 0x02940288  //DDRSS_PHY_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D8 0x00000030  //DDRSS_PHY_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0DC 0x0120003C  //DDRSS_PHY_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E0 0x00000000  //DDRSS_PHY_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E4 0x0C000000  //DDRSS_PHY_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E8 0x07FF0000  //DDRSS_PHY_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0EC 0x00000000  //DDRSS_PHY_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F0 0x00000000  //DDRSS_PHY_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F4 0x00000000  //DDRSS_PHY_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F8 0x00000000  //DDRSS_PHY_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0FC 0x00000000  //DDRSS_PHY_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C100 0x00000000  //DDRSS_PHY_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C104 0x00000004  //DDRSS_PHY_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C108 0x00000000  //DDRSS_PHY_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C10C 0x00000000  //DDRSS_PHY_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C110 0x00000000  //DDRSS_PHY_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C114 0x00000000  //DDRSS_PHY_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C118 0x00000000  //DDRSS_PHY_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C11C 0x00000000  //DDRSS_PHY_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C120 0x041F07FF  //DDRSS_PHY_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C124 0x00000000  //DDRSS_PHY_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C128 0x01CCB001  //DDRSS_PHY_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C12C 0x2000CCB0  //DDRSS_PHY_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C130 0x20000140  //DDRSS_PHY_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C134 0x07FF0200  //DDRSS_PHY_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C138 0x0000DD01  //DDRSS_PHY_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C13C 0x10100303  //DDRSS_PHY_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C140 0x10101010  //DDRSS_PHY_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C144 0x10101010  //DDRSS_PHY_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C148 0x00021010  //DDRSS_PHY_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C14C 0x00100010  //DDRSS_PHY_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C150 0x00100010  //DDRSS_PHY_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C154 0x00100010  //DDRSS_PHY_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C158 0x00100010  //DDRSS_PHY_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C15C 0x02020010  //DDRSS_PHY_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C160 0x51515041  //DDRSS_PHY_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C164 0x31804000  //DDRSS_PHY_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C168 0x04A00340  //DDRSS_PHY_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C16C 0x01008080  //DDRSS_PHY_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C170 0x04050001  //DDRSS_PHY_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C174 0x00000504  //DDRSS_PHY_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C178 0x42100010  //DDRSS_PHY_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C17C 0x010C053E  //DDRSS_PHY_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C180 0x000F0C14  //DDRSS_PHY_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C184 0x01000140  //DDRSS_PHY_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C188 0x007A0120  //DDRSS_PHY_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C18C 0x00000C00  //DDRSS_PHY_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C190 0x000001CC  //DDRSS_PHY_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C194 0x20100200  //DDRSS_PHY_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C198 0x00000005  //DDRSS_PHY_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C19C 0x76543210  //DDRSS_PHY_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A0 0x00000008  //DDRSS_PHY_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A4 0x02800280  //DDRSS_PHY_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A8 0x02800280  //DDRSS_PHY_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1AC 0x02800280  //DDRSS_PHY_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B0 0x02800280  //DDRSS_PHY_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B4 0x01CC0280  //DDRSS_PHY_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B8 0x0000AE02  //DDRSS_PHY_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1BC 0x00AE00A2  //DDRSS_PHY_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C0 0x00A200A8  //DDRSS_PHY_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C4 0x00AE009C  //DDRSS_PHY_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C8 0x00AE00A8  //DDRSS_PHY_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1CC 0x00A800A2  //DDRSS_PHY_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D0 0x00A2009C  //DDRSS_PHY_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D4 0x00AE0096  //DDRSS_PHY_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D8 0x00AE009C  //DDRSS_PHY_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1DC 0x018E00A2  //DDRSS_PHY_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E0 0x01A00000  //DDRSS_PHY_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E4 0x00000000  //DDRSS_PHY_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E8 0x00000000  //DDRSS_PHY_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1EC 0x00080200  //DDRSS_PHY_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F0 0x00000000  //DDRSS_PHY_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F4 0x00000000  //DDRSS_PHY_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C400 0x04C00000  //DDRSS_PHY_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C404 0x00000000  //DDRSS_PHY_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C408 0x00000200  //DDRSS_PHY_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C40C 0x00000000  //DDRSS_PHY_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C410 0x00000000  //DDRSS_PHY_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C414 0x00000000  //DDRSS_PHY_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C418 0x00000000  //DDRSS_PHY_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C41C 0x00000000  //DDRSS_PHY_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C420 0x00000001  //DDRSS_PHY_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C424 0x00000000  //DDRSS_PHY_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C428 0x094C0000  //DDRSS_PHY_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C42C 0x010101FF  //DDRSS_PHY_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C430 0x00010000  //DDRSS_PHY_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C434 0x00C02404  //DDRSS_PHY_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C438 0x00CC0008  //DDRSS_PHY_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C43C 0x00660201  //DDRSS_PHY_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C440 0x00000000  //DDRSS_PHY_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C444 0x00000000  //DDRSS_PHY_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C448 0x00000000  //DDRSS_PHY_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C44C 0x0000AAAA  //DDRSS_PHY_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C450 0x00005555  //DDRSS_PHY_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C454 0x0000B5B5  //DDRSS_PHY_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C458 0x00004A4A  //DDRSS_PHY_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C45C 0x00005656  //DDRSS_PHY_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C460 0x0000A9A9  //DDRSS_PHY_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C464 0x0000B7B7  //DDRSS_PHY_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C468 0x00004848  //DDRSS_PHY_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C46C 0x00000000  //DDRSS_PHY_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C470 0x00000000  //DDRSS_PHY_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C474 0x08000000  //DDRSS_PHY_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C478 0x0F000008  //DDRSS_PHY_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C47C 0x00000F0F  //DDRSS_PHY_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C480 0x00E4E400  //DDRSS_PHY_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C484 0x00070820  //DDRSS_PHY_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C488 0x000C0020  //DDRSS_PHY_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C48C 0x00062000  //DDRSS_PHY_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C490 0x00000000  //DDRSS_PHY_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C494 0x55555555  //DDRSS_PHY_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C498 0xAAAAAAAA  //DDRSS_PHY_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C49C 0x55555555  //DDRSS_PHY_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A0 0xAAAAAAAA  //DDRSS_PHY_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A4 0x00005555  //DDRSS_PHY_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A8 0x01000100  //DDRSS_PHY_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4AC 0x00800180  //DDRSS_PHY_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B0 0x00000000  //DDRSS_PHY_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B4 0x00100000  //DDRSS_PHY_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B8 0x00000000  //DDRSS_PHY_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4BC 0x1208000F  //DDRSS_PHY_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C0 0x00000006  //DDRSS_PHY_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C4 0x00020200  //DDRSS_PHY_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C8 0x01D801CC  //DDRSS_PHY_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4CC 0x00000F00  //DDRSS_PHY_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D0 0x00000000  //DDRSS_PHY_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D4 0x02A00294  //DDRSS_PHY_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D8 0x00000031  //DDRSS_PHY_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4DC 0x0120003C  //DDRSS_PHY_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E0 0x00000000  //DDRSS_PHY_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E4 0x0C000000  //DDRSS_PHY_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E8 0x07FF0000  //DDRSS_PHY_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4EC 0x00000000  //DDRSS_PHY_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F0 0x00000000  //DDRSS_PHY_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F4 0x00000000  //DDRSS_PHY_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F8 0x00000000  //DDRSS_PHY_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4FC 0x00000000  //DDRSS_PHY_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C500 0x00000000  //DDRSS_PHY_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C504 0x00000004  //DDRSS_PHY_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C508 0x00000000  //DDRSS_PHY_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C50C 0x00000000  //DDRSS_PHY_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C510 0x00000000  //DDRSS_PHY_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C514 0x00000000  //DDRSS_PHY_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C518 0x00000000  //DDRSS_PHY_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C51C 0x00000000  //DDRSS_PHY_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C520 0x041F07FF  //DDRSS_PHY_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C524 0x00000000  //DDRSS_PHY_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C528 0x01CCB001  //DDRSS_PHY_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C52C 0x2000CCB0  //DDRSS_PHY_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C530 0x20000140  //DDRSS_PHY_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C534 0x07FF0200  //DDRSS_PHY_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C538 0x0000DD01  //DDRSS_PHY_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C53C 0x10100303  //DDRSS_PHY_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C540 0x10101010  //DDRSS_PHY_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C544 0x10101010  //DDRSS_PHY_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C548 0x00021010  //DDRSS_PHY_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C54C 0x00100010  //DDRSS_PHY_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C550 0x00100010  //DDRSS_PHY_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C554 0x00100010  //DDRSS_PHY_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C558 0x00100010  //DDRSS_PHY_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C55C 0x02020010  //DDRSS_PHY_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C560 0x51515041  //DDRSS_PHY_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C564 0x31804000  //DDRSS_PHY_345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C568 0x04A40340  //DDRSS_PHY_346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C56C 0x01008080  //DDRSS_PHY_347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C570 0x04050001  //DDRSS_PHY_348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C574 0x00000504  //DDRSS_PHY_349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C578 0x42100010  //DDRSS_PHY_350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C57C 0x010C053E  //DDRSS_PHY_351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C580 0x000F0C14  //DDRSS_PHY_352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C584 0x01000140  //DDRSS_PHY_353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C588 0x007A0120  //DDRSS_PHY_354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C58C 0x00000C00  //DDRSS_PHY_355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C590 0x000001CC  //DDRSS_PHY_356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C594 0x20100200  //DDRSS_PHY_357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C598 0x00000005  //DDRSS_PHY_358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C59C 0x76543210  //DDRSS_PHY_359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A0 0x00000008  //DDRSS_PHY_360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A4 0x02800280  //DDRSS_PHY_361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A8 0x02800280  //DDRSS_PHY_362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5AC 0x02800280  //DDRSS_PHY_363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B0 0x02800280  //DDRSS_PHY_364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B4 0x01D20280  //DDRSS_PHY_365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B8 0x0000AE02  //DDRSS_PHY_366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5BC 0x00A800A2  //DDRSS_PHY_367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C0 0x00AE009C  //DDRSS_PHY_368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C4 0x00AE009C  //DDRSS_PHY_369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C8 0x00AE00A8  //DDRSS_PHY_370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5CC 0x00A800A8  //DDRSS_PHY_371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D0 0x00AE00A2  //DDRSS_PHY_372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D4 0x00AE00A8  //DDRSS_PHY_373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D8 0x00AE009C  //DDRSS_PHY_374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5DC 0x019A00A2  //DDRSS_PHY_375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E0 0x01A00000  //DDRSS_PHY_376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E4 0x00000000  //DDRSS_PHY_377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E8 0x00000000  //DDRSS_PHY_378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5EC 0x00080200  //DDRSS_PHY_379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F0 0x00000000  //DDRSS_PHY_380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F4 0x00000000  //DDRSS_PHY_381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C800 0x00000100  //DDRSS_PHY_512_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C804 0x00001000  //DDRSS_PHY_513_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C808 0x00080000  //DDRSS_PHY_514_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C80C 0x00000000  //DDRSS_PHY_515_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C810 0x00000000  //DDRSS_PHY_516_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C814 0x00000100  //DDRSS_PHY_517_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C818 0x00000000  //DDRSS_PHY_518_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C81C 0x00000000  //DDRSS_PHY_519_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C820 0x00000000  //DDRSS_PHY_520_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C824 0x00000000  //DDRSS_PHY_521_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C828 0x00000000  //DDRSS_PHY_522_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C82C 0x00000000  //DDRSS_PHY_523_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C830 0x00000000  //DDRSS_PHY_524_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C834 0x00DCBA98  //DDRSS_PHY_525_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C838 0x00000000  //DDRSS_PHY_526_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C83C 0x00000000  //DDRSS_PHY_527_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C840 0x00000000  //DDRSS_PHY_528_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C844 0x00000000  //DDRSS_PHY_529_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C848 0x00000000  //DDRSS_PHY_530_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C84C 0x00000100  //DDRSS_PHY_531_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C850 0x00000000  //DDRSS_PHY_532_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C854 0x00000000  //DDRSS_PHY_533_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C858 0x00000000  //DDRSS_PHY_534_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C85C 0x00000000  //DDRSS_PHY_535_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C860 0x00000000  //DDRSS_PHY_536_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C864 0x00000000  //DDRSS_PHY_537_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C868 0x00000000  //DDRSS_PHY_538_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C86C 0x00000000  //DDRSS_PHY_539_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C870 0x0A418820  //DDRSS_PHY_540_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C874 0x103F0000  //DDRSS_PHY_541_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C878 0x000F0100  //DDRSS_PHY_542_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C87C 0x0000000F  //DDRSS_PHY_543_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C880 0x020002CC  //DDRSS_PHY_544_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C884 0x00030000  //DDRSS_PHY_545_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C888 0x00000300  //DDRSS_PHY_546_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C88C 0x00000300  //DDRSS_PHY_547_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C890 0x00000300  //DDRSS_PHY_548_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C894 0x00000300  //DDRSS_PHY_549_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C898 0x00000300  //DDRSS_PHY_550_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C89C 0x42080010  //DDRSS_PHY_551_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A0 0x0000003E  //DDRSS_PHY_552_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A4 0x00000000  //DDRSS_PHY_553_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A8 0x00000000  //DDRSS_PHY_554_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC00 0x00000100  //DDRSS_PHY_768_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC04 0x00001000  //DDRSS_PHY_769_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC08 0x00080000  //DDRSS_PHY_770_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC0C 0x00000000  //DDRSS_PHY_771_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC10 0x00000000  //DDRSS_PHY_772_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC14 0x00000100  //DDRSS_PHY_773_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC18 0x00000000  //DDRSS_PHY_774_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC1C 0x00000000  //DDRSS_PHY_775_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC20 0x00000000  //DDRSS_PHY_776_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC24 0x00000000  //DDRSS_PHY_777_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC28 0x00000000  //DDRSS_PHY_778_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC2C 0x00000000  //DDRSS_PHY_779_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC30 0x00000000  //DDRSS_PHY_780_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC34 0x00DCBA98  //DDRSS_PHY_781_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC38 0x00000000  //DDRSS_PHY_782_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC3C 0x00000000  //DDRSS_PHY_783_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC40 0x00000000  //DDRSS_PHY_784_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC44 0x00000000  //DDRSS_PHY_785_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC48 0x00000000  //DDRSS_PHY_786_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC4C 0x00000100  //DDRSS_PHY_787_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC50 0x00000000  //DDRSS_PHY_788_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC54 0x00000000  //DDRSS_PHY_789_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC58 0x00000000  //DDRSS_PHY_790_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC5C 0x00000000  //DDRSS_PHY_791_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC60 0x00000000  //DDRSS_PHY_792_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC64 0x00000000  //DDRSS_PHY_793_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC68 0x00000000  //DDRSS_PHY_794_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC6C 0x00000000  //DDRSS_PHY_795_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC70 0x16A4A0E6  //DDRSS_PHY_796_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC74 0x103F0000  //DDRSS_PHY_797_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC78 0x000F0000  //DDRSS_PHY_798_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC7C 0x0000000F  //DDRSS_PHY_799_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC80 0x020002CC  //DDRSS_PHY_800_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC84 0x00030000  //DDRSS_PHY_801_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC88 0x00000300  //DDRSS_PHY_802_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC8C 0x00000300  //DDRSS_PHY_803_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC90 0x00000300  //DDRSS_PHY_804_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC94 0x00000300  //DDRSS_PHY_805_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC98 0x00000300  //DDRSS_PHY_806_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC9C 0x42080010  //DDRSS_PHY_807_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA0 0x0000003E  //DDRSS_PHY_808_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA4 0x00000000  //DDRSS_PHY_809_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA8 0x00000000  //DDRSS_PHY_810_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D000 0x00000100  //DDRSS_PHY_1024_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D004 0x00001000  //DDRSS_PHY_1025_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D008 0x00080000  //DDRSS_PHY_1026_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D00C 0x00000000  //DDRSS_PHY_1027_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D010 0x00000000  //DDRSS_PHY_1028_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D014 0x00000100  //DDRSS_PHY_1029_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D018 0x00000000  //DDRSS_PHY_1030_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D01C 0x00000000  //DDRSS_PHY_1031_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D020 0x00000000  //DDRSS_PHY_1032_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D024 0x00000000  //DDRSS_PHY_1033_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D028 0x00000000  //DDRSS_PHY_1034_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D02C 0x00000000  //DDRSS_PHY_1035_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D030 0x00000000  //DDRSS_PHY_1036_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D034 0x00DCBA98  //DDRSS_PHY_1037_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D038 0x00000000  //DDRSS_PHY_1038_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D03C 0x00000000  //DDRSS_PHY_1039_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D040 0x00000000  //DDRSS_PHY_1040_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D044 0x00000000  //DDRSS_PHY_1041_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D048 0x00000000  //DDRSS_PHY_1042_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D04C 0x00000100  //DDRSS_PHY_1043_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D050 0x00000000  //DDRSS_PHY_1044_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D054 0x00000000  //DDRSS_PHY_1045_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D058 0x00000000  //DDRSS_PHY_1046_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D05C 0x00000000  //DDRSS_PHY_1047_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D060 0x00000000  //DDRSS_PHY_1048_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D064 0x00000000  //DDRSS_PHY_1049_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D068 0x00000000  //DDRSS_PHY_1050_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D06C 0x00000000  //DDRSS_PHY_1051_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D070 0x2307B9AC  //DDRSS_PHY_1052_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D074 0x10030000  //DDRSS_PHY_1053_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D078 0x000F0000  //DDRSS_PHY_1054_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D07C 0x0000000F  //DDRSS_PHY_1055_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D080 0x020002CC  //DDRSS_PHY_1056_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D084 0x00030000  //DDRSS_PHY_1057_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D088 0x00000300  //DDRSS_PHY_1058_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D08C 0x00000300  //DDRSS_PHY_1059_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D090 0x00000300  //DDRSS_PHY_1060_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D094 0x00000300  //DDRSS_PHY_1061_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D098 0x00000300  //DDRSS_PHY_1062_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D09C 0x42080010  //DDRSS_PHY_1063_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A0 0x0000003E  //DDRSS_PHY_1064_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A4 0x00000000  //DDRSS_PHY_1065_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A8 0x00000000  //DDRSS_PHY_1066_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D400 0x00000000  //DDRSS_PHY_1280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D404 0x00000100  //DDRSS_PHY_1281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D408 0x00000000  //DDRSS_PHY_1282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D40C 0x00000000  //DDRSS_PHY_1283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D410 0x00000000  //DDRSS_PHY_1284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D414 0x00000000  //DDRSS_PHY_1285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D418 0x00050000  //DDRSS_PHY_1286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D41C 0x04000100  //DDRSS_PHY_1287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D420 0x00000055  //DDRSS_PHY_1288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D424 0x00000000  //DDRSS_PHY_1289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D428 0x06800000  //DDRSS_PHY_1290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D42C 0x00000000  //DDRSS_PHY_1291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D430 0x00000000  //DDRSS_PHY_1292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D434 0x01002000  //DDRSS_PHY_1293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D438 0x00004001  //DDRSS_PHY_1294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D43C 0x00020028  //DDRSS_PHY_1295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D440 0x00010100  //DDRSS_PHY_1296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D444 0x00000001  //DDRSS_PHY_1297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D448 0x00000000  //DDRSS_PHY_1298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D44C 0x0F0F0E06  //DDRSS_PHY_1299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D450 0x00010101  //DDRSS_PHY_1300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D454 0x010F0004  //DDRSS_PHY_1301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D458 0x00000000  //DDRSS_PHY_1302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D45C 0x20125770  //DDRSS_PHY_1303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D460 0x00000064  //DDRSS_PHY_1304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D464 0x00000000  //DDRSS_PHY_1305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D468 0x00000000  //DDRSS_PHY_1306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D46C 0x01020103  //DDRSS_PHY_1307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D470 0x03020102  //DDRSS_PHY_1308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D474 0x03030303  //DDRSS_PHY_1309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D478 0x03030303  //DDRSS_PHY_1310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D47C 0x00040000  //DDRSS_PHY_1311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D480 0x00005201  //DDRSS_PHY_1312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D484 0x00000003  //DDRSS_PHY_1313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D488 0x00010000  //DDRSS_PHY_1314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D48C 0x00000000  //DDRSS_PHY_1315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D490 0x00000003  //DDRSS_PHY_1316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D494 0x00010000  //DDRSS_PHY_1317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D498 0x00000000  //DDRSS_PHY_1318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D49C 0x07070001  //DDRSS_PHY_1319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A0 0x00005400  //DDRSS_PHY_1320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A4 0x000040A2  //DDRSS_PHY_1321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A8 0x0003584F  //DDRSS_PHY_1322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4AC 0x00015890  //DDRSS_PHY_1323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B0 0x00015890  //DDRSS_PHY_1324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B4 0x00015890  //DDRSS_PHY_1325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B8 0x0001584F  //DDRSS_PHY_1326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4BC 0x00015890  //DDRSS_PHY_1327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C0 0x0001581D  //DDRSS_PHY_1328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C4 0x0001581D  //DDRSS_PHY_1329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C8 0x00015890  //DDRSS_PHY_1330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4CC 0x00015890  //DDRSS_PHY_1331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D0 0x00000000  //DDRSS_PHY_1332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D4 0x00000046  //DDRSS_PHY_1333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D8 0x00000400  //DDRSS_PHY_1334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4DC 0x00000008  //DDRSS_PHY_1335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E0 0x00815890  //DDRSS_PHY_1336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E4 0x0081581D  //DDRSS_PHY_1337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E8 0x00158900  //DDRSS_PHY_1338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4EC 0x001581D8  //DDRSS_PHY_1339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F0 0x00F5890F  //DDRSS_PHY_1340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F4 0x03F581DF  //DDRSS_PHY_1341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F8 0x00000000  //DDRSS_PHY_1342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4FC 0x00000000  //DDRSS_PHY_1343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D500 0xB3000000  //DDRSS_PHY_1344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D504 0x04102006  //DDRSS_PHY_1345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D508 0x00041020  //DDRSS_PHY_1346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D50C 0x01C98C98  //DDRSS_PHY_1347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D510 0x3F400000  //DDRSS_PHY_1348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D514 0x3F3F1F3F  //DDRSS_PHY_1349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D518 0x0000001F  //DDRSS_PHY_1350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D51C 0x00000000  //DDRSS_PHY_1351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D520 0x00000000  //DDRSS_PHY_1352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D524 0x00000000  //DDRSS_PHY_1353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D528 0x00000001  //DDRSS_PHY_1354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D52C 0x00000000  //DDRSS_PHY_1355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D530 0x00000000  //DDRSS_PHY_1356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D534 0x00000000  //DDRSS_PHY_1357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D538 0x00000000  //DDRSS_PHY_1358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D53C 0x76543210  //DDRSS_PHY_1359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D540 0x00000098  //DDRSS_PHY_1360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D544 0x00000000  //DDRSS_PHY_1361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D548 0x00000000  //DDRSS_PHY_1362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D54C 0x00000000  //DDRSS_PHY_1363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D550 0x00040700  //DDRSS_PHY_1364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D554 0x00000000  //DDRSS_PHY_1365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D558 0x00000000  //DDRSS_PHY_1366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D55C 0x00000000  //DDRSS_PHY_1367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D560 0x030F7102  //DDRSS_PHY_1368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D564 0x00000100  //DDRSS_PHY_1369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D568 0x00000000  //DDRSS_PHY_1370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D56C 0x0001F7C0  //DDRSS_PHY_1371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D570 0x00020002  //DDRSS_PHY_1372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D574 0x00000000  //DDRSS_PHY_1373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D578 0x00001142  //DDRSS_PHY_1374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D57C 0x03020400  //DDRSS_PHY_1375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D580 0x00000080  //DDRSS_PHY_1376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D584 0x03900390  //DDRSS_PHY_1377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D588 0x03900390  //DDRSS_PHY_1378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D58C 0x03900390  //DDRSS_PHY_1379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D590 0x03900390  //DDRSS_PHY_1380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D594 0x03900390  //DDRSS_PHY_1381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D598 0x03900390  //DDRSS_PHY_1382_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D59C 0x00000300  //DDRSS_PHY_1383_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A0 0x00000300  //DDRSS_PHY_1384_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A4 0x00000300  //DDRSS_PHY_1385_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A8 0x00000300  //DDRSS_PHY_1386_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5AC 0x31823FC7  //DDRSS_PHY_1387_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B0 0x00000000  //DDRSS_PHY_1388_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B4 0x0C000D3F  //DDRSS_PHY_1389_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B8 0x30000D3F  //DDRSS_PHY_1390_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5BC 0x300D3F11  //DDRSS_PHY_1391_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C0 0x01990000  //DDRSS_PHY_1392_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C4 0x000D3FCC  //DDRSS_PHY_1393_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C8 0x00000C11  //DDRSS_PHY_1394_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5CC 0x300D3F11  //DDRSS_PHY_1395_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D0 0x01990000  //DDRSS_PHY_1396_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D4 0x300C3F11  //DDRSS_PHY_1397_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D8 0x01990000  //DDRSS_PHY_1398_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5DC 0x300C3F11  //DDRSS_PHY_1399_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E0 0x01990000  //DDRSS_PHY_1400_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E4 0x300D3F11  //DDRSS_PHY_1401_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E8 0x01990000  //DDRSS_PHY_1402_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5EC 0x300D3F11  //DDRSS_PHY_1403_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F0 0x01990000  //DDRSS_PHY_1404_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F4 0x20040004  //DDRSS_PHY_1405_DATA

BG、

Jiminli

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

Jimin、您好！

感谢您的参与。

请注意、由于年末的假期、我们的回复可能会延迟。

此致、

Sreenivasa

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

Jimin、您好！

我注意到、在发生故障的电路板上、DDR 时钟偏差要大得多、超出了我们在 DDR 布局指南中的建议：https://www.ti.com/lit/pdf/spracu1

请注意、在将电路板上、CK_P 传递到 CK_N 时偏斜为： 928.77-927.71 = 1.06mil (在规格范围内)

在故障电路板上、CK_P 至 CK_N 偏斜为：876.875-867.151 = 9.724mil (超出规格)

CK_P 至 CK_N 的偏斜应在0.4ps (或2mil)内

这可能是导致您在故障电路板上看到问题的一个因素。

作为一个快速实验和可能的解决方法、您可以尝试通过更改配置文件中的以下两行来降低故障电路板上的时钟频率：

#define DDRSS_PLL_FREQUENCY 1 3333350000
#define DDRSS_PLL_FREQUENCY 2 3333350000

这会将频率降低至667MHz。

此致、

James

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好 JJD、

很抱歉耽误你的日期。

计算出的子板的 CK_P 和 CK_N 布线长度错误、原因是我们错过了一个距离(红色)、如下所示：

[引用 userid="1187" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4459511 #4459511"]在发生故障的电路板上、CK_P 至 CK_N 的偏差为：876.875-867.151 = 9.724mil (超出规格)

因此我们重新计算了它：CK_N 1058.68mil CK_P 1058.32mil。

CK_P 至 CK_N 的偏斜似乎在 2mil 内。

此外、我们会将 DDR 频率降低到667MHz 作为指令、子板 DDR 测试失败现象仍然存在。

谢谢、

jimin.Li

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

Jimin、

在从工作板中仔细检查寄存器转储后、我注意到寄存器表示该板的培训也没有成功完成、即使它在功能上工作。此外、由于似乎使用的是 gels、因此我认为初始化 DDR 并执行培训的驱动程序可能存在问题。

您是否在电路板上使用了 VTT 稳压器？如何生成所需的 VREF (DDR4_VREFca)？

此致、

James

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好 JJD、

谢谢！

[引用 userid="1187" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4467993 #4467993)]我注意到，寄存器表明，即使该板在功能上运行，该培训也无法成功完成。 [/报价]

是的、我们在母板和子板上都使用了 VTT 稳压器。

AM64x-EVM GP 板和我们的板之间的区别有两点：

我们的电路板稳压器器件型号为 TPS51200DRCT。

AM64x-EVM GP 板是 TPS51206DSQR。

电路板：稳压器的 VTT_EN 信号连接到 FPGA (上电后、FPGA 将保持高电平)。

AM64x-EVM GP 板：

首先、OSPI0_CSN0生成1.8V DDR_VTT_EN、然后通过电平转换器 TXS0102DCUR 将其转换为3.3V DDR_VTT_EN_3.3 最后、将 DDR_VTT_EN_3.3连接到稳压器的 VTT_EN 信号。

谢谢、

jimin.Li

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

谢谢您 Jimin。请检查 VTT_EN 信号的时序和稳定性：

-VTT_EN 相对于 DDR_RESET 的时序是多少？在 DDR_RESET 变为高电平之前、VTT_EN 必须为高电平、以确保在 DDR 初始化发生之前启用稳压器。 VTT_EN 变为高电平之后可能还有一段斜坡时间(请查看稳压器数据表)、必须在 DDR_RESET 变为高电平之前完成该时间

确保 VTT_EN 变为高电平并保持高电平。该信号必须只有一个从低电平到高电平的转换、并在所有 DDR 初始化和操作过程中保持高电平

确保 VTT_EN 在指定电压(1.8V)下保持高电平

此致、

James

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 JJD：

是的。我们已经仔细检查了 VTT_EN 和 DDR_RESET 信号的时序是否正常。

[报价 userid="1187" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4469268 #4469268"]VTT_EN 必须为高电平、然后 DDR_RESET 才会变为高电平、以确保在 DDR 初始化发生之前启用稳压器。 VTT_EN 变为高电平之后可能还有一段斜坡时间(请查看稳压器数据表)、必须在 DDR_RESET 变为高电平之前完成此时间[/ quot]

此外、关于代码中的 DDR VTT 函数、我删除了 K3-am642-R5-EVM.dts 中的 VTT_SUPPLY 节点。测试失败现象仍然存在。

我有一些问题：

1.儿童委员会和母板都没有完成复员方案培训？

2.无论子板 DDR 测试失败还是测试失败、DDR 培训始终未完成？

如果使用 GEL 进行操作、您是否认为有必要使用 CCS 演示(syscfg 选择 DDR)在我们的板上运行 DDR memcpy 测试？

[引用 userid="1187" URL"~/support/processors-group/processors/f/processors-forum/1172324/am6442-after-am6442-r5-spl-initial-ddr-test-memcpy-fail/4467993 #4467993)]我注意到，寄存器表明，即使该板在功能上运行，该培训也无法成功完成。此外、由于事情似乎与 gels 一起工作、[/引述]

如何判断 DDR 培训是否完成？您能提供线索或规格吗？

谢谢、

jimin.Li

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

Jimin

1.是的、从您发送的通过和失败寄存器转储中、两个都显示了未完成的培训结果。看起来培训已部分完成、但有一个"doe"位、表示培训算法已完全完成、但未设置。

至少在您发送的寄存器转储中。您仅为每个电路板提供了1个寄存器转储。为了更好地了解、如果您可以提供一些寄存器转储(几个来自故障子板、几个来自通过主板)、我们可以获得更好的确认。此外、如果您可以使用 GEL 脚本发送寄存器转储、也许我可以识别导致此情况的原因。

3. 是的、我最好使用 GEL 配置运行测试

您能否使用 GEL 脚本发送 regdump、以及在引导时从每个失败和通过情形中再发送几个 regdump

此致、

James

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 JJD：

我是中国新年的 OOO。感谢您的建议。我将在我从职业回来时更新该主题。

BG、

jimin.Li

0 admin 2 年多前

TI__Guru**** 2050740 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

jimin.Li 您好

感谢您的备注。

此致、

Sreenivasa