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[参考译文] TDA4VM:TIDL 推理在8.5中失败、但对于某些 TFLITE 模型来说是在8.4中有效的

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Other Parts Discussed in Thread: TDA4VM

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https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1204537/tda4vm-tidl-inference-fails-in-8-5-but-works-in-8-4-for-some-tflite-models

器件型号:TDA4VM

您好!

我有 TDA4VM 板、      在 ubuntu 18.04下使用 ti-processor-sdk-rtos-j721e-evm 版本08_05。

我正在使用 Python 脚本导入并使用 OSRT ( TFLITE ) API 运行推理。

在几个 CNN 模型(TFLITE )上,我在推理期间收到一个错误,如下所示:

 ------- config file  ---------
{'model_path': '../SHARE/ydet/ydet_reduced_int8.tflite', 'artifact_folder': './ARTIF/artif_YDET', 'in_range_min': 0.0, 'in_range_max': 1.0, 'calib_nbTensors': 1, 'calib_accuy': 0, 'calib_nbIterations': 1, 'calib_tensorBits': 8, 'calib_debug_level': 0, 'calib_deny_list': ' 114 , 6 ', 'calib_high_resolution_optimization': 0, 'random_mode': 0, 'inence_debug_level': 0, 'images_folder': '', 'image_inf': '', 'image_inf_constval': 0.5, 'model_type': 1}
 ----------------
 running inference on TIDL , and on OSRT
INFERENCE   tidl_tools_path=/home/ti-proc-rtos-8-5/tidl_j721e_08_05_00_16/tidl_tools , artifact_folder=./ARTIF/artif_YDET , model=../SHARE/ydet/ydet_reduced_int8.tflite
run inference  ... use_tidl backend =  True

 Number of subgraphs:1 , 73 nodes delegated out of 77 nodes

The soft limit is 2048
The hard limit is 2048
MEM: Init ... !!!
MEM: Init ... Done !!!
 0.0s:  VX_ZONE_INIT:Enabled
 0.11s:  VX_ZONE_ERROR:Enabled
 0.15s:  VX_ZONE_WARNING:Enabled
 0.2134s:  VX_ZONE_INIT:[tivxInit:184] Initialization Done !!!
 0.7465s:  VX_ZONE_ERROR:[tivxAlgiVisionCreate:332] Calling ialg.algInit failed with status = -1120
Segmentation fault (core dumped)

此错误在 SDK 版本08_05 上发生、但在版本08_04上不会发生。

我在 TIDL 源代码中检查了  一个与初始化期间内存分配失败相关的问题(在  tiovx/kernels/ivision/common/tivx_alg_vision.c 中 )
崩溃本身可能只是错误检测之后的一个错误。

下面是 GDB 中的反向跟踪:

Thread 7 "python3" received signal SIGSEGV, Segmentation fault.
	[Switching to Thread 0x7fffea8f9700 (LWP 13696)]
	0x00007fffc0fd3ea4 in TIDL_removePriorityObject(void*, IALG_MemRec*) () from /home/ti-proc-rtos-8-5/tidl_j721e_08_05_00_16/tidl_tools/libvx_tidl_rt.so
	(gdb) bt
	#0  0x00007fffc0fd3ea4 in TIDL_removePriorityObject(void*, IALG_MemRec*) () from /home/ti-proc-rtos-8-5/tidl_j721e_08_05_00_16/tidl_tools/libvx_tidl_rt.so
	#1  0x00007fffc0eed99a in tivxAlgiVisionDeleteAlg () from /home/ti-proc-rtos-8-5/tidl_j721e_08_05_00_16/tidl_tools/libvx_tidl_rt.so
	#2  0x00007fffc0eeddcf in tivxAlgiVisionCreate () from /home/ti-proc-rtos-8-5/tidl_j721e_08_05_00_16/tidl_tools/libvx_tidl_rt.so
	#3  0x00007fffc0eece6d in tivxKernelTIDLCreate () from /home/ti-proc-rtos-8-5/tidl_j721e_08_05_00_16/tidl_tools/libvx_tidl_rt.so
	#4  0x00007fffc0ee9a80 in ownTargetKernelCreate () from /home/ti-proc-rtos-8-5/tidl_j721e_08_05_00_16/tidl_tools/libvx_tidl_rt.so
	#5  0x00007fffc0ee1715 in ownTargetNodeDescNodeCreate () from /home/ti-proc-rtos-8-5/tidl_j721e_08_05_00_16/tidl_tools/libvx_tidl_rt.so
	#6  0x00007fffc0ee3154 in ownTargetTaskMain () from /home/ti-proc-rtos-8-5/tidl_j721e_08_05_00_16/tidl_tools/libvx_tidl_rt.so
	#7  0x00007fffc0eea558 in tivxTaskMain () from /home/ti-proc-rtos-8-5/tidl_j721e_08_05_00_16/tidl_tools/libvx_tidl_rt.so
	#8  0x00007ffff77ca6db in start_thread (arg=0x7fffea8f9700) at pthread_create.c:463
	#9  0x00007ffff7b0361f in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:95

 

如上所述,我在某些模型(预量化的 TFLITE 模型)上有这个错误。

感谢你的帮助。   

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好!

    您能否确认 您为"quantization_scale_type"编译选项设置的值? 此外,您是否可以确认编译已成功进行,没有任何错误,请分享编译日志。

    此致、

    Anand

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好!

    advanced_options:量化_scale_type =0  (非2的幂)
    这是导入8位的日志(导入单个输入张量和随机值),显示没有错误。
    tidl_tools_path                                 = /home/ti-proc-rtos-8-5/tidl_j721e_08_05_00_16/tidl_tools
    artifacts_folder                                = ./ARTIF/artif_YDET
    tidl_tensor_bits                                = 8
    debug_level                                     = 0
    num_tidl_subgraphs                              = 16
    tidl_denylist                                   = 114   6
    tidl_denylist_layer_name                        =
    tidl_denylist_layer_type                         =
    model_type                                      =
    tidl_calibration_accuracy_level                 = 64
    tidl_calibration_options:num_frames_calibration = 1
    tidl_calibration_options:bias_calibration_iterations = 1
    mixed_precision_factor = -1.000000
    model_group_id = 0
    power_of_2_quantization                         = 2
    enable_high_resolution_optimization             = 0
    pre_batchnorm_fold                              = 1
    add_data_convert_ops                          = 0
    output_feature_16bit_names_list                 =
    m_params_16bit_names_list                       =
    reserved_compile_constraints_flag               = 1601
    ti_internal_reserved_1                          =
    
     Number of subgraphs:1 , 73 nodes delegated out of 77 nodes
    
    WARNING : Pad layer won't be merged in the succeeding layer, it will be treated as a stand alone layer
    WARNING : Pad layer won't be merged in the succeeding layer, it will be treated as a stand alone layer
    WARNING : Pad layer won't be merged in the succeeding layer, it will be treated as a stand alone layer
    WARNING : Pad layer won't be merged in the succeeding layer, it will be treated as a stand alone layer
    WARNING : Pad layer won't be merged in the succeeding layer, it will be treated as a stand alone layer
    
     ************** Frame index 1 : Running float import *************
    IMPORT nb operations : Total Giga Macs : 5.2293   , network file ./ARTIF/artif_YDET/tempDir/136_tidl_net.bin_netLog.txt
    INFORMATION: [TIDL_ResizeLayer] model/lambda/resize/ResizeNearestNeighbor Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] model/lambda_1/resize/ResizeNearestNeighbor Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    WARNING: [TIDL_E_DATAFLOW_INFO_NULL] Network compiler returned with error or didn't executed, this model can only be used on PC/Host emulation mode, it is not expected to work on target/EVM.
    ****************************************************
    **          3 WARNINGS          0 ERRORS          **
    ****************************************************
    The soft limit is 2048
    The hard limit is 2048
    MEM: Init ... !!!
    MEM: Init ... Done !!!
     0.0s:  VX_ZONE_INIT:Enabled
     0.11s:  VX_ZONE_ERROR:Enabled
     0.15s:  VX_ZONE_WARNING:Enabled
     0.1689s:  VX_ZONE_INIT:[tivxInit:184] Initialization Done !!!
    INFO: Created TensorFlow Lite XNNPACK delegate for CPU.
    ------debug ---------
    TENSOR details : input  name=inputs:0   index=137  shape=[  1 512 608   3]  type=<class 'numpy.float32'>  nb_of_elem=933888
    TENSOR details : output  name=Identity_2:0   index=138  shape=[ 1 64 76  5]  type=<class 'numpy.float32'>  nb_of_elem=24320
    TENSOR details : output  name=Identity_1:0   index=139  shape=[ 1 32 38  5]  type=<class 'numpy.float32'>  nb_of_elem=6080
    TENSOR details : output  name=Identity:0   index=140  shape=[ 1 16 19  5]  type=<class 'numpy.float32'>  nb_of_elem=1520
    TENSOR=input calibration tensor 0   size=933888 shape=(1, 512, 608, 3) min=0.000 max=1.000  :   0.1171 0.9406 0.0156 0.6484 0.5904  ... 0.1409 0.2720  ... 0.7644 0.8286 0.7213 0.8195
    
     ************ Frame index 1 : Running fixed point mode for calibration ****************
    IMPORT nb operations : Total Giga Macs : 5.2293   , network file ./ARTIF/artif_YDET/tempDir/136_tidl_net.bin_netLog.txt
    IMPORT nb operations : Total Giga Macs : 5.2293   , network file ./ARTIF/artif_YDET/tempDir/136_tidl_net.bin_netLog.txt
    
    ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~
    
    Processing config file #0 : /home/calll81z/jacinto/ARTIF/artif_YDET/tempDir/136_tidl_io_.qunat_stats_config.txt
     ----------------------- TIDL Process with REF_ONLY FLOW ------------------------
    
    #    0 . .. T   15607.59  .... ..... ... .... .....IMPORT nb operations : Total Giga Macs : 5.2293   , network file ./ARTIF/artif_YDET/tempDir/136_tidl_net.bin_netLog.txt
    
    ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~
    
    Processing config file #0 : /home/calll81z/jacinto/ARTIF/artif_YDET/tempDir/136_tidl_io_.qunat_stats_config.txt
     ----------------------- TIDL Process with REF_ONLY FLOW ------------------------
    
    #    0 . .. T   16733.15  .... ..... ... .... .....
    
    
     *****************   Calibration iteration number 0 completed ************************
    
    
    
    IMPORT nb operations : Total Giga Macs : 5.2293   , network file ./ARTIF/artif_YDET/tempDir/136_tidl_net.bin_netLog.txt
    
    ------------------ Network Compiler Traces -----------------------------
    successful Memory allocation
    Rerunning network compiler
    
    ------------------ Network Compiler Traces -----------------------------
    successful Memory allocation
    INFORMATION: [TIDL_ResizeLayer] model/lambda/resize/ResizeNearestNeighbor Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] model/lambda_1/resize/ResizeNearestNeighbor Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    ****************************************************
    **          2 WARNINGS          0 ERRORS          **
    ****************************************************
     import done ... copying model  ../SHARE/ydet/ydet_reduced_int8.tflite  to artifact dir ./ARTIF/artif_YDET
    
     end import
    IMPORT num_of_calib_tensors=1  accuracy_level=0  calibration_iterations=1
    
    
    MEM: Deinit ... !!!
    MEM: Alloc's: 29 alloc's of 339652644 bytes
    MEM: Free's : 29 free's  of 339652644 bytes
    MEM: Open's : 0 allocs  of 0 bytes
    MEM: Deinit ... Done !!!
    ... end tool ...
    
    此致、
    克里斯托弗
  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好!

    我再次查看了这些具有新 SDK 08_06 版本的模型。

    现在导入过程顺利。

    因此我们可以关闭该票证。

    谢谢。

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    好的、谢谢。