[参考译文] TDA4VM：C7X 上的 uDMA 慢于 A72上的 memcpy

app_udma_ch_handle_t handle = NULL;
#ifdef C71
handle = appUdmaCopyNDGetHandle(8U);
#endif
if (0 == appUdmaCopy1D(handle, &prms))
{
    ret = true;
}

typedef struct
{
    uint32_t elems;
    uint32_t srcOffset;
    uint32_t dstOffset;
} TensorCpyCfg;

bool TensorBlockCpyDma(const TensorCpyCfg* const cfg,
                       const tivx_obj_desc_tensor_t* const srcDescriptor,
                       const tivx_obj_desc_tensor_t* const dstDescriptor,
                       const void* restrict const srcMapped,
                       void* restrict const dstMapped)
{
    bool ret = false;
    if (   (NULL == cfg)
        || (NULL == srcDescriptor)
        || (NULL == dstDescriptor)
        || (NULL == srcMapped)
        || (NULL == dstMapped))
    {
        VX_PRINT(VX_ZONE_ERROR, "Invalid input pointer\n");
    }
    else if (0U == cfg->elems)
    {
        VX_PRINT(VX_ZONE_ERROR, "Empty copy\n");
    }
    else
    {
        const uint32_t transferSize = cfg->elems * srcDescriptor->stride[0];
        const uint32_t srcAvailableSize = srcDescriptor->mem_size - cfg->srcOffset * srcDescriptor->stride[0];
        const uint32_t dstAvailableSize = dstDescriptor->mem_size - cfg->dstOffset * dstDescriptor->stride[0];
        if (   (transferSize > srcAvailableSize)
            || (transferSize > dstAvailableSize))
        {
            VX_PRINT(VX_ZONE_ERROR, "Invalid size/offset combination\n");
        }
        else
        {

            const uint32_t srcOffset = cfg->srcOffset*srcDescriptor->stride[0];
            const uint32_t dstOffset = cfg->dstOffset*dstDescriptor->stride[0];

            uint64_t srcPhys = tivxMemShared2PhysPtr(srcDescriptor->mem_ptr.shared_ptr, VX_MEMORY_TYPE_HOST) + srcOffset;
            uint64_t dstPhys = tivxMemShared2PhysPtr(dstDescriptor->mem_ptr.shared_ptr, VX_MEMORY_TYPE_HOST) + dstOffset;

            uint32_t start = tivxPlatformGetTimeInUsecs();
            app_udma_copy_1d_prms_t prms;
            appUdmaCopy1DPrms_Init(&prms);
            uint32_t delta = tivxPlatformGetTimeInUsecs() - start;
            VX_PRINT(VX_ZONE_WARNING, "appUdmaCopy1DPrms_Init = %u us\n", delta);
            prms.dest_addr = dstPhys;
            prms.src_addr = srcPhys;
            prms.length = transferSize;

            app_udma_ch_handle_t handle = NULL;
            #ifdef C71
            start = tivxPlatformGetTimeInUsecs();
            handle = appUdmaCopyNDGetHandle(8U);
            delta = tivxPlatformGetTimeInUsecs() - start;
            VX_PRINT(VX_ZONE_WARNING, "appUdmaCopyNDGetHandle = %u us\n", delta);
            #endif
            start = tivxPlatformGetTimeInUsecs();
            if (0 == appUdmaCopy1D(handle, &prms))
            {
                // void* dstVirt = (uint8_t*) dstMapped + dstOffset;
                // appMemCacheInv(dstVirt, transferSize);
                ret = true;
            }
            delta = tivxPlatformGetTimeInUsecs() - start;
            VX_PRINT(VX_ZONE_WARNING, "appUdmaCopy1D = %u us\n", delta);
        }
    }
    return ret;
}

TEST_CASE("TensorCpy - Performance comparison)
{
	REQUIRE(0 == appInit());
	tivxRegisterMemoryTargetA72Kernels();	// Registers the A72 memcpy kernel

	std::string target = TIVX_TARGET_A72_0;
	std::string impl = "CPU";

	const size_t COLS = 864;
	const size_t ROWS = 128 * 5;
	std::vector<vx_size> dims{COLS, ROWS};

	TiovxUserKernelsTests::VxTensorWrapper src("TensorCpy src", dims);
	TiovxUserKernelsTests::VxTensorWrapper dst("TensorCpy dst", dims);
	TiovxUserKernelsTests::VxUserDataObjectWrapper<TensorCpyCfg> cfg("TensorCpyCfg");

	TensorCpyGraph graph(cfg, src, dst, target);	// Calls vxCreateContext()

	src.Allocate(graph.ctx);						// Calls vxCreateTensor()
	dst.Allocate(graph.ctx);						// Calls vxCreateTensor()

	float* srcptr = src.Map(VX_WRITE_ONLY);			// Calls tivxMapTensorPatch()
	float* dstptr = dst.Map(VX_WRITE_ONLY);			// Calls tivxMapTensorPatch()
	for (size_t i = 0; i < COLS*ROWS; i++)
	{
		srcptr[i] = i;
		dstptr[i] = 0;
	}
	src.Unmap();									// Calls tivxUnMapTensorPatch()
	dst.Unmap();									// Calls tivxUnMapTensorPatch()

	TensorCpyCfg cfgData;
	cfgData.elems = COLS * ROWS;
	cfgData.srcOffset = 0;
	cfgData.dstOffset = 0;
	cfg.Allocate(graph.ctx, &cfgData);				// Calls vxCreateUserDataObject()

	graph.Allocate();								// Calls vxCreateGraph()
	graph.Verify();									// Calls vxVerifyGraph()
	graph.Run();									// Calls vxProcessGraph()
	graph.PrintStats();								// Calls tivx_utils_graph_perf_print()

	srcptr = src.Map(VX_READ_ONLY);					// Calls tivxMapTensorPatch()
	dstptr = dst.Map(VX_READ_ONLY);					// Calls tivxMapTensorPatch()

	REQUIRE(0 == memcmp(srcptr, dstptr, COLS*ROWS*sizeof(float)));

	src.Delete();									// Calls vxReleaseTensor()
	dst.Delete();									// Calls vxReleaseTensor()
	cfg.Delete();									// Calls vxReleaseUserDataObject()

	graph.Delete();									// Calls vxReleaseGraph(), vxReleaseContext()

	tivxUnRegisterMemoryTargetA72Kernels();			// Unregisters A72 memcpy kernel
	REQUIRE(0 == appDeInit());
}