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大家好
CPSW2G 的 RGMII 被连接到我们电路板内的 Switch (sja1105)。
如下所示设置 cpsw2g 驱动程序:
1/ io-pkt-v6-hc -d cpsw2g verbose=0xff、mac-to-mac=1、speed=1000
2/ ifconfig am0启动
但 我测量的 TX 时钟仅为2.5MHz
硬件:
登录2info 的日志:
J784S4-EVM@QNX:/# slog2info | grep io_pkt Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog* 0 cpsw_entry:546 Entry --> Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 cpsw_attach:718 Entry --> Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 cpsw_parse_options:200 Verbose -->255 Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 cpsw_parse_options:222 mac_to_mac -->1 Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 cpsw_parse_options:235 speed -->1000 Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 bsd_mii_initmedia:270 Came here --> Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 jeken: EnetIfBoard_cpsw2gMacModeConfig portNum=0, mode=0x2 Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 Success - write to MCU_ENET_CTRL - 0x12 Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 jeken: EnetIf_selectCptsClock clkSelMux=0xf Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 Success - write to MCU_ENET_CLKSEL - 0xf00 Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 cpsw2g Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 Vendor .............. 0x0 Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 Device .............. 0x0 Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 Revision ............ 0x0 Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 I/O port base ....... 0x46000000 Jan 01 00:01:19.692 io_pkt_v6_hc.118804 slog 0 MAC address ......... 68e74a 08bf9a Jan 01 00:01:44.415 io_pkt_v6_hc.118804 slog 0 cpsw_ioctl:386 Came here -->cmd-0x8090690c Jan 01 00:01:44.415 io_pkt_v6_hc.118804 slog 0 cpsw_init:999 Entry --> Jan 01 00:01:44.415 io_pkt_v6_hc.118804 slog 0 EnetIf_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:4 From 1 To 0 Jan 01 00:01:44.415 io_pkt_v6_hc.118804 slog 0 EnetIf_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 1 To 0 Jan 01 00:01:44.415 io_pkt_v6_hc.118804 slog 0 ENET_CPSW_2G on MCU NAVSS Jan 01 00:01:44.434 io_pkt_v6_hc.118804 slog 56 [UDMA] Calling Udma_resmgr_open Jan 01 00:01:44.434 io_pkt_v6_hc.118804 slog 56 [UDMA] Opening resmgr!!! Jan 01 00:01:44.435 io_pkt_v6_hc.118804 slog 56 [UDMA] Opened resmgr fd=6!!! Jan 01 00:01:44.435 io_pkt_v6_hc.118804 slog 56 [UDMA] eventHandle->vintrNum = 57!!! Jan 01 00:01:44.435 io_pkt_v6_hc.118804 slog 56 [UDMA] eventHandle->irIntrNum = 17!!! Jan 01 00:01:44.435 io_pkt_v6_hc.118804 slog 56 [UDMA] eventHandle->coreIntrNum = 81!!! Jan 01 00:01:44.447 io_pkt_v6_hc.118804 slog 0 EnetIf_registerIntr2: tx isr 81 thread priority set to 21 Jan 01 00:01:44.447 io_pkt_v6_hc.118804 slog 0 EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/81 coid/1073741848 event/d Jan 01 00:01:44.447 io_pkt_v6_hc.118804 slog 0 Enet_open: cpsw2g: features: 0x00000000 Jan 01 00:01:44.447 io_pkt_v6_hc.118804 slog 0 Enet_open: cpsw2g: errata : 0x00000000 Jan 01 00:01:44.448 io_pkt_v6_hc.118804 slog 0 cpsw_alloc:299: Alloc successfull; Virt: 0x4c4819e000, Phys: 0xfe7290000 Jan 01 00:01:44.448 io_pkt_v6_hc.118804 slog 0 EnetUdma_memMgrInit: addr=0x4c4819e000 is aligned Jan 01 00:01:44.459 io_pkt_v6_hc.118804 slog 0 EnetIf_registerIntr: cpsw stat isr thread priority set to 21 Jan 01 00:01:44.459 io_pkt_v6_hc.118804 slog 0 EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/888 coid/1073741852 event/e Jan 01 00:01:44.459 io_pkt_v6_hc.118804 slog 0 EnetIf_registerIntr: cpsw cpts isr thread priority set to 22 Jan 01 00:01:44.459 io_pkt_v6_hc.118804 slog 0 EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/890 coid/1073741854 event/f Jan 01 00:01:44.460 io_pkt_v6_hc.118804 slog 0 cpsw_alloc:299: Alloc successfull; Virt: 0x4c4823a000, Phys: 0xfe72a4000 Jan 01 00:01:44.460 io_pkt_v6_hc.118804 slog 0 EnetIfMem_init: addr=0x4c4823a000 is aligned Jan 01 00:01:44.460 io_pkt_v6_hc.118804 slog 0 EnetIfMem_init: addr=0x4c4823a000, size=0x221000, gMem=0x4c4823a000, gMemBufPhys=0xfe72a4000 Jan 01 00:01:44.460 io_pkt_v6_hc.118804 slog 0 EnetIfMem_init: gDmaDescMemArray=0x4c4823a000, size=0x200000 Jan 01 00:01:44.460 io_pkt_v6_hc.118804 slog 0 EnetIfMem_init: gRingMemArray=0x4c4843a000, size=0x21000 Jan 01 00:01:44.461 io_pkt_v6_hc.118804 slog 0 EnetIfMem_init: gDmaDescMemArrayBasePhys=0xfe72a4000, gDmaDescMemArrayBase=0x4c4823a000 Jan 01 00:01:44.463 io_pkt_v6_hc.118804 slog 0 initQs() freePktInfoQ initialized with 256 pkts Jan 01 00:01:44.477 io_pkt_v6_hc.118804 slog 56 [UDMA] eventHandle->globalEvent = 56!!! Jan 01 00:01:44.477 io_pkt_v6_hc.118804 slog 56 [UDMA] eventHandle->vintrNum = 58!!! Jan 01 00:01:44.477 io_pkt_v6_hc.118804 slog 56 [UDMA] eventHandle->vintrBitNum = 0!!! Jan 01 00:01:44.477 io_pkt_v6_hc.118804 slog 56 [UDMA] eventHandle->irIntrNum = 18!!! Jan 01 00:01:44.477 io_pkt_v6_hc.118804 slog 56 [UDMA] eventHandle->coreIntrNum = 82!!! Jan 01 00:01:44.500 io_pkt_v6_hc.118804 slog 0 EnetIf_registerIntr2: rx isr 82 thread priority set to 21 Jan 01 00:01:44.500 io_pkt_v6_hc.118804 slog 0 EnetIf_registerIntr2: RX InterruptAttachEvent succeed irq/82 coid/1073741855 event/10 Jan 01 00:01:44.500 io_pkt_v6_hc.118804 slog 0 Host MAC address: Jan 01 00:01:44.500 io_pkt_v6_hc.118804 slog 0 68:e7:4a:08:bf:9a Jan 01 00:01:44.501 io_pkt_v6_hc.118804 slog 0 cpsw_init:1068 Phy is linked Jan 01 00:01:44.501 io_pkt_v6_hc.118804 slog 0 cpsw_init:1104 <--Exit Jan 01 00:01:44.501 io_pkt_v6_hc.118804 slog 0 cpsw_ioctl:472 <-- Jan 01 00:01:44.501 io_pkt_v6_hc.118804 slog 0 cpsw_ioctl:386 Came here -->cmd-0x80906931 Jan 01 00:01:44.501 io_pkt_v6_hc.118804 slog 0 cpsw_filter: Clear IFF_ALLMULTI Jan 01 00:01:44.501 io_pkt_v6_hc.118804 slog 0 cpsw_filter: Adding Multicast MAC Addr -> 33:33:ff:08:bf:9a Jan 01 00:01:44.501 io_pkt_v6_hc.118804 slog 0 cpsw_ioctl:472 <-- Jan 01 00:01:44.501 io_pkt_v6_hc.118804 slog 0 cpsw_ioctl:386 Came here -->cmd-0x80906931 Jan 01 00:01:44.501 io_pkt_v6_hc.118804 slog 0 cpsw_filter: Clear IFF_ALLMULTI Jan 01 00:01:44.502 io_pkt_v6_hc.118804 slog 0 cpsw_filter: Adding Multicast MAC Addr -> 33:33:00:00:00:01 Jan 01 00:01:44.502 io_pkt_v6_hc.118804 slog 0 cpsw_filter: Adding Multicast MAC Addr -> 33:33:ff:08:bf:9a Jan 01 00:01:44.502 io_pkt_v6_hc.118804 slog 0 cpsw_ioctl:472 <-- Jan 01 00:01:44.502 io_pkt_v6_hc.118804 slog 0 cpsw_ioctl:386 Came here -->cmd-0x80906931 Jan 01 00:01:44.502 io_pkt_v6_hc.118804 slog 0 cpsw_ioctl:472 <-- Jan 01 00:01:44.502 io_pkt_v6_hc.118804 slog 0 cpsw_ioctl:386 Came here -->cmd-0x80906910 Jan 01 00:01:44.502 io_pkt_v6_hc.118804 slog 0 cpsw_init:999 Entry --> Jan 01 00:01:44.502 io_pkt_v6_hc.118804 slog 0 cpsw_init:1104 <--Exit Jan 01 00:01:44.502 io_pkt_v6_hc.118804 slog 0 cpsw_ioctl:472 <-- Jan 01 00:01:44.778 io_pkt_v6_hc.118804 slog 0 cpsw_start:1240 Entry --> Jan 01 00:01:44.778 io_pkt_v6_hc.118804 slog 0 cpsw_start:1313 packet length 86, EthType is 0x86dd, IPv6 Protocol is 0x0, txFreeCnt 128 Jan 01 00:01:44.778 io_pkt_v6_hc.118804 slog 0 TX Buffer ------> size:86 Jan 01 00:01:44.778 io_pkt_v6_hc.118804 slog 0 Dst addr : Jan 01 00:01:44.778 io_pkt_v6_hc.118804 slog 0 33:33:ff:08:bf:9a Jan 01 00:01:44.778 io_pkt_v6_hc.118804 slog 0 Src addr : Jan 01 00:01:44.778 io_pkt_v6_hc.118804 slog 0 68:e7:4a:08:bf:9a Jan 01 00:01:44.778 io_pkt_v6_hc.118804 slog 0 EtherType: 0x86dd Jan 01 00:01:44.778 io_pkt_v6_hc.118804 slog 0 Payload : Jan 01 00:01:44.778 io_pkt_v6_hc.118804 slog 0 60 00 00 00 00 20 00 01 00 00 00 00 00 00 00 00 Jan 01 00:01:44.778 io_pkt_v6_hc.118804 slog 0 00 00 00 00 00 00 00 00 ff 02 00 00 00 00 00 00 Jan 01 00:01:44.778 io_pkt_v6_hc.118804 slog 0 00 00 00 01 ff 08 bf 9a 3a 00 01 00 05 02 00 00 Jan 01 00:01:44.778 io_pkt_v6_hc.118804 slog 0 83 00 01 5e 00 00 00 00 ff 02 00 00 00 00 00 00 Jan 01 00:01:44.778 io_pkt_v6_hc.118804 slog 0 00 00 00 01 ff 08 bf 9a Jan 01 00:01:45.428 io_pkt_v6_hc.118804 slog 0 cpsw_start:1240 Entry --> Jan 01 00:01:45.428 io_pkt_v6_hc.118804 slog 0 cpsw_start:1313 packet length 78, EthType is 0x86dd, IPv6 Protocol is 0x3a, txFreeCnt 127 Jan 01 00:01:45.428 io_pkt_v6_hc.118804 slog 0 TX Buffer ------> size:78 Jan 01 00:01:45.428 io_pkt_v6_hc.118804 slog 0 Dst addr : Jan 01 00:01:45.428 io_pkt_v6_hc.118804 slog 0 33:33:ff:08:bf:9a Jan 01 00:01:45.428 io_pkt_v6_hc.118804 slog 0 Src addr : Jan 01 00:01:45.428 io_pkt_v6_hc.118804 slog 0 68:e7:4a:08:bf:9a Jan 01 00:01:45.428 io_pkt_v6_hc.118804 slog 0 EtherType: 0x86dd Jan 01 00:01:45.428 io_pkt_v6_hc.118804 slog 0 Payload : Jan 01 00:01:45.428 io_pkt_v6_hc.118804 slog 0 60 00 00 00 00 18 3a ff 00 00 00 00 00 00 00 00 Jan 01 00:01:45.428 io_pkt_v6_hc.118804 slog 0 00 00 00 00 00 00 00 00 ff 02 00 00 00 00 00 00 Jan 01 00:01:45.428 io_pkt_v6_hc.118804 slog 0 00 00 00 01 ff 08 bf 9a 87 00 48 fa 00 00 00 00 Jan 01 00:01:45.428 io_pkt_v6_hc.118804 slog 0 fe 80 00 00 00 00 00 00 6a e7 4a ff fe 08 bf 9a Jan 01 00:01:45.428 io_pkt_v6_hc.118804 slog 0 fe 80 00 00 00 00 00 00 6a e7 4a ff fe 08 bf 9a
Br
耶肯
您好、Jeken!
但 我测量的 TX 时钟仅为2.5MHz
您能告诉我们您用于测量 TX 时钟的时钟探测点是什么吗?
此外、您希望它的时钟频率是多少?
谢谢。
大家好
时钟探测点为 MCU_RGMII1_TXC、如果 RGMII 用于1000M 模式、则应为125MHz。
我发现了这个问题。
当 TDA4VH 的 RGMII 未连接到开关(引脚悬架状态)时、仅从 MCU_RGMII1_TXC 输出2.5MHz。
当 TDA4VH 的 RGMII 连接到开关时、输出为125MHz
我还有一个问题:
我要启用 RGMII 延迟、您能帮助我检查它是否正确吗?
代码:
Br
耶肯
您好、Jeken:
感谢您确认 TX 时钟查询现在已被应答。
对于 RGMII 延迟 配置、您共享的代码片段是必须执行此操作的正确位置。 默认情况下、该驱动器将 CTRLMMR_MCU_ENET_CTRL 位配置为4至1 (无内部发送延迟)。 但如果我们需要有内部传输延迟、我们需要清除此位。
谢谢。