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[参考译文] SK-AM64:CSPW 的裸机配置

Guru**** 1123190 points
请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1233980/sk-am64-baremetal-configuration-of-cspw

器件型号:SK-AM64

大家好

void InitializeEthernet()
{
    _mainpadconfig->PADCONFIG126 = BIT18|BIT16|0x4;//18MDIO
    _mainpadconfig->PADCONFIG127 = BIT16|0x4;//19MDC
    _mainpadconfig->PADCONFIG158 = BIT21|BIT18|BIT16|0x0;//EXTI

    _mainpadconfig->PADCONFIG71 = BIT21|BIT18|BIT16|0x4;
    _mainpadconfig->PADCONFIG74 = BIT21|BIT18|BIT16|0x4;
    _mainpadconfig->PADCONFIG84 = BIT21|BIT18|BIT16|0x4;
    _mainpadconfig->PADCONFIG85 = BIT21|BIT18|BIT16|0x4;
    _mainpadconfig->PADCONFIG51 = BIT21|BIT18|BIT16|0x4;
    _mainpadconfig->PADCONFIG54 = BIT21|BIT18|BIT16|0x4;
    _mainpadconfig->PADCONFIG73 = BIT16|0x4;
    _mainpadconfig->PADCONFIG75 = BIT16|0x4;
    _mainpadconfig->PADCONFIG76 = BIT16|0x4;
    _mainpadconfig->PADCONFIG83 = BIT16|0x4;
    _mainpadconfig->PADCONFIG55 = BIT16|0x4;
    _mainpadconfig->PADCONFIG56 = BIT16|0x4;

    _mainpadconfig->PADCONFIG66 = BIT21|BIT18|BIT16|0x2;
    _mainpadconfig->PADCONFIG67 = BIT21|BIT18|BIT16|0x2;
    _mainpadconfig->PADCONFIG68 = BIT21|BIT18|BIT16|0x2;
    _mainpadconfig->PADCONFIG69 = BIT21|BIT18|BIT16|0x2;
    _mainpadconfig->PADCONFIG70 = BIT21|BIT18|BIT16|0x2;
    _mainpadconfig->PADCONFIG72 = BIT21|BIT18|BIT16|0x2;
    _mainpadconfig->PADCONFIG77 = BIT16|0x2;
    _mainpadconfig->PADCONFIG78 = BIT16|0x2;
    _mainpadconfig->PADCONFIG79 = BIT16|0x2;
    _mainpadconfig->PADCONFIG80 = BIT16|0x2;
    _mainpadconfig->PADCONFIG81 = BIT16|0x2;
    _mainpadconfig->PADCONFIG82 = BIT16|0x2;

    _mainpadconfig->PADCONFIG98 = BIT16|0x7;
    _mcupadconfig->PADCONFIG5   = BIT16|0x7;

    SOC_moduleClockEnable(TISCI_DEV_CPSW0,1);
    SOC_moduleClockEnable(TISCI_DEV_DMASS0,1);

    for(uint32 i=0;i< (2 *100);i++);
    _cpsw->mdio.CONTROL &= (~0xFF | 99);
    _cpsw->mdio.CONTROL &= ~BIT31;
    _cpsw->mdio.CONTROL |= BIT24;
    _cpsw->mdio.CONTROL |= BIT30;

    uint16 phyregisters0[0x1DF];
    uint16 phyregisters1[0x1DF];
    uint32 status=0;

    for(uint32 i=0;i<0x1DF;i++)status = MDIO_phyExtRegRead((uint32)&_cpsw->mdio, NULL, 0, i, &phyregisters0[i]);
    phyregisters0[0x0000] |= BIT09;     status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 0, 0x0000, phyregisters0[0x0000]);
    phyregisters0[0x0018] = 0x2232;     status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 0, 0x0018, phyregisters0[0x0018]);
    phyregisters0[0x0032] |= BIT07;     status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 0, 0x0032, phyregisters0[0x0032]);
    phyregisters0[0x00E9] = 0xDF22;     status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 0, 0x00E9, phyregisters0[0x00E9]);
    phyregisters0[0x001F] = BIT14;      status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 0, 0x001F, phyregisters0[0x001F]);
    for(uint32 i=0;i< (200 *100);i++);

    for(uint32 i=0;i<0x1DF;i++)status = MDIO_phyExtRegRead((uint32)&_cpsw->mdio, NULL, 1, i, &phyregisters1[i]);
    phyregisters1[0x0000] |= BIT09;     status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 1, 0x0000, phyregisters1[0x0000]);
    phyregisters1[0x0018] = 0x2232;     status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 1, 0x0018, phyregisters1[0x0018]);
    phyregisters1[0x0032] |= BIT07;     status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 1, 0x0032, phyregisters1[0x0032]);
    phyregisters1[0x001F] = BIT14;      status = MDIO_phyExtRegWrite((uint32)&_cpsw->mdio, NULL, 1, 0x001F, phyregisters1[0x001F]);
    for(uint32 i=0;i< (200 *100);i++);

    volatile uint32 *CTRLMMR_ENET1_CTRL = ((volatile uint32*)(0x43004044));
    volatile uint32 *CTRLMMR_ENET2_CTRL = ((volatile uint32*)(0x43004048));
    *CTRLMMR_ENET1_CTRL = 2;
    *CTRLMMR_ENET2_CTRL = 2;

    _cpsw->control.CONTROL = BIT15|BIT14|BIT02;

    _cpsw->control.PTYPEREG = 0x2;

    _cpsw->control.VLANLTPYE = 0x88A88100;

    _cpsw->control.FREQUENCY = 250;

    _cpsw->control.P0RXMAXLEN = 1518;

    _cpsw->control.STATPORTEN =  BIT02|BIT01|BIT00;

    _cpsw->ale.CONTROL |=  BIT31;
    _cpsw->ale.CONTROL |=  BIT30;
    _cpsw->ale.CONTROL |=  BIT04;

    _cpsw->control.P0CONTROL|= BIT01|BIT00;
    _cpsw->control.P1CONTROL|= BIT01;
    _cpsw->control.P1SAL = 0xABCD;
    _cpsw->control.P1SAH = 0xCDEF0000;
    _cpsw->control.P1MACCONTROL = BIT24|BIT23|BIT22|BIT07;

}

我编写了上述代码来配置 CPSW。 焊盘配置和 MDIO 正常工作。 我已使用 PRUICSSG 对其进行了测试、并且 PRU 接收并发送数据正常。

现在、我将尝试使用 CPSW 而不是 PRU 来实现该目的

我不确定 CPSW 器件配置是否正确。 这些许多注册是否足以配置 CPSW 以接收数据、是否缺失任何数据、或者订单是否错误? 由于所有端口上的统计寄存器都是死区和0、因此即使以太网插孔接收到的 LED 闪烁、也不显示任何活动。

谢谢

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    尊敬的 

    感谢您的提问。

    我需要与开发团队合作来检查这一点。

    请允许我花点时间与您联系。

    此致

    Ashwani

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好!

    我玩了很多,发现了问题。 它实际上是 CPSW_PN_MAC_CONTROL_REG_k 的问题、在我的代码中它位于第89行、即 _cpsw->control.P1MACCONTROL。 显然我强制 MAC 进入千兆模式和统计数字来了活和开始递增。 以下是新寄存器配置

    _cpsw->control.P1MACCONTROL = BIT24|BIT23|BIT22|BIT17|BIT07|BIT05|BIT00;

    希望它对将来的某个人有所帮助