专家您好：
我们最近将 mcal 闪存驱动器调整为 indac 模式、但在调试过程中、我发现在使用 indac 模式时、OSPI_ind_xfer_mode_write 函数中调用的 CSL_ospiWriteFifoData 函数可将数据写入地址0x50000000。 
您能解释一下为什么 mcal 闪存驱动程序在 indac 模式下将数据写入这个内存段吗？
OSPI_IND_AHB_ADDR_TRIGGER_REG [/报价]OSPI_IND_AHB_ADDR_TRIGGER_REG 00000000
我认为函数 CSL_ospiWriteFifoData 中的代码 CSL_REG32_WR (indAddr、* srcPtr)行会触发对地址0x50000000的写入操作。 您能解释一下执行此操作的原因吗？
现在、OSPI 在使用 INDAC 模式的读取和写入操作中均能正常工作。
至于 mcal FLS 模块在0x50000000上的写入操作、我通过 Trace32中设置的写入断点来确定。 
您如何确认数据写入0x50000000。 另外，如果确实是这种情况，您可以确认数据是否被写入闪存？
帧、如下所示：
您好、Karan：
我们目前使用 INDAC 模式工作正常、这只是我的问题。
int32_t OspiFlash_xspiIndacWrite(App_OspiObj *ospiObj, uint8_t *buf, uint32_t numBytes, bool intrPollMode, uint32_t offset) /* based on OSPI_ind_xfer_mode_write_v0 in OSPI_v0.c */
{
int32_t status = OSPI_FLASH_APP_STATUS_SUCCESS;
uint8_t *pSrc; /* Source address */
uint32_t size;
uint32_t remainSize;
uint32_t totalSize;
uint32_t wrByte;
uint32_t sramLevel;
uint32_t blkNumOffset;
uint8_t cmdWren = OSPI_FLASH_CMD_WREN;
const CSL_ospi_flash_cfgRegs *baseAddr = (const CSL_ospi_flash_cfgRegs *)(OSPI_FLASH_CONFIG_REG_BASE_ADDR);
pSrc = (uint8_t *)buf;
remainSize = 0;
totalSize = (uint32_t)numBytes;
blkNumOffset = (uint32_t)(offset/OSPI_FLASH_DEVICE_BLOCK_SIZE);
/* Erase the region before writing */
OspiFlash_ospiEraseBlk(blkNumOffset, totalSize, FALSE);
while(totalSize>0)
{
size = totalSize < OSPI_FLASH_DEVICE_PAGE_SIZE ? totalSize : OSPI_FLASH_DEVICE_PAGE_SIZE;
OspiFlash_ospiXferIntrInit(intrPollMode);
OspiFlash_cmdWrite((const uint8_t *)&cmdWren, 1, NULL, 0, intrPollMode);
OspiFlash_waitReady(OSPI_FLASH_WRR_WRITE_TIMEOUT, intrPollMode);
/* Disable DAC mode */
CSL_ospiDacEnable(baseAddr, FALSE);
/* Set write address in indirect mode */
CSL_ospiIndSetStartAddr(baseAddr, (uint32_t)offset, FALSE);
if (intrPollMode) /* if interrupt mode is used then OSPI_hwiFxn will handle, if poll mode is used the below code will handle */
{
/* start the indirect write */
CSL_ospiIndWriteExecute(baseAddr, size);
remainSize = size;
while(remainSize > 0U)
{
/* Wait indirect write SRAM fifo level below watermark */
status = OSPI_waitWriteSramLvl(baseAddr,&sramLevel);
wrByte = (CSL_OSPI_SRAM_PARTITION_WR - sramLevel) * CSL_OSPI_FIFO_WIDTH; /* check if Macro is SoC specific */
wrByte = (wrByte > remainSize) ? remainSize : wrByte;
/* Write data to FIFO */
CSL_ospiWriteFifoData((uintptr_t)(OSPI_FLASH_DATA_BASE_ADDR), pSrc, wrByte); /* OSPI_FLASH_DATA_BASE_ADDR = MCU_FSS0_DAT_REG1 = 0x0050000000 */
pSrc += wrByte;
remainSize -= wrByte;
}
if(status == OSPI_FLASH_APP_STATUS_SUCCESS)
{
status = OSPI_waitIndWriteComplete(baseAddr);
}
if(status == OSPI_FLASH_APP_STATUS_ERROR)
{
CSL_ospiIndWriteCancel(baseAddr);
}
}
else
{
/* Book keeping of transmit and receive buffers */
ospiObj->writeBufIdx = (uint8_t *)pSrc;
ospiObj->writeCountIdx = (uint32_t)size;
ospiObj->readBufIdx = NULL_PTR;
ospiObj->readCountIdx = 0;
/* start the indirect write */
CSL_ospiIndWriteExecute(baseAddr, size);
/* To wait till write completes in interrupt mode? */
SemaphoreP_pend(ospiObj->ospiFlashTransferDoneSem, SemaphoreP_WAIT_FOREVER);
}
OspiFlash_waitReady(OSPI_FLASH_PAGE_PROG_TIMEOUT, FALSE);
pSrc += size;
offset += size;
totalSize -= size;
}
return status;
}
在该函数第52行中：
