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[参考译文] TMS320DM8148:适用于 MT41K128M16JT-125 IT K 的 TI814x-DDR3-Init-U-Boot

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请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1262904/tms320dm8148-ti814x-ddr3-init-u-boot-for-mt41k128m16jt-125-it-k

器件型号:TMS320DM8148

您好!

基于 ti-ezsdk_dm814x-evm_5_05_02_00、我的客户板将 DDR3替换为4个 MT41K128M16JT-125 IT K。

我正努力关注这样的点。 但大多数显示为灰色或无法下载。

https://rashkash103.github.io/ti-wiki/processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot.html

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/445754/adding-ddr3-changes-to-am33xx-soc itssearch-user-mt41k128m16jt-125-k-part-number?tisearch=e2e-sitesearch&keymatch=MT41K128M16JT-125#

https://rashkash103.github.io/ti-wiki/processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot_Wordwise_SWleveling.html

https://processors.wiki.ti.com/index.php/TI81XX_PSP_UBOOT_User_Guide

您是否提供完整文件以及让我尝试为 ddr_defs_ti814x.h 生成 DDR 相关参数的步骤、如下所示

/* TI814X DDR2 PHY CFG 参数 */
#define DDR2_PHY_RD_DQS_CS0_define (EMIF == 0)? 0x35:0x35)
#define DDR2_PHY_WR_DQS_CS0_define (EMIF == 0)? 0x20:0x20)
#define DDR2_PHY_RD_DQS_Gate_CS0_define (EMIF == 0)? 0x90:0x90)
#define DDR2_PHY_WR_DATA_CS0_define (EMIF == 0)? 0x50:0x50)
#define DDR2_PHY_CTRL_SLAVE_RATIO_CS0_define 0x80

/* TI814X DDR3 PHY CFG 参数 */
#define DDR3_PHY_RD_DQS_CS0_BYTE0 (EMIF == 0)? 0x37:0x3A)
#define DDR3_PHY_RD_DQS_CS0_BYTE1 (EMIF == 0)? 0x37:0x3C)
#define DDR3_PHY_RD_DQS_CS0_BYTE2 (EMIF == 0)? 0x33:0x38)
#define DDR3_PHY_RD_DQS_CS0_BYTE3 (EMIF == 0)? 0x33:0x34)

#define DDR3_PHY_WR_DQS_CS0_BYTE0 (EMIF == 0)? 0x41:0x48)
#define DDR3_PHY_WR_DQS_CS0_BYTE1 (EMIF == 0)? 0x48:0x4D)
#define DDR3_PHY_WR_DQS_CS0_BYTE2 (EMIF == 0)? 0x50:0x54)
#define DDR3_PHY_WR_DQS_CS0_BYTE3 (EMIF == 0)? 0x4F:0x51)

#define DDR3_PHY_RD_DQS_Gate_CS0_BYTE0 (EMIF == 0)? 0xEA:0xE1)
#define DDR3_PHY_RD_DQS_Gate_CS0_BYTE1 (EMIF == 0)? 0x119:0x103)
#define DDR3_PHY_RD_DQS_Gate_CS0_BYTE2 (EMIF == 0)? 0x11F:0x120)
#define DDR3_PHY_RD_DQS_Gate_CS0_BYTE3 (EMIF == 0)? 0x14F:0x149)

#define DDR3_PHY_WR_DATA_CS0_BYTE0 (EMIF == 0)? 0x8A:0x8F)
#define DDR3_PHY_WR_DATA_CS0_BYTE1 (EMIF == 0)? 0x87:0x87)
#define DDR3_PHY_WR_DATA_CS0_BYTE2 (EMIF == 0)? 0x87:0x83)
#define DDR3_PHY_WR_DATA_CS0_BYTE3 (EMIF == 0)? 0x7f:0x84)

/* TI814X DDR3 EMIF CFG 寄存器值533MHz */
#define DDR3_EMIF_READ_LATENCY 0x0017020B
#define DDR3_EMIF_TIM1 0x0EEF3723
#define DDR3_EMIF_TIM2 0x30AA7FE2
#define DDR3_EMIF_TIM3 0x50FFE56F
#define DDR3_EMIF_REF_CTRL 0x0000103D
#define DDR3_EMIF_SDRAM_CONFIG 0x61C122B2
#define DDR3_EMIF_SDRAM_ZQCR 0x50074BE1

此致,

加里