工具与软件：
您好！
SDK 版本：09.02.0.05
参考链接：
我们将 serdes2 lane2配置为 SGMII 7。
我的设备树配置：
// SPDX-License-Identifier: GPL-2.0 /** * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with * J7AHP board. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the * board. * * Product Datasheet: www.ti.com/.../spruj74.pdf * Product Link: www.ti.com/.../J721EXENETXPANEVM * * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; /plugin/; #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/mux/ti-serdes.h> #include <dt-bindings/phy/phy-cadence.h> #include <dt-bindings/phy/phy.h> #include "k3-pinctrl.h" &{/} { aliases { ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5"; ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6"; ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7"; }; }; &main_cpsw0 { status = "okay"; }; &main_cpsw0_port7 { status = "okay"; phy-handle = <&cpsw9g_phy0>; phy-mode = "sgmii"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>; phy-names = "mac", "serdes"; }; &main_cpsw0_mdio { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mdio0_pins_default>; bus_freq = <1000000>; reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; reset-post-delay-us = <120000>; #address-cells = <1>; #size-cells = <0>; cpsw9g_phy0: ethernet-phy@16 { reg = <0>; }; }; &exp2 { /* Power-up ENET1 EXPANDER PHY. */ qsgmii-line-hog { gpio-hog; gpios = <16 GPIO_ACTIVE_HIGH>; output-low; }; /* Toggle MUX2 for MDIO lines */ mux-sel-hog { gpio-hog; gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>; output-high; }; }; &main_pmx0 { mdio0_pins_default: mdio0-pins-default { pinctrl-single,pins = < J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */ >; }; }; &serdes_ln_ctrl { idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>, <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>, <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>, <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>, <J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>, <J784S4_SERDES2_LANE2_QSGMII_LANE7>, <J784S4_SERDES2_LANE3_QSGMII_LANE8>; }; &serdes_wiz2 { status = "okay"; }; &serdes2 { status = "okay"; #address-cells = <1>; #size-cells = <0>; serdes2_qsgmii_link: phy@0 { reg = <2>; cdns,num-lanes = <1>; #phy-cells = <0>; cdns,phy-type = <PHY_TYPE_SGMII>; resets = <&serdes_wiz2 3>; }; };
&main_cpsw0_port7｛
状态="正常"；
phy-handle =<&cpsw9g_phy0>；
PHY 模式="SGMII"；
MAC-ADDRESS =[00 00 00 00]；
phys =<&cpsw0_phy_gmii_sel 7>、<&serdes2_qsgmii_link>；
PHY-NAMEs ="MAC"、"SerDes"；
}；
节点的 PHY 模式会导致以下错误。
日志显示：
[2.687623] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA03102, cpsw version 0x6BA82902 Ports: 9 quirks: 000000000000
[ 2.700322] phy-gmii-sel 104044.phy：phy_gmii_sel_of_xlate id：7 ext：139780624
[ 2.701486] phy-gmii-sel 104044.phy：端口7：不支持的模式："SGMII"
我检查了驱动程序 phy-gmii-sel.c
静态常量
结构 phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 =｛
.use_of_data = true、
.regfields = phy_gmii_sel_fields_am654、
.extra_modes = bit (PHY_INTERFACT_MODE_QSGMII)|
位(PHY_INTERFACE_MODE_USXGMII)、
.NUM_PORTS = 8、
.num_qsgmii_main_ports = 2、
}；
似乎只有 j784s‘s EXTRA_MODES 不支持 SGMII。 在选择模式后、程序会退出。
case PHY_INTERFACE_MODE_QSGMII: if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_QSGMII))) goto unsupported; if (if_phy->priv->qsgmii_main_ports & BIT(if_phy->id - 1)) gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII; else gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII_SUB; break; case PHY_INTERFACE_MODE_SGMII: if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_SGMII))) goto unsupported; else gmii_sel_mode = J72XX_GMII_SEL_MODE_SGMII; break;
电流驱动器不支持 SGMII？
谢谢
