[参考译文] TDA4VM：TDA4VM RTOS 0806：Ethfw Loopbacken 测试

static int32_t Cpsw_isPortLinkUp(Cpsw_Handle hCpsw,
                                 Enet_MacPort macPort,
                                 bool *linked)
{
    int32_t status = ENET_SOK;
#if ENET_CFG_IS_ON(CPSW_SGMII)
    EnetPer_Handle hPer = (EnetPer_Handle)hCpsw;
    CSL_Xge_cpsw_ss_sRegs *ssRegs = (CSL_Xge_cpsw_ss_sRegs *)hPer->virtAddr2;
    uint32_t portNum = ENET_MACPORT_NORM(macPort);
    uint32_t portId = ENET_MACPORT_ID(macPort);
    EnetMod_Handle hMacPort = hCpsw->hMacPort[portNum];
    Enet_IoctlPrms prms;
    EnetMacPort_GenericInArgs macPortInArgs;
    EnetMacPort_Interface mii;
    EnetMac_LayerType enetLayer;
    EnetMac_SublayerType enetSublayer;
    bool sgmiiLink;
    uint32_t qsgmiiId;

    ENETTRACE_VAR(portId);
    status = EnetSoc_getMacPortMii(hPer->enetType, hPer->instId, macPort, &mii);
    ENETTRACE_ERR_IF(status != ENET_SOK, "Port %u: Failed to get ENET_CTRL: %d\n", portId, status);

    if (status == ENET_SOK)
    {
        enetLayer = mii.layerType;
        enetSublayer = mii.sublayerType;

        if (enetLayer == ENET_MAC_LAYER_GMII)
        {
            if (enetSublayer == ENET_MAC_SUBLAYER_SERIAL)
            {
                /* We have link status in CPSW subsystem regs as well as in SGMII regs,
                 * check SGMII regs as link status in CPSW subsystem regs is only for
                 * QSGMII link status */
                macPortInArgs.macPort = macPort;
                ENET_IOCTL_SET_INOUT_ARGS(&prms, &macPortInArgs, &sgmiiLink);
                status = EnetMod_ioctl(hMacPort, CPSW_MACPORT_IOCTL_GET_SGMII_LINK_STATUS, &prms);
                ENETTRACE_ERR_IF(status != ENET_SOK,
                                 "Port %u: Failed to get SGMII link state: %d\n", portId, status);
                *linked = sgmiiLink;
                printf("ZD goto ... func %s macPort %d ...Cpsw_isPortLinkUp IOCTL done sgmiiLink  %d\n",__func__,macPort,sgmiiLink);

            }
            else if ((enetSublayer == ENET_MAC_SUBLAYER_QUAD_SERIAL_MAIN) ||
                     (enetSublayer == ENET_MAC_SUBLAYER_QUAD_SERIAL_SUB))
            {

static void EthFwBoard_configSierra0Clks(void)
{
    uint32_t moduleId = TISCI_DEV_SERDES_16G0;
    uint32_t clkRateHz = 100000000U;
    uint32_t clkId[] = {
        TISCI_DEV_SERDES_16G0_CORE_REF1_CLK,
        TISCI_DEV_SERDES_16G0_CORE_REF_CLK};
    uint32_t clkParId[] = {
        TISCI_DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK,
        TISCI_DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK};
    uint32_t i;
    int32_t status;

    for (i = 0U; i < ENET_ARRAYSIZE(clkId); i++)
    {
        status = Sciclient_pmSetModuleClkParent(moduleId, clkId[i], clkParId[i], SCICLIENT_SERVICE_WAIT_FOREVER);
        if (status != CSL_PASS)
        {
            appLogPrintf("Failed to reparent clk %u: %d\n", clkId[i], status);
            EnetAppUtils_assert(false);
        }

        EnetAppUtils_clkRateSet(moduleId, clkId[i], clkRateHz);
    }

    EnetAppUtils_setDeviceState(moduleId, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0U);
}

[MCU2_0]     17.961974 s: APP: Syncing with 5 CPUs ... Done !!!
[MCU2_0]     17.962169 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]     17.963853 s: REMOTE_SERVICE: register service name [com.ti.remote_service_test]
[MCU2_0]     17.963928 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]     17.963969 s: REMOTE_SERVICE: register service name [rtos_test]
[MCU2_0]     17.964007 s: REMOTE_SERVICE: register service name [com.ti.perf_stats]
[MCU2_0]     17.964045 s: ETHFW: Init ... !!!
[MCU2_0]     17.964090 s: ZD goto ... func EthFwBoard_init
[MCU2_0]     18.001078 s: PMLIBClkRateSet failed for clock Id = 42
[MCU2_0]     18.001171 s: Assertion @ Line: 190 in enet_apputils_k3.c: false : failed !!!