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器件型号：TDA4VH-Q1 主题中讨论的其他器件：TDA4VH、 AM69A
工具与软件：
您好：
我使用 TDA4VH SERDES4为4个 Realtek RTL8211FS 以太网 SGMII PHY 芯片提供4个 LAN SGMII 信号。
现在、我可以 通过 MDIO 与 RTL8211FS PHY 通信。 但连接 MAIN_cpsw0和 Phy 之间的链路
未启动。 SEDES PLL 有时可以被锁定、但并非总是如此。 我使用 TI SDK "ti-processor-sdk-linux-am69-sk-10_00_07_06"
内核)。 您可以帮助我检查我的 DTS 文件设置吗？
非常感谢~
我的 DTS 设置：
// SPDX-License-Identifier: GPL-2.0 /* * DT Overlay for CPSW9G in SGMII mode using ROVY-M2-M-SGMII with ROVY-EVM board * * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ * Copyright 2024 Technexion Ltd. * * Author: Alex Fang <alex.fang@technexion.com> * */ /dts-v1/; /plugin/; #include <dt-bindings/mux/ti-serdes.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy-cadence.h> #include "k3-pinctrl.h" &{/} { model = "TechNexion ROVY-4VH and EVM baseboard with 4xSGMII"; aliases { ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5"; ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6"; ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7"; ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8"; }; }; &serdes_ln_ctrl { idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>, <J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_USB>, <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>, <J784S4_SERDES1_LANE2_PCIE2_LANE0>, <J784S4_SERDES1_LANE3_PCIE2_LANE1>, <J784S4_SERDES2_LANE0_IP4_UNUSED>, <J784S4_SERDES2_LANE1_IP4_UNUSED>, <J784S4_SERDES2_LANE2_IP4_UNUSED>, <J784S4_SERDES2_LANE3_IP4_UNUSED>, <J784S4_SERDES4_LANE0_QSGMII_LANE5>, <J784S4_SERDES4_LANE1_QSGMII_LANE6>, <J784S4_SERDES4_LANE2_QSGMII_LANE7>, <J784S4_SERDES4_LANE3_QSGMII_LANE8>; }; &serdes_wiz4 { status = "okay"; }; &serdes4 { #address-cells = <1>; #size-cells = <0>; status = "okay"; serdes4_sgmii_link: phy@0 { reg = <0>; resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, <&serdes_wiz4 3>, <&serdes_wiz4 4>; cdns,phy-type = <PHY_TYPE_SGMII>; cdns,num-lanes = <4>; #phy-cells = <0>; }; }; &main_cpsw0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mdio_pins_default>; }; &main_cpsw0_port1 { status = "disabled"; }; &main_cpsw0_port2 { status = "disabled"; }; &main_cpsw0_port3 { status = "disabled"; }; &main_cpsw0_port4 { status = "disabled"; }; &main_cpsw0_port5 { status = "okay"; phy-mode = "sgmii"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 5>, <&serdes4_sgmii_link>; phy-names = "mac", "serdes"; phy-handle = <&main_cpsw0_phy0>; }; &main_cpsw0_port6 { status = "okay"; phy-mode = "sgmii"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 6>, <&serdes4_sgmii_link>; phy-names = "mac", "serdes"; phy-handle = <&main_cpsw0_phy1>; }; &main_cpsw0_port7 { status = "okay"; phy-mode = "sgmii"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 7>, <&serdes4_sgmii_link>; phy-names = "mac", "serdes"; phy-handle = <&main_cpsw0_phy2>; }; &main_cpsw0_port8 { status = "okay"; phy-mode = "sgmii"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 8>, <&serdes4_sgmii_link>; phy-names = "mac", "serdes"; phy-handle = <&main_cpsw0_phy3>; }; &main_cpsw0_mdio { status = "okay"; bus_freq = <1000000>; #address-cells = <1>; #size-cells = <0>; main_cpsw0_phy0: ethernet-phy@4 { reg = <4>; reset-gpios = <&pca9554_sgmii 0 GPIO_ACTIVE_LOW>; reset-assert-us = <35000>; reset-deassert-us = <75000>; rtl821x,aldps-disable; rtl821x,clkout-disable; realtek,phy-mode-eee-disable; }; main_cpsw0_phy1: ethernet-phy@5 { reg = <5>; reset-gpios = <&pca9554_sgmii 1 GPIO_ACTIVE_LOW>; reset-assert-us = <35000>; reset-deassert-us = <75000>; rtl821x,aldps-disable; rtl821x,clkout-disable; realtek,phy-mode-eee-disable; }; main_cpsw0_phy2: ethernet-phy@6 { reg = <6>; reset-gpios = <&pca9554_sgmii 2 GPIO_ACTIVE_LOW>; reset-assert-us = <35000>; reset-deassert-us = <75000>; rtl821x,aldps-disable; rtl821x,clkout-disable; realtek,phy-mode-eee-disable; }; main_cpsw0_phy3: ethernet-phy@7 { reg = <7>; reset-gpios = <&pca9554_sgmii 3 GPIO_ACTIVE_LOW>; reset-assert-us = <35000>; reset-deassert-us = <75000>; rtl821x,aldps-disable; rtl821x,clkout-disable; realtek,phy-mode-eee-disable; }; }; &main_pmx0 { mdio_pins_default: mdio-pins-default { pinctrl-single,pins = < J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */ >; }; }; &main_i2c5 { /* I2C_E */ #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; pca9554_sgmii: pca9554_sgmii@27 { compatible = "nxp,pca9554"; reg = <0x27>; gpio-controller; #gpio-cells = <2>; status = "okay"; }; };
设计 PLL 锁定成功：
SEDES PLL 锁定失败：
此致
Alex Fang
