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器件型号：AM6442 工具与软件：
大家好！
我已经在使用捕获 上一篇文章的指示,但我想做它的中断. 它按照我收到的指导工作,但我仍然得到许多呼叫每秒(而不是一个)。 在两秒钟内说出>1M 的呼叫。
我尝试过的最重要的事情：
-不使用任务管理器,我认为中断7是有效的,但在我确认它后仍然得到激活
-仅配置捕获6.
我是否必须执行其他操作来确认该中断？ 共享相关代码。
此致。
inline void pad_config_aka_dtb() {
hw_wr_reg32(0x00a40034, 0x010016);
hw_wr_reg32(0x00a40038, 0x010016);
hw_wr_reg32(0x00a4003C, 0x010016);
hw_wr_reg32(0x00a40040, 0x010016);
// pin mux for LATCH_IN - time sync router PRG1_IEP0_EDC_LATCH_IN0
hw_wr_reg32(0x000F4100, 0x00040002);
// time sync router PRG1_IEP0_EDC_LATCH_IN1
// hw_wr_reg32(0x00a40028, 0x00010009);
}
void reset_counter_iep_IEP0() {
/* Disable counter */
CT_IEP0.global_cfg_reg_bit.cnt_enable = 0;
/* 64 bits */
CT_IEP0.cmp_cfg_reg_bit.shadow_en = 0;
/* Reset Count register */
CT_IEP0.count_reg0_bit.count_lo = 0;
CT_IEP0.count_reg1_bit.count_hi = 0;
/* Clear overflow status register */
CT_IEP0.global_status_reg_bit.cnt_ovf = 1;
}
void configure_counter_IEP0() {
CT_IEP0.global_cfg_reg_bit.default_inc = 4;
CT_IEP0.global_cfg_reg_bit.cnt_enable = 1;
CT_IEP0.cmp_cfg_reg_bit.cmp_en = 0; // enable compensation
CT_IEP0.compen_reg_bit.compen_cnt = 0; // count for compensation
CT_IEP0.global_cfg_reg_bit.cmp_inc = 0; // inc when compensation is active
CT_IEP0.slow_compen_reg_bit.slow_compen_cnt =
0; // Slow disabled when we enable compensation
CT_IEP0.cap_cfg_reg = 0x0003FFC0;
// CT_IEP0.cap_cfg_reg = 0x10000;
}
#define PRU1_0_TASK_MGR_REG_BASE (0x300aa000UL)
// This one calls ISR in C, after saving the registers.
extern void tm_ch4_send(void);
#define CSL_ICSS_G_PR1_IEP0_SLV_CAPR6_REG0 (0x00000050U)
volatile int count = 0;
inline void config_task_manager() {
// disable task manager, pru_io/firmware/common/icss_tm_macros.in
__asm(" TSEN 0;");
// clear event from previous debug.
hw_wr_reg32(PRU1_0_TASK_MGR_REG_BASE, 0x0fff);
asm(" xin 252, &r0.b3,1");
asm(" nop ");
asm(" nop ");
hw_wr_reg32(PRU1_0_TASK_MGR_REG_BASE, 0x0000);
// configure task manager for iep_task, TS2 is highest priority and can
// pre-empt TS1
// general purpose mode = 2,
// TS2_S0 = tm_ch4_send (bit 7)
hw_wr_reg32(PRU1_0_TASK_MGR_REG_BASE, 0x0182);
// // set address of tm_ch4_send
// // TS2_0
hw_wr_reg32(PRU1_0_TASK_MGR_REG_BASE + 0x1c, (unsigned int)tm_ch4_send);
// set TS2 trigger to
// S2_0 (bit 7-0) iep0_cmp0 = 16
// S2_1 (bit 15-8) iep0_cmp1 = 17
// 0x26 = 38, IEP_CAPR[0] event.
// 0x26 is the one we need.
hw_wr_reg32(PRU1_0_TASK_MGR_REG_BASE + 0x40, 0x1126);
// enable task manager
__asm(" TSEN 1;");
}
// Called from ASM
#pragma RETAIN(pps_isr)
void pps_isr() {
uint32_t reg2 = CT_IEP0.cap_status_reg;
uint32_t reg0 = CT_IEP0.capr6_reg0;
uint32_t reg1 = CT_IEP0.capr6_reg1;
*(icssg_shared_mem_) = 0;
*(icssg_shared_mem_ + 1) = count++;
*(icssg_shared_mem_ + 2) = reg0;
*(icssg_shared_mem_ + 3) = reg1;
*(icssg_shared_mem_ + 3) = reg2;
}
void main() {
reset_counter_iep_IEP0();
pad_config_aka_dtb();
configure_counter_IEP0();
config_task_manager();
*(icssg_shared_mem_) = 0;
*(icssg_shared_mem_ + 1) = 0;
*(icssg_shared_mem_ + 2) = 0;
*(icssg_shared_mem_ + 3) = 0;
*(icssg_shared_mem_ + 4) = 0;
while (1) {
}
}
; ----------------------------------------------------------------------------
; task tm_ch4_send
;
; ----------------------------------------------------------------------------
.global tm_ch4_send
.global pps_isr
TM_YIELD_XID .set 252
BANK0_ID .set 10
tm_ch4_send:
xout BANK0_ID, &r0, 120 ; save R0-r26
JAL r3.w2, ||pps_isr||
nop
xin TM_YIELD_XID, &R0.b3,1 ; exit task after two instructions/cycles
nop
xin BANK0_ID, &r0, 120 ; save R0-r26
nop
nop ; unreachable
nop ; unreachable
