Other Parts Discussed in Thread: AFE7950
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器件型号： AFE7950
您好、
我们在单次模式下生成 SYSREF 信号。 除了对齐转换器中的通道外、我们还希望从已知的时间轴确定地复位 AFE 中 NCO 的相位。 在 SYSREF 脉冲发生器模式下、通过使 LMK 上的 SYNC 引脚生效、SYSREF 信号从 LMK04828B 发送到 AFE7950。 我们从 FPGA 将 LMK 上的 SYNC 引脚置为有效。 SYNC 置为有效发生在 10MHz 的特定时间间隔上、但并非所有时间间隔。
我们担心 LMK04828B 的 SYNC 置为有效与 AFE 上的 LMFC 时钟不一致。 因此、我们尝试更改 Latte 中的 K（每个多帧参数的帧数）以使 LMFC 10MHz — 当我们将 SYNC 引脚置为有效时、它将与保持一致。 但是、我们注意到该工具不会接受我们的设置 K 高于 24 — 软件似乎迫使它回到 25。 为什么？
我们是否需要 LMFC 与 SYSREF 脉冲对齐？ 如果我们这样做、如何生成 LMFC 10MHz？
这是我们的配置文件：
############## Read me ##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 491.52M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_44210; Data Rate = 491.52M ---> To capture 4 RX channels
sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion
setupParams.skipFpga = True # setup FPGA (TSW14J56) using HSDC Pro
############## Top Level ##############
sysParams.FRef = 600
sysParams.FadcRx = 3000
sysParams.FadcFb = 3000
sysParams.Fdac = 12000
sysParams.externalClockRx=False
sysParams.externalClockTx=False
############## Digital Chain ##############
##### RX #####
sysParams.ddcFactorRx = [12,12,12,12] #DDC decimation factor for RX A, B, C and D
#sysParams.rxNco0 = [[9500,9500], #Band0, Band1 for RXA
# [9500,9500], #Band0, Band1 for RXB
# [9500,9500], #Band0, Band1 for RXC
# [9500,9500]] #Band0, Band1 for RXD
sysParams.rxNco0 = [[4000,4000], #Band0, Band1 for RXA
[4000,4000], #Band0, Band1 for RXB
[4000,4000], #Band0, Band1 for RXC
[4000,4000]] #Band0, Band1 for RXD
##### FB #####
sysParams.fbEnable = [False,False]
sysParams.ddcFactorFb = [12,12] #DDC decimation factor for FB 1 and 2
sysParams.fbNco0 = [4000,4000] #Band0 for FB1 and FB2
##### TX #####
sysParams.ducFactorTx = [48,48,48,48] #DUC interpolation factor for TX A, B, C and D
#sysParams.txNco0 = [[9500,9500], #Band0, Band1 for TXA
# [9500,9500], #Band0, Band1 for TXB
# [9500,9500], #Band0, Band1 for TXC
# [9500,9500]] #Band0, Band1 for TXD
sysParams.txNco0 = [[4000,4000], #Band0, Band1 for TXA
[4000,4000], #Band0, Band1 for TXB
[4000,4000], #Band0, Band1 for TXC
[4000,4000]] #Band0, Band1 for TXD
############## JESD ##############
##### ADC-JESD #####
sysParams.jesdSystemMode= [3,3]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb -fb
#SystemMode 1: 1R1F-FDD ; rx -rx -fb -fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx -rx -rx -rx
#SystemMode 4: 1F ; fb -fb- fb -fb
#SystemMode 5: 1R1F-TDD ; rx/fb-rx/fb-rx/fb-rx/fb
sysParams.jesdTxProtocol= [0,0] # 0 - 8b/10b encoding; 2 - 64b/66b encoding
sysParams.LMFSHdRx = ["24410","24410","24410","24410"]
# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["22210","22210"]
sysParams.rxJesdTxScr = [True,True,True,True]
sysParams.fbJesdTxScr = [True,True]
sysParams.rxJesdTxK = [16,16,16,16] # CANNOT CHANGE THIS TO 25???
sysParams.fbJesdTxK = [16,16]
sysParams.serdesTxLanePolarity =[0,0,0,0,1,0,1,0]
sysParams.jesdTxLaneMux = [2,3,6,7,0,1,4,5] # Enter which lanes you want in each location.
##### DAC-JESD #####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx = ["24410","24410","24410","24410"]
sysParams.serdesRxLanePolarity = [0,0,0,0,0,1,1,1]
sysParams.jesdRxLaneMux = [4,5,0,1,7,6,2,3] # Enter which lanes you want in each location.
#sysParams.jesdRxLaneMux = [0,1,2,3,4,6,7,5] # Enter which lanes you want in each location.
sysParams.jesdRxRbd = [4, 4]
sysParams.jesdRxScr = [True,True,True,True]
sysParams.jesdRxK = [16,16,16,16] # CANNOT CHANGE THIS TO 25???
##### JESD Common #####
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack = True #JESD Sync signal is connected to FPGA
############## GPIO ##############
sysParams.gpioMapping = {
'H8': 'ADC_SYNC0',
'H7': 'ADC_SYNC1',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'DAC_SYNC0',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
############## LMK Params ##############
lmkParams.lmkVcoFreq = 3000
lmkParams.xtalFreq = 122.88
lmkParams.sysrefFreq = 3000/1024
lmkParams.pllEn = True
lmkParams.inputClk = 480 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk = True
setupParams.fpgaRefClk = 125 # Should be equal to LaneRate/40 for TSW14J56
pathdz = "C:/"
#lmkParams.pllEn = False
#lmkParams.inputClk = 1000 # Valid only when lmkParams.pllEn = False
#lmkParams.lmkFrefClk = True
#setupParams.fpgaRefClk = 125 # Should be equal to LaneRate/40 for TSW14J56
############## Logging ##############
#logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.setFileName(pathdz+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x21 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1
device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
#added by dz
#PhaseOffset=int(90/(360/2^16))
#PhaseOffset=int(32768)
#device.writeReg(0x12,0x2)
#device.writeReg(0xE1,(PhaseOffset>>8)&0xFF)
#device.writeReg(0xE0,PhaseOffset&0xFF)
#device.writeReg(0x12,0x0)
lmklogDumpInst=mLogDump.logDump(pathdz+r"\Afe79xxPg1_LMK.txt")
lmklogDumpInst.logFormat=0x21
lmk.logClassInst = lmklogDumpInst
lmk.rawWriteLogEn=1
setupParams.skipLmk = False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()
谢谢