[参考译文] AFE7950：环回脉冲相位变化

admin

Other Parts Discussed in Thread: AFE7950

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1604584/afe7950-loopback-pulse-phase-variation

器件型号： AFE7950

您好、

我们在 MIMO 脉冲雷达应用中使用 AFE7950。在启用具有 AFE7950 的定制 PCBA 时、我们会通过同轴电缆将 AFE7950 上 D/A 通道的输出环回到其 A/D 输入。在我们的脉冲雷达应用中、返回信号与传输信号的相位关系至关重要。

遗憾的是、在这种环回配置中、我们注意到输出信号与我们在返回时测量的信号之间有很大的相位可变性。我们已经确定、激励 TI204C IP 的 D/A 发送侧的数字信号相位在不同触发条件下是一致的。但是、来自 A/D 的返回信号与输出信号相比具有本质上是随机的相位。请参阅以下屏幕截图。我还附加了 Latte 配置。我们担心 DUC/DDC 的 NCO 与采样时钟相比可以自由运行、并且/或者 SYSREF 脉冲未复位抽取和内插计数器。我们在脉冲 SYSREF 模式下运行。停止 SYSREF 脉冲对相位可变性的影响极小。通常、我们在发送传出 D/A 脉冲之前发送 SYSREF 脉冲。

在每个屏幕截图中、您都会注意到捕获信号的相位差异很大。显示的信号是来自 AFE7950 ADC 的 RX 信号。捕获是通过在信号的上升沿触发逻辑分析仪来完成的、该逻辑分析仪向 Ti204C IP 的 TX 半部启动输出脉冲。如上所述、我们已经建立了从触发器到发出输出脉冲的一致相位。但是、在返回信号上通过环回同轴电缆使用相同的触发器时、我们看不到信号相位一致。如果相位被简单地抵消,这是可以接受的,然而,它在脉冲间是不一致的,这对我们的应用是严重的。

ConfigLmk_int_clk_3xx.zip

我们使用示波器测量到达 AFE7950 的 SYSREF 脉冲与 AFE7950 参考时钟的时序、我们认为已经满足 50ps 的建立和保持要求。但是、我们注意到在 LMK04828B 上（这是 AFE7950 和 TI204C FPGA IP 的参考时钟和 SYSREF 原点）置位 SYNC 引脚与 FPGA 中出现的 SYSREF 脉冲之间存在一些插入延迟差异。我们使用 LMK04828B 作为时钟 IC。我在下面提供了 Rx 和 Tx 时钟分配图。我还附上了 Latte 配置文件。

##############		Read me			##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 491.52M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_44210; Data Rate = 491.52M ---> To capture 4 RX channels

sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion

setupParams.skipFpga = True  # setup FPGA (TSW14J56) using HSDC Pro 
##############		Top Level			##############
sysParams.FRef			= 500
sysParams.FadcRx		= 3000
sysParams.FadcFb		= 3000
sysParams.Fdac			= 12000
sysParams.externalClockRx=False
sysParams.externalClockTx=False
													
##############		Digital Chain		##############

		#####	RX	#####
sysParams.ddcFactorRx	=	[12,12,12,12]				#DDC decimation factor for RX A, B, C and D
#sysParams.rxNco0		= 	[[9500,9500],			#Band0, Band1 for RXA 
#							[9500,9500],        		#Band0, Band1 for RXB 
#							[9500,9500],        	#Band0, Band1 for RXC 
#							[9500,9500]]        	#Band0, Band1 for RXD 
sysParams.rxNco0		= 	[[4000,4000],			#Band0, Band1 for RXA 
							[4000,4000],        		#Band0, Band1 for RXB 
							[4000,4000],        	#Band0, Band1 for RXC 
							[4000,4000]]        	#Band0, Band1 for RXD 

		#####	FB	#####
sysParams.fbEnable		=	[False,False]
sysParams.ddcFactorFb	=	[12,12]					#DDC decimation factor for FB 1 and 2
sysParams.fbNco0		= 	[4000,4000]				#Band0 for FB1 and FB2 

		#####	TX	#####
sysParams.ducFactorTx	=	[48,48,48,48]			#DUC interpolation factor for TX A, B, C and D
#sysParams.txNco0		= 	[[9500,9500],			#Band0, Band1 for TXA 
#							[9500,9500],        		#Band0, Band1 for TXB 
#							[9500,9500],        	#Band0, Band1 for TXC 
#							[9500,9500]]        	#Band0, Band1 for TXD
sysParams.txNco0		= 	[[4000,4000],			#Band0, Band1 for TXA 
							[4000,4000],        		#Band0, Band1 for TXB 
							[4000,4000],        	#Band0, Band1 for TXC 
							[4000,4000]]        	#Band0, Band1 for TXD


##############		JESD		##############

		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [3,3]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [0,0]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdRx		= ["24410","24410","24410","24410"]
													# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
													# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb		= ["22210","22210"]

sysParams.rxJesdTxScr	= [True,True,True,True]
sysParams.fbJesdTxScr	= [True,True]

sysParams.rxJesdTxK		= [16,16,16,16]
sysParams.fbJesdTxK		= [16,16]

sysParams.serdesTxLanePolarity =[0,0,0,0,1,0,1,0]
sysParams.jesdTxLaneMux	= [2,3,6,7,0,1,4,5]			# Enter which lanes you want in each location. 

		#####	DAC-JESD	#####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx		= ["24410","24410","24410","24410"]
sysParams.serdesRxLanePolarity   = [0,0,0,0,0,1,1,1]
sysParams.jesdRxLaneMux          = [4,5,0,1,7,6,2,3]			# Enter which lanes you want in each location.
#sysParams.jesdRxLaneMux          = [0,1,2,3,4,6,7,5]			# Enter which lanes you want in each location.

sysParams.jesdRxRbd		= [4, 4]
sysParams.jesdRxScr		= [True,True,True,True]
sysParams.jesdRxK		= [16,16,16,16]

		#####	JESD Common	#####
	
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack	= True	#JESD Sync signal is connected to FPGA

##############		GPIO		##############
sysParams.gpioMapping	= {
						'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

sysParams.continuousSysref = False
##############		LMK Params		##############
lmkParams.lmkVcoFreq = 3000
lmkParams.xtalFreq = 122.88
lmkParams.sysrefFreq = 3000/1024

lmkParams.pllEn			= True
lmkParams.inputClk		= 480 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= True
setupParams.fpgaRefClk	= 125 # Should be equal to LaneRate/40 for TSW14J56

pathdz = "C:/Users/DougZielinski/Documents/Texas Instruments/AFE79xxLatte/lib/"

#lmkParams.pllEn			= False
#lmkParams.inputClk		= 1000 # Valid only when lmkParams.pllEn = False
#lmkParams.lmkFrefClk	= True
#setupParams.fpgaRefClk	= 125 # Should be equal to LaneRate/40 for TSW14J56

##############		Logging		##############
#logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.setFileName(pathdz+r"\Afe79xxPg1.txt")
#logDumpInst.logFormat=0x21 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
#logDumpInst.logFormat=0x2000 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.logFormat=0x40 #Phil wants this one.  Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1

device.delay_time = 0
#-------------------------------------------------------------------------------------------------#

#added by dz
#PhaseOffset=int(90/(360/2^16))
#PhaseOffset=int(32768)
#device.writeReg(0x12,0x2)
#device.writeReg(0xE1,(PhaseOffset>>8)&0xFF)
#device.writeReg(0xE0,PhaseOffset&0xFF)
#device.writeReg(0x12,0x0)

lmklogDumpInst=mLogDump.logDump(pathdz+r"\Afe79xxPg1_LMK.txt")
lmklogDumpInst.logFormat=0x21
lmk.logClassInst = lmklogDumpInst
lmk.rawWriteLogEn=1

setupParams.skipLmk = False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = True
AFE.LMK.lmkConfig()

4 个月前

射频与微波（参考译文帖）

射频与微波（参考译文帖）(Read Only)

[参考译文] AFE7950：环回脉冲相位变化