[参考译文] AFE7950EVM：AFE7950EVM 上的 LMK04828 配置和时钟问题

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https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1635219/afe7950evm-issue-with-lmk04828-configuration-and-clocking-on-afe7950evm

器件型号： AFE7950EVM
主题： LMK04828 中讨论的其他器件

您好、

在评估 AFE7950EVM 电路板时、我目前正在努力配置 AFE 和 LMK 模块（下面随附了脚本）。目前、AFE 未接收到时钟信号。我怀疑 LMK 模块可能未正确配置。

为了进行此调试、我使用示波器探测了 SPI 信号。我观察到 LMK_SCK 和 LMK_SDIO 正在切换、但 LMK_CS 保持低电平且 LMK_SDO 保持高电平。此外、我知道 LMK_SDO 与 LMK04828 的复位信号相关联、是一个输出。基于此、假设 LMK04828 可能仍处于复位状态是否正确？

您能否确认我的调试方法是否合适？如果是、
如何使 LMK04828 退出复位状态？
2.是否可能缺少任何所需的配置命令？
是否需要特定的 Python 命令或序列来正确初始化 LMK 模块？

感谢您的支持。

#fpgaside 24410 afeside 12410 1 inst's are there
##############		Read me			##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 245.76M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_44210; Data Rate = 245.76M ---> To capture 4 RX channels

sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion

setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro 
##############		Top Level			##############
sysParams.FRef			= 491.52
sysParams.FadcRx		= 2949.12
sysParams.FadcFb		= 2949.12
sysParams.Fdac			= 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
													
##############		Digital Chain		##############

		#####	RX	#####
sysParams.ddcFactorRx	=	[12,12,12,12]			#DDC decimation factor for RX A, B, C and D
sysParams.rxEnable		=   [True,True,False,False]
sysParams.rxNco0		= 	[[1500,1500],			#Band0, Band1 for RXA 
							[1500,1500],        	#Band0, Band1 for RXB 
							[1500,1500],        	#Band0, Band1 for RXC 
							[1500,1500]]        	#Band0, Band1 for RXD  

		#####	FB	#####
sysParams.fbEnable		=	[False,False]
sysParams.ddcFactorFb	=	[12,12]					#DDC decimation factor for FB 1 and 2
sysParams.fbNco0		= 	[9500,9500]				#Band0 for FB1 and FB2 

		#####	TX	#####
sysParams.ducFactorTx	=	[48,48,48,48]			#DUC interpolation factor for TX A, B, C and D
sysParams.txEnable		=   [True,True,False,False]
sysParams.txNco0		= 	[[1500,1500],			#Band0, Band1 for TXA 
							[1500,1500],        	#Band0, Band1 for TXB 
							[1500,1500],        	#Band0, Band1 for TXC 
							[1500,1500]]        	#Band0, Band1 for TXD


##############		JESD		##############

		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [3,3]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [0,0]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdRx		= ["24410","24410","24410","24410"]   #changed by Lakshmi ["44210","44210","44210","44210"] 
													# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
													# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb		= ["24410","24410"]

sysParams.rxJesdTxScr	= [True,True,True,True] 
sysParams.fbJesdTxScr	= [True,True]

sysParams.rxJesdTxK		= [16,16,16,16]
sysParams.fbJesdTxK		= [16,16]

sysParams.jesdTxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location. 
													# For example, if you want to exchange the first two lines of each 2T,
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.serdesTxLanePolarity = [1,1,0,0,1,1,0,0]	########## newly added
sysParams.jesdTxRbd		= [2, 2] 					########## newly added
		#####	DAC-JESD	#####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx		= ["24410","24410","24410","24410"]  
sysParams.jesdRxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location.
sysParams.serdesRxLanePolarity = [1,1,0,0,0,0,0,0]													# For example, if you want to exchange the first two lines of each 2R
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd		= [2, 2] 					########## changed
sysParams.jesdRxScr		= [True,True,True,True]
sysParams.jesdRxK		= [16,16,16,16]

		#####	JESD Common	#####
	
sysParams.jesdABLvdsSync= False
sysParams.jesdCDLvdsSync= False
sysParams.syncLoopBack	= True	#JESD Sync signal is connected to FPGA

##############		GPIO		##############
sysParams.gpioMapping	= {
						'H8': 'ADC_SYNC0',
						'H7': 'DAC_SYNC0',  	#'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'ADC_SYNC1',		#'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

##############		LMK Params		##############
lmkParams.pllEn			= True
lmkParams.inputClk		= 983.04 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= True
setupParams.fpgaRefClk	= 245.76 # Should be equal to LaneRate/40 for TSW14J56

##############		Logging		##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x21 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1
lmk.rawWriteLogEn = 1

device.delay_time = 0
#--------------------------------------#
setupParams.skipLmk	=	False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()

## Initiates AFE79xx Bring-up
setupParams.skipLmk	= True 
AFE.deviceBringup()

AFE.TOP.overrideTdd(15,3,15)