Other Parts Discussed in Thread: AFE7950
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器件型号： AFE7950EVM
主题中讨论的其他器件： AFE7950
您好、
我们目前正在使用 AFE7950 EVM 板、并已使用 Latte 工具成功实现 JESD 通信。 我们能够在通过 Latte 配置器件时观察到噪声和斜坡数据。
为了将配置迁移到 FPGA 平台、我们使用了 Python 脚本生成 SPI 命令文件。 然后、我们将这些命令转换为 C 文件、并使用它们从 FPGA 控制 AFE7950 和 LMK 器件。但是、通过 FPGA 应用相同的配置后、即使启用了斜坡模式、我们也无法观察到预期的噪声或斜坡数据输出。 我们仔细地将 Latte 生成的 SPI 命令文件与我们的 SPI 命令 C 文件进行了比较、没有发现任何差异。
在生成的 SPI 命令文件中、一些延迟命令我们将其解释为毫秒。
但我们不确定它是否正确。 您能否确认？
delaySec (0.001000)； — 在 SPI 命令文件中
usleep(1000 ); -我们正在使用什么
有人能帮助我们了解导致此问题的原因吗？ 我们附加了 Python 脚本和生成的 SPI 命令文件以供参考。
如果您有任何建议或故障排除指导、我们将不胜感激。
#fpgaside 24410 afeside 12410 1 inst's are there
############## Read me ##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 245.76M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_44210; Data Rate = 245.76M ---> To capture 4 RX channels
sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion
setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro
############## Top Level ##############
sysParams.FRef = 491.52
sysParams.FadcRx = 2949.12
sysParams.FadcFb = 2949.12
sysParams.Fdac = 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
############## Digital Chain ##############
##### RX #####
sysParams.ddcFactorRx = [12,12,12,12] #DDC decimation factor for RX A, B, C and D
sysParams.rxEnable = [True,True,False,False]
sysParams.rxNco0 = [[1500,1500], #Band0, Band1 for RXA
[1500,1500], #Band0, Band1 for RXB
[1500,1500], #Band0, Band1 for RXC
[1500,1500]] #Band0, Band1 for RXD
##### FB #####
sysParams.fbEnable = [False,False]
sysParams.ddcFactorFb = [12,12] #DDC decimation factor for FB 1 and 2
sysParams.fbNco0 = [9500,9500] #Band0 for FB1 and FB2
##### TX #####
sysParams.ducFactorTx = [48,48,48,48] #DUC interpolation factor for TX A, B, C and D
sysParams.txEnable = [True,True,False,False]
sysParams.txNco0 = [[1500,1500], #Band0, Band1 for TXA
[1500,1500], #Band0, Band1 for TXB
[1500,1500], #Band0, Band1 for TXC
[1500,1500]] #Band0, Band1 for TXD
############## JESD ##############
##### ADC-JESD #####
sysParams.jesdSystemMode= [3,3]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb -fb
#SystemMode 1: 1R1F-FDD ; rx -rx -fb -fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx -rx -rx -rx
#SystemMode 4: 1F ; fb -fb- fb -fb
#SystemMode 5: 1R1F-TDD ; rx/fb-rx/fb-rx/fb-rx/fb
sysParams.jesdTxProtocol= [0,0] # 0 - 8b/10b encoding; 2 - 64b/66b encoding
sysParams.LMFSHdRx = ["24410","24410","24410","24410"] #changed by Lakshmi ["44210","44210","44210","44210"]
# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["24410","24410"]
sysParams.rxJesdTxScr = [True,True,True,True]
sysParams.fbJesdTxScr = [True,True]
sysParams.rxJesdTxK = [16,16,16,16]
sysParams.fbJesdTxK = [16,16]
sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2T,
# this should be [[1,0,2,3],[5,4,6,7]]
sysParams.serdesTxLanePolarity = [1,1,0,0,0,0,0,0] ########## newly added
#sysParams.jesdTxRbd = [2, 2] ########## newly added
##### DAC-JESD #####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx = ["24410","24410","24410","24410"]
sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location.
sysParams.serdesRxLanePolarity = [1,1,0,0,0,0,0,0] # For example, if you want to exchange the first two lines of each 2R
# this should be [[1,0,2,3],[5,4,6,7]]
#sysParams.jesdRxRbd = [2, 2] ########## changed
sysParams.jesdRxScr = [True,True,True,True]
sysParams.jesdRxK = [16,16,16,16]
##### JESD Common #####
sysParams.jesdABLvdsSync= False
sysParams.jesdCDLvdsSync= False
sysParams.syncLoopBack = True #JESD Sync signal is connected to FPGA
############## GPIO ##############
sysParams.gpioMapping = {
'H8': 'ADC_SYNC0',
'H7': 'DAC_SYNC0', #'ADC_SYNC1',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'ADC_SYNC1', #'DAC_SYNC0',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
############## LMK Params ##############
lmkParams.pllEn = True
lmkParams.inputClk = 983.04 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk = True
setupParams.fpgaRefClk = 245.76 # Should be equal to LaneRate/40 for TSW14J56
############## Logging of LMK SPI config ##############
#lmklogDumpInst=mLogDump.logDump(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1_LMK.txt")
#lmklogDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1_LMK.txt")
#lmklogDumpInst.logFormat=0x1
#lmk.logClassInst = lmklogDumpInst
#lmk.rawWriteLogEn=1
##################### logging of AFESPI config ############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x21 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1
lmk.rawWriteLogEn = 1
device.delay_time = 0
#--------------------------------------#
setupParams.skipLmk = False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()
#-------------------------------------------------------------------------------------------------#
#sysParams.dacJesdConstantTestPatternValue =10000
#AFE.adcDacSync()
#AFE.selectCh(0,0) it will check for RXA channel
#device.readReg(0x03)
#AFE.deviceBringup()
#AFE.TOP.overrideTdd(15,3,15) # bit-wise; 4R,2F,4T
#setupParams.skipLmk = 1
#AFE.deviceBringup()
#AFE.TOP.overrideTdd(15,3,15)
#setupParams.skipLmk = 0
## Initiates AFE79xx Bring-up
setupParams.skipLmk = True
AFE.deviceBringup()
AFE.TOP.overrideTdd(15,3,15)