[参考译文] AFE7700：JESD 回路模式启用

Oleksii、

我们将对此进行研究。

此致、

Jim

大家好、Jim！

`ve，我将 Lib 更新为 2.20版，并对配置和脚本正确性有更多的疑问。

硬件说明：FPGA 连接到 SRX1-4、STX1-4 (所有通道均不反相)、双向1 LVDS 同步

我的强制目标：全速率2949.12MHz；9.83Gbps 串行器/解串器速度、8b/10b 编码、通道1-4、TDD 模式上的 DAC 和 ADC 数据速率254.76M。

我的可选目标是 在 DAC 运行期间获得来自 FB 的数据( 如果需要、可以修改电路板并连接 TX/RX 信号)。 `s 可能、优化功耗以使用单个 JESD 内核。

以下是当前脚本版本：

setupParams.selectedDut=1
if boardType in ("EVM","HSC1373"):
	if setupParams.selectedDut==1:
		AFE=AFE1
		device=device1
		logDumpInst=logDumpInst1
	else:
		AFE=AFE0
		device=device0
		logDumpInst=logDumpInst0
else:
	setupParams.selectedDut=0
	
sysParams=AFE.systemParams
device.hardReadAlways=False
##### System Parameters
sysParams.FRef                  = 245.76#368.64#
sysParams.Fs                    = 2949.12#56*61.44#3440.64#
sysParams.pllMuxModes			= 0	
										#0: 4T4R Mode with PLL0 as Master. PLL 0 for all the LOs.
										#1: 4T4R Mode with PLL2 as Master. PLL 2 for all the LOs.
										#2: 4T4R FDD Mode. PLL0 for TX and PLL2 for RX.
										#3: 2*2T2R FDD Mode: PLL0 AB-TX;PLL3 AB-RX; PLL2 CD TX; PLL4 CD RX
										#4: 2T2R FDD - TDD Mode: PLL0 AB-TX; PLL3-AB-RX; PLL2 CD
sysParams.useSpiSysref			= False
# LO Settings
sysParams.pllLo					= [3500.01,sysParams.Fs,3501.06,1800.24,3400.0]	#PLL Frequencies for PLLs [0,1,2,3,4]#4899.9825
sysParams.jesdLoopbackEn		= 0		#Make it 1 to Enable the JESDTX to JESDRX internal loopback

## In below parameters, first in the array is for first 2T2R1F and second 2T2R1F.
# JESD and Serdes Parameters
sysParams.LMFSHdRx                = ["24410","24410"] 
sysParams.LMFSHdFb                = ["12410","12410"]
sysParams.LMFSHdTx                = ["24410","24410"] #["24410","24410"]
sysParams.systemMode              = [2,2]					# 0-Identical, 1-FDD, 2-TDD
sysParams.dedicatedLaneMode       = [1,1]
sysParams.jesdProtocol            = 0#1#0				# -0:B; 1:H; 2:C
sysParams.serdesFirmware		  =r"C:\\Users\\sa\\Documents\\Texas Instruments\\Latte\\lib\\Afe77xxLibraries\\AFE77xxLibraryPG1P1\\resourceFiles\\with_rom.fw.d04a4d.bin" #False#True#""					# If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
sysParams.jesdTxLaneMux			= [0,1,2,3,4,5,6,7]	# RX1,RX2,RX3,RX4,FB1,FB2 # Enter which lanes you want in each location. 
															# Note that across 2T Mux is not possible in 0.5.
															# For example, if you want to exchange the first two lines of each 2T, this should be [1,0,2,3,5,4,6,7]
sysParams.jesdRxLaneMux			= [0,1,4,5,2,3,6,7]	# TX1,TX2,TX3,TX4,NA,NA, NA, NA	# Enter which lanes you want in each location.
															# Note that across 2R Mux is not possible in 0.5.
sysParams.serdesTxLanePolarity	= [0,0,0,0,0,0,0,0] 
sysParams.serdesRxLanePolarity	= [0,0,0,0,0,0,0,0] 										# For example, if you want to exchange the first two lines of each 2R, this should be 
sysParams.jesdRxRbd				= [15, 15]
sysParams.jesdScr				= [True,True]		# Does the Same config for JESD TX and RX
sysParams.jesdK					= [16,16] 
sysParams.lowIfNcoRx			=	[0,0]
sysParams.lowIfNcoTx			=	[0,0]
sysParams.lowIfNcoFb			=	[0,0]

# Decimation and interpolation Parameters
sysParams.ducFactorTx				= [12, 12]#[14, 14]#[28./3,28./3]#[7, 7]#
sysParams.ddcFactorRx				= [12, 12]#[14, 14]#
sysParams.ddcFactorFb				= [12, 12]#[7, 7]#
sysParams.fbNco						= [3500.01,3500.01]#[4899.9825, 4899.9825]

sysParams.setTxLoFbNcoFreqForTxCalib	= True#False#		# Note that if this is True, the fbNcoValues entered above will be overwritten and fbNCO and LO values will be chosen to the closest supported values.
sysParams.txIqMcCalibMode=2		# 0 -Single Fb Mode FB AB ; 1 -Single Fb Mode FB CD ; 2- Dual Fb_Mode
sysParams.customerConfig			= False#True

LMKParams.pllEn			=	True					# If this is True, it takes the onboard oscillator as input to PLL and all clocks are generated from it. If it is False, it takes the external clock input of frequency - lmkParams.inputClk and generates the required clocks through dividers (No LMK PLL will be used).
LMKParams.lmkFrefClk	=	True
#LMKParams.inputClk		=	1474.56#1290.24#
LMKParams.sysrefFreq	=	0.96
sysParams.bitFileType=0			#0-Regular. 1- Same clock rate to FPGA 2 inputs. 2-8-Lane codes
'''
sysParams.jesdTxRxABSyncMux		= 0 
sysParams.jesdTxRxCDSyncMux		= 0 
sysParams.jesdTxFBABSyncMux		= 0 
sysParams.jesdTxFBCDSyncMux		= 0 
sysParams.jesdRxABSyncMux		= 0 
sysParams.jesdRxCDSyncMux		= 0 
sysParams.jesdABLvdsSync		= 1
sysParams.jesdCDLvdsSync		= 1
'''
if simulationMode==False:
	setupParams.skipFpga=1
	setupParams.skipLmk=0
AFE.skipRxConfig=0
AFE.skipFbConfig=0
AFE.skipTxConfig=0
AFE.skipAgc=1

sysParams.enableRxDsaFactoryCal 		= False
sysParams.enableTxDsaFactoryCal 		= False
sysParams.enableTxIqmcLolTrackingCorr = False
sysParams.enableRxIqmcLolTrackingCorr = True

logDumpInst.setFileName("D:\\AFE77xx_config\\configfixSysrefLB.txt")
logDumpInst.logFormat=0x07
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1

device.optimizeWrites=1
device.rawWriteLogEn=1
device.rewriteFile=1
#myfpga.rawWriteLogEn=0
lmk.rawWriteLogEn=1

AFE.initializeConfig()
AFE.deviceBringup()

AFE.TOP.overrideTdd(1, 1, 1)

device.rawWriteLogEn=1
myfpga.rawWriteLogEn=0
lmk.rawWriteLogEn=0

engine.sampleNo=32768

现在、DAC 配置为2条链路、每个链路有2条信道。 如果从 FPGA 路由1个差分同步信号、是否应切换到1个链路4通道？

 `ve、对于1个链路4通道、我要将 sysParams.LMFSHdTx 定义为[48410"、"48410"] 同时将 jesdRxLaneMux 恢复为[1、2、3、4、5、6、7、8]。要 期望为 DAC 数据使用 SRX1-4通道、我对吗？  

ADC 方面：

`ve 我仅连接到 FPGA 的 STX1-4、因此我需要正确映射那里的数据。 `m、我使用专用通道标志将 FB 链路路布置到 STX5、6、并为 SYNC 信号选择未使用的引脚。 是否允许去掉 FB、使 RX 通道保持正常运行？

在4RX 和2FB 通道之间共享前4个串联通道以处理它们时应采用什么策略(显然涉及 GPIO 控制)、在  这种情况下、必须如何编写脚本？

谢谢。

您的快速响应将极大地帮助我们 ！

您好 、Oleksii、

我正在处理这个。 我将在星期五之前收到更新。  

此致、

Vijay

你好！ 仍在等待您的更新。

此致、

Oleksii Shuko