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尊敬的 TI 团队:
我在将 AFE7950EVM 与 TSW14J57EVM 配合使用时发现了基波附近的杂散
输入频率= 9610MHz、电平=-13.1dBFS
因为我看到基频附近的文本"杂散"、所以我放大窗口
再次放大
最大值为-70.5dBFS、基波为-13.1dBFS
SFDR 为-13.1 (-70.5)= 57.4dBc、对吗?
将 AFE7950EVM 与 TSW14J57EVM 配合使用时是否正常?
Latte 启动文件(OnboardClk_RX_250m)
############## Read me ############## #In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 491.52M #In HSDC Pro ADC tab, Select AFE79xx_2x2RX_24410; Data Rate = 245.76M ---> To capture 4 RX channels #In HSDC Pro ADC tab, Select AFE79xx_1x2FB_44210; Data Rate = 491.52M ---> To capture 2 FB channels sysParams=AFE.systemParams sysParams.__init__();sysParams.chipVersion=chipVersion setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro ############## Top Level ############## sysParams.FRef = 491.52 sysParams.FadcRx = 2949.12 sysParams.FadcFb = 2949.12 sysParams.Fdac = 2949.12*4 sysParams.externalClockRx=False sysParams.externalClockTx=False ############## Digital Chain ############## ##### RX ##### sysParams.ddcFactorRx = [12,12,12,12] #DDC decimation factor for RX A, B, C and D sysParams.rxNco0 = [[9500,9500], #Band0, Band1 for RXA [9500,9500], #Band0, Band1 for RXB [9500,9500], #Band0, Band1 for RXC [9500,9500]] #Band0, Band1 for RXD ##### FB ##### sysParams.ddcFactorFb = [6,6] #DDC decimation factor for FB 1 and 2 sysParams.fbNco0 = [9500,9500] #Band0 for FB1 and FB2 ##### TX ##### sysParams.ducFactorTx = [24,24,24,24] #DUC interpolation factor for TX A, B, C and D sysParams.txNco0 = [[9500,9500], #Band0, Band1 for TXA [9500,9500], #Band0, Band1 for TXB [9500,9500], #Band0, Band1 for TXC [9500,9500]] #Band0, Band1 for TXD ############## JESD ############## ##### ADC-JESD ##### sysParams.jesdSystemMode= [1,1] #SystemMode 0: 2R1F-FDD ; rx1-rx2-fb -fb #SystemMode 1: 1R1F-FDD ; rx -rx -fb -fb #SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2 #SystemMode 3: 1R ; rx -rx -rx -rx #SystemMode 4: 1F ; fb -fb- fb -fb #SystemMode 5: 1R1F-TDD ; rx/fb-rx/fb-rx/fb-rx/fb sysParams.jesdTxProtocol= [0,0] # 0 - 8b/10b encoding; 2 - 64b/66b encoding sysParams.LMFSHdRx = ["24410","24410","24410","24410"] # The 2nd and 4th are valid only for jesdSystemMode values in (0,2). # For other modes, select 4 converter modes for 1st and 3rd. sysParams.LMFSHdFb = ["22210","22210"] sysParams.rxJesdTxScr = [True,True,True,True] sysParams.fbJesdTxScr = [True,True] sysParams.rxJesdTxK = [16,16,16,16] sysParams.fbJesdTxK = [16,16] sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location. # For example, if you want to exchange the first two lines of each 2T, # this should be [[1,0,2,3],[5,4,6,7]] ##### DAC-JESD ##### sysParams.jesdRxProtocol= [0,0] sysParams.LMFSHdTx = ["44210","44210","44210","44210"] sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location. # For example, if you want to exchange the first two lines of each 2R # this should be [[1,0,2,3],[5,4,6,7]] sysParams.jesdRxRbd = [4, 4] sysParams.jesdRxScr = [True,True,True,True] sysParams.jesdRxK = [16,16,16,16] ##### JESD Common ##### sysParams.jesdABLvdsSync= True sysParams.jesdCDLvdsSync= True sysParams.syncLoopBack = True #JESD Sync signal is connected to FPGA ############## GPIO ############## sysParams.gpioMapping = { 'H8': 'ADC_SYNC0', 'H7': 'ADC_SYNC1', 'N8': 'ADC_SYNC2', 'N7': 'ADC_SYNC3', 'H9': 'DAC_SYNC0', 'G9': 'DAC_SYNC1', 'N9': 'DAC_SYNC2', 'P9': 'DAC_SYNC3', 'P14': 'GLOBAL_PDN', 'K14': 'FBABTDD', 'R6': 'FBCDTDD', 'H15': ['TXATDD','TXBTDD'], 'V5': ['TXCTDD','TXDTDD'], 'E7': ['RXATDD','RXBTDD'], 'R15': ['RXCTDD','RXDTDD']} ############## LMK Params ############## lmkParams.pllEn = True lmkParams.inputClk = 983.04 # Valid only when lmkParams.pllEn = False lmkParams.lmkFrefClk = True setupParams.fpgaRefClk = 245.76 # Should be equal to LaneRate/40 for TSW14J56 ############## Logging ############## logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt") logDumpInst.logFormat=0x1 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute. logDumpInst.rewriteFile=1 logDumpInst.rewriteFileFormat4=1 device.optimizeWrites=0 device.rawWriteLogEn=1 device.delay_time = 0 #-------------------------------------------------------------------------------------------------# setupParams.skipLmk = False AFE.initializeConfig() lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq lmkParams.lmkPulseSysrefMode = False AFE.LMK.lmkConfig() ## Initiates AFE79xx Bring-up setupParams.skipLmk = True sysParams.txEnable = [False,False,False,False] AFE.deviceBringup() AFE.TOP.overrideTdd(15,3,15)
谢谢~
你好,奈文,
您看到的那个输入音调周围的裙板是由 AFE 时钟的相位噪声引起的。 如果你想摆脱裙板,那么将需要应用一个更干净的时钟。 为了获得最佳的相位噪声性能、应向 AFE 提供具有良好相位噪声性能的外部时钟。 有关针对外部时钟修改 EVM 的说明、请参阅 AFE79xx 安全文件夹中的外部时钟指南。
如果您想要使用当前时钟配置、但希望从测量 SNR 和 SFDR 中排除裙板、那么您可以使用以下设置在 HSDC pro 中的基音周围陷波。
此致、
大卫·查帕罗