您好!
我尝试使用 AFE7950EVM 板执行 JESD 环回。 我在端口 RXA 上有一个信号发生器、在端口 TXA 板上有一个频谱分析仪。 我将 NCO 频率设置为8900MHz、将信号发生器频率设置为8950MHz。
AFE 通过 Latte 工具进行编程、我可以按顺序执行以下 python 脚本:Setup.py、devInit.py 和经过少量修改的 S3_OnboardClk_RX_TX_500M_FB_disabled.py 版本。
我添加了命令 sysParams.serdesFirmware 和 sysParams.jesdLoopBackEn、并将这两个命令都设置为 true。
脚本在运行时不会出现错误、但我无法测量 AFE 的 TX 端口上的输出信号。 我还尝试了其他端口没有成功。
您能查看我的代码吗? 我缺少什么吗?
此致
斯特凡
############## Read me ############## #In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 491.52M #In HSDC Pro ADC tab, Select AFE79xx_2x2RX_44210; Data Rate = 491.52M ---> To capture 4 RX channels sysParams=AFE.systemParams sysParams.__init__();sysParams.chipVersion=chipVersion setupParams.skipFpga = False # setup FPGA (TSW14J56) using HSDC Pro ############## Top Level ############## sysParams.FRef = 491.52 sysParams.FadcRx = 2949.12 sysParams.FadcFb = 2949.12 sysParams.Fdac = 2949.12*4 sysParams.externalClockRx=False sysParams.externalClockTx=False ############## Digital Chain ############## ##### RX ##### sysParams.ddcFactorRx = [6,6,6,6] #DDC decimation factor for RX A, B, C and D sysParams.rxNco0 = [[8900,8900], #Band0, Band1 for RXA [8900,8900], #Band0, Band1 for RXB [8900,8900], #Band0, Band1 for RXC [8900,8900]] #Band0, Band1 for RXD ##### FB ##### sysParams.fbEnable = [False,False] sysParams.ddcFactorFb = [6,6] #DDC decimation factor for FB 1 and 2 sysParams.fbNco0 = [8900,8900] #Band0 for FB1 and FB2 ##### TX ##### sysParams.ducFactorTx = [24,24,24,24] #DUC interpolation factor for TX A, B, C and D sysParams.txNco0 = [[8900,8900], #Band0, Band1 for TXA [8900,8900], #Band0, Band1 for TXB [8900,8900], #Band0, Band1 for TXC [8900,8900]] #Band0, Band1 for TXD ############## JESD ############## ##### ADC-JESD ##### sysParams.jesdSystemMode= [3,3] #SystemMode 0: 2R1F-FDD ; rx1-rx2-fb -fb #SystemMode 1: 1R1F-FDD ; rx -rx -fb -fb #SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2 #SystemMode 3: 1R ; rx -rx -rx -rx #SystemMode 4: 1F ; fb -fb- fb -fb #SystemMode 5: 1R1F-TDD ; rx/fb-rx/fb-rx/fb-rx/fb sysParams.jesdTxProtocol= [0,0] # 0 - 8b/10b encoding; 2 - 64b/66b encoding sysParams.LMFSHdRx = ["44210","44210","44210","44210"] # The 2nd and 4th are valid only for jesdSystemMode values in (0,2). # For other modes, select 4 converter modes for 1st and 3rd. sysParams.LMFSHdFb = ["44210","44210"] sysParams.rxJesdTxScr = [True,True,True,True] sysParams.fbJesdTxScr = [True,True] sysParams.rxJesdTxK = [16,16,16,16] sysParams.fbJesdTxK = [16,16] #sysParams.jesdTxLaneMux = [5,6,4,7,3,2,0,1] sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location. # For example, if you want to exchange the first two lines of each 2T, # this should be [[1,0,2,3],[5,4,6,7]] ##### DAC-JESD ##### sysParams.jesdRxProtocol= [0,0] sysParams.LMFSHdTx = ["44210","44210","44210","44210"] #sysParams.jesdRxLaneMux = [5,6,4,7,3,2,1,0] sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location. # For example, if you want to exchange the first two lines of each 2R # this should be [[1,0,2,3],[5,4,6,7]] sysParams.jesdRxRbd = [4, 4] sysParams.jesdRxScr = [True,True,True,True] sysParams.jesdRxK = [16,16,16,16] ##### JESD Common ##### sysParams.jesdABLvdsSync= True sysParams.jesdCDLvdsSync= True sysParams.syncLoopBack = False #JESD Sync signal is connected to FPGA sysParams.serdesFirmware= True sysParams.jesdLoopBackEn= True #sysParams.serdesRxLanePolarity = [1,1,1,1,0,0,0,0] #sysParams.serdesTxLanePolarity = [1,1,0,0,1,1,0,0] ############## GPIO ############## sysParams.gpioMapping = { 'H8': 'ADC_SYNC0', 'H7': 'ADC_SYNC1', 'N8': 'ADC_SYNC2', 'N7': 'ADC_SYNC3', 'H9': 'DAC_SYNC0', 'G9': 'DAC_SYNC1', 'N9': 'DAC_SYNC2', 'P9': 'DAC_SYNC3', 'P14': 'GLOBAL_PDN', 'K14': 'FBABTDD', 'R6': 'FBCDTDD', 'H15': ['TXATDD','TXBTDD'], 'V5': ['TXCTDD','TXDTDD'], 'E7': ['RXATDD','RXBTDD'], 'R15': ['RXCTDD','RXDTDD']} ############## LMK Params ############## lmkParams.pllEn = True lmkParams.inputClk = 983.04 # Valid only when lmkParams.pllEn = False lmkParams.lmkFrefClk = True setupParams.fpgaRefClk = 245.76 # Should be equal to LaneRate/40 for TSW14J56 ############## Logging ############## logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt") logDumpInst.logFormat=0x0 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute. logDumpInst.rewriteFile=1 logDumpInst.rewriteFileFormat4=1 device.optimizeWrites=0 device.rawWriteLogEn=1 device.delay_time = 0 #-------------------------------------------------------------------------------------------------# AFE.deviceBringup() AFE.TOP.overrideTdd(15,3,15) # bit-wise; 4R,2F,4T