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我使用 ZCU102和7950EVM 测试了 AFE7950芯片的 DAC 输出。 运行 TI_IP_12Gbps_8 Lane_Config L.mk.py (从我的安全资源)脚本以观察 DAC 输出、TXA (5400M)电源可以达到-4dB、但另一个低于-20dB！我如何修改脚本参数配置？
另一个 问题是如何配置端口以输出超过10G 的信号？
期待回复！！！谢谢
嗨、查帕罗
感谢您的回复！
如果我只是更新 sysParams.txNco0、那么 DAC 输出的频率不是 txNco0 值！ 我更新 sysParams.txNco0、 sysParams。 Fdac、sysParams.ncoFreqMode 和 sysParams.ducFactorTx 来获取 所需的 txNco0频率。
现在、我有两个问题：
1) 四个通道的输出功率不同、 时，TXA 的功率 比 TXD 大20dB 以上。 如果我希望四通道的输出功率保持一致(达到 TXA 值)、应 更新哪个参数？
2) 2)运行您的演示(从 ZCU102_AFE79xx_64b66b_12Gbps)、TX 应以 NCO 频率+(491.52/64)=(NCO+7.68) MHz 输出单频。 但测得的输出频率 I 大约等于(NCO + 11.99) MHz。 原因是什么？ 或者哪个参数 配置不正确？
尊敬的 David：
1) 1)我将 TXA 和 TXB 通道配置为10GHz，测量的功率为-10dBm 和-16dBm (包括电缆损耗)；将 TXC 和 TXD 通道配置为10.2GHz，测量的功率为-20dBm 和-28dBm (包括电缆损耗)；
2）我尚未更改 ZCU102_AFE79xx_64b66b_12Gbps\bbitfiles 中使用的数据速率和 FPGA 文件 TI_204C_IP_Ref.bit 。
修改后的 phython 脚本如下所示：
'''
Validation : AFE79xx Library Version
v1.67, v1.74
Case RX TX FB CLK Notes
---- ----------------- ----------------- ----------------- ----------- ------------
1 245.76Msps, 24410 491.52Msps, 44210 491.52Msps, 22210 FADC=2949.12M DAC in interleaved mode
SerDes=9830.4Mbps SerDes=9830.4Mbps SerDes=9830.4Mbps FDAC=8847.36M
PLL0, NCO=3500M PLL0, NCO=3500M NCO=3500M REF=491.52M
2 245.76Msps, 24410 491.52Msps, 44210 491.52Msps, 22210 FADC=2949.12M DAC in straight mode
SerDes=9830.4Mbps SerDes=9830.4Mbps SerDes=9830.4Mbps FDAC=8847.36M
PLL0, NCO=3500M PLL0, NCO=3500M NCO=3500M REF=491.52M
'''
setupParams.skipFpga = 1
sysParams = AFE.systemParams
setupParams.fpgaRefClk = 184.32
AFE.systemStatus.loadTrims = 1
sysParams.fbEnable = [False]*2
sysParams.FRef = 491.52
sysParams.FadcRx = 2949.12
sysParams.FadcFb = 2949.12
sysParams.Fdac = 2949.12*4
sysParams.enableDacInterleavedMode = False #DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs
sysParams.modeTdd = 0
# 0- Single TDD Pin for all Channels
# 1- Separate Control for 2T/2R/1F
# 2- Separate Control for 1T/1R/1F
sysParams.topLevelSystemMode = 'StaticTDDMode'
sysParams.RRFMode = 0 #4T4R2F FDD mode
sysParams.jesdSystemMode = [3,3]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb-fb
#SystemMode 1: 1R1F-FDD ; rx1-rx1-fb-fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx1-rx1-rx1-rx1
#SystemMode 4: 1F ; fb-fb-fb-fb
#SystemMode 5: 1R1F-TDD ; rx1/fb-rx1/fb-rx1/fb-rx1/fb
#SystemMode 8: 1R1F-TDD 1R-FDD (FB-2Lanes)(RX1 RX2 interchanged) ; rx2/fb-rx2/fb-rx1-rx1
sysParams.jesdLoopbackEn = 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
sysParams.LMFSHdRx =['44210', '44210', '44210', '44210']
# The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["22210","22210"]
sysParams.LMFSHdTx = ["44210","44210","44210","44210"]
sysParams.jesdTxProtocol = [2,2] #64b/66b
sysParams.jesdRxProtocol = [2,2] #64b/66b
sysParams.serdesFirmware = True # If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7]
# Enter which lanes you want in each location.
# Note that across 2T Mux is not possible in 0.5.
# For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7]
# Enter which lanes you want in each location.
# Note that across 2R Mux is not possible in 0.5.
# For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd = [4, 4]
# scrambler is disabled
sysParams.rxJesdTxScr = [False]*4
sysParams.fbJesdTxScr = [False]*2
sysParams.jesdRxScr = [False]*4
sysParams.rxJesdTxK = [1,1,1,1]
sysParams.fbJesdTxK = [1,1]
sysParams.jesdRxK = [1,1,1,1]
#sysParams.ncoFreqMode = "1KHz"
sysParams.ncoFreqMode = "FCW"
sysParams.txNco0 = [[10000,10000], #Band0, Band1 for TxA for NCO0
[10000,10000], #Band0, Band1 for TxB for NCO0
[10200,10200], #Band0, Band1 for TxC for NCO0
[10200,10200]] #Band0, Band1 for TxD for NCO0
sysParams.rxNco0 = [[10000,10000], #Band0, Band1 for RxA for NCO0
[10000,10000], #Band0, Band1 for RxB for NCO0
[10200,10200], #Band0, Band1 for RxC for NCO0
[10200,10200]] #Band0, Band1 for RxD for NCO0
sysParams.fbNco0 = [9500,9500] #FBA, FBC for NCO0
sysParams.numBandsRx = [0]*4 # 0 for single, 1 for dual
sysParams.numBandsFb = [0,0]
sysParams.numBandsTx = [0,0,0,0]
sysParams.ddcFactorRx = [4]*4 # DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorFb = [4]*2
#sysParams.ducFactorTx = [12]*4
sysParams.ducFactorTx = [16]*4
AFE.systemStatus.loadTrims =1
## The following parameters sets up the LMK04828 clocking schemes
lmkParams.pllEn = True#False
lmkParams.inputClk = 1474.56#737.28
lmkParams.lmkFrefClk = True
## The following parameters sets up the register and macro dumps
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat = 0x00
logDumpInst.rewriteFile = 1
logDumpInst.rewriteFileFormat4 = 1
device.optimizeWrites = 0
device.rawWriteLogEn = 1
## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync = 1
sysParams.jesdCDLvdsSync = 1
sysParams.rxJesdTxSyncMux = [0,0,0,0]
sysParams.fbJesdTxSyncMux = [0,0]
sysParams.jesdRxSyncMux = [0,0,0,0] #[0,0,1,1]
sysParams.syncLoopBack = True
# ## The following parameters sets up the AGC
# sysParams.agcParams[0].agcMode = 1 ##internal AGC
# sysParams.agcParams[0].gpioRstEnable = 0 ##disable GPIO based reset to AGC detector
# sysParams.agcParams[0].atken = [0, 1, 0] ##enable big and small step attack
# sysParams.agcParams[0].decayen = [0,1,0] ##enable big and small step decay
# sysParams.agcParams[0].atksize = [2,1,0] ## bigs step = 2dB, small step = 1dB
# sysParams.agcParams[0].decaysize = [2,1,0] ##big step = 2dB, small step = 1dB
# sysParams.agcParams[0].atkthreshold = [-1, -2, -14] ##attack threshold
# sysParams.agcParams[0].decaythreshold = [-14, -6, -20] ##decay threshold
# sysParams.agcParams[0].atkwinlength = [170, 170] ## detector time constant expressed inn absolute time in ns.
# sysParams.agcParams[0].decaywinlength = 87380 ##detector time constant expressed in absolute time in ns. All detectors use the same value for decay time constant
# sysParams.agcParams[0].atkNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].decayNumHitsAbs = [100,100] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].minDsaAttn = 0 ##minimum DSA attenuation used by AGC
# sysParams.agcParams[0].maxDsaAttn = 22 ##maximum DSA attenuation used by AGC
# sysParams.agcParams[0].totalGainRange = 22 ##total gain range used by ALC for gain compensation
# sysParams.agcParams[0].minAttnAlc = 0 ##minimum attenuation used by ALC for compensation when useMinAttnAgc = 0
# sysParams.agcParams[0].useMinAttnAgc = 1 ##enable ALC to use minimum attenuation from AGC for which compensation is required.
# sysParams.agcParams[0].alcEn = 1
# sysParams.agcParams[0].alcMode = 0 ##floating point DGC
# sysParams.agcParams[0].fltPtMode = 0 ##if exponent > 0, dont send MSB
# sysParams.agcParams[0].fltPtFmt = 1 ##3 bit exponent
## The following parameters sets up the GPIOs
sysParams.gpioMapping={
'H8': 'ADC_SYNC0',
'H7': 'ADC_SYNC1',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'DAC_SYNC0',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
#AFE.systemParams.papParams[0]['enable'] = True
#AFE.systemParams.papParams[1]['enable'] = True
#AFE.systemParams.papParams[2]['enable'] = True
#AFE.systemParams.papParams[3]['enable'] = True
## Initiates LMK04828 and AFE79xx Bring-up
setupParams.skipLmk = False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
AFE.LMK.lmkConfig()你好 Xiao,
检查 RTL 后、您发现幅度差异很大的原因可能是 FPGA 发送到 DAC 的音调。 似乎发送到每个通道的音调具有不同的振幅。 如果您希望向每个 DAC 发送相同的音调、则应对"refdesign_TX.SV"进行以下更改、然后应重新生成位流。
assign tx_lane_data[0][63 -: 16] = sine_i[0][63 - sine_count*4]; assign tx_lane_data[0][47 -: 16] = sine_i[0][62 - sine_count*4]; assign tx_lane_data[0][31 -: 16] = sine_i[0][61 - sine_count*4]; assign tx_lane_data[0][15 -: 16] = sine_i[0][60 - sine_count*4]; assign tx_lane_data[1][63 -: 16] = sine_q[0][63 - sine_count*4]; assign tx_lane_data[1][47 -: 16] = sine_q[0][62 - sine_count*4]; assign tx_lane_data[1][31 -: 16] = sine_q[0][61 - sine_count*4]; assign tx_lane_data[1][15 -: 16] = sine_q[0][60 - sine_count*4]; assign tx_lane_data[2][63 -: 16] = sine_i[0][63 - sine_count*4]; assign tx_lane_data[2][47 -: 16] = sine_i[0][62 - sine_count*4]; assign tx_lane_data[2][31 -: 16] = sine_i[0][61 - sine_count*4]; assign tx_lane_data[2][15 -: 16] = sine_i[0][60 - sine_count*4]; assign tx_lane_data[3][63 -: 16] = sine_q[0][63 - sine_count*4]; assign tx_lane_data[3][47 -: 16] = sine_q[0][62 - sine_count*4]; assign tx_lane_data[3][31 -: 16] = sine_q[0][61 - sine_count*4]; assign tx_lane_data[3][15 -: 16] = sine_q[0][60 - sine_count*4]; assign tx_lane_data[4][63 -: 16] = sine_i[0][63 - sine_count*4]; assign tx_lane_data[4][47 -: 16] = sine_i[0][62 - sine_count*4]; assign tx_lane_data[4][31 -: 16] = sine_i[0][61 - sine_count*4]; assign tx_lane_data[4][15 -: 16] = sine_i[0][60 - sine_count*4]; assign tx_lane_data[5][63 -: 16] = sine_q[0][63 - sine_count*4]; assign tx_lane_data[5][47 -: 16] = sine_q[0][62 - sine_count*4]; assign tx_lane_data[5][31 -: 16] = sine_q[0][61 - sine_count*4]; assign tx_lane_data[5][15 -: 16] = sine_q[0][60 - sine_count*4]; assign tx_lane_data[6][63 -: 16] = sine_i[0][63 - sine_count*4]; assign tx_lane_data[6][47 -: 16] = sine_i[0][62 - sine_count*4]; assign tx_lane_data[6][31 -: 16] = sine_i[0][61 - sine_count*4]; assign tx_lane_data[6][15 -: 16] = sine_i[0][60 - sine_count*4]; assign tx_lane_data[7][63 -: 16] = sine_q[0][63 - sine_count*4]; assign tx_lane_data[7][47 -: 16] = sine_q[0][62 - sine_count*4]; assign tx_lane_data[7][31 -: 16] = sine_q[0][61 - sine_count*4]; assign tx_lane_data[7][15 -: 16] = sine_q[0][60 - sine_count*4];
此致、
大卫·查帕罗