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/*!
* @brief Sensor inter-chirp (during chirp idle time) dynamic power save disable override
* mode. \n This field provides various RX and TX chain dynamic rapid power save disable
* option in inter-chirp idle time.
* | Value | Definition |
* |-------|----------- |
* | 0 | Dynamic Power Save Enable (default)|
* | 1 | Dynamic Power Save Disable |
* Bit field definition: \n
* | Bit Field | Definition |
* |-------|----------- |
* | Bit 0 | TX PA POWERSAVE_DISABLE control |
* | Bit 1 | TX LO POWERSAVE_DISABLE control |
* | Bit 2 | RX RF POWERSAVE_DISABLE control |
* | Bit 3 | RX BB POWERSAVE_DISABLE control |
* | Bit 4 | RX LO POWERSAVE_DISABLE control |
* | Bits [7:5] | Reserved |
* By default these power save modes are enabled in FECSS. \n
* Recommended settings:
* | Chirp Idle Time | INTER_CHIRP_PS_DIS |
* |-----------------| ------------------ |
* | > max of (6us - tx start time, 3.1us) | 0x00 (Power save Enabled) |
* | > max of (4us - tx start time, 3.1us) and <= max of (6us - tx start time, 3.1us) | 0x1F (Power save Disabled) |
* | < max of (4us - tx start time, 3.1us) | Not Supported idle time |
* Note: The minimum idle time can not go lower than max of (4us - tx start time, 3.1us).
*
*/
UINT8 c_InterChirpPsDis;
