[参考译文] CC1310：伪同步事件

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Other Parts Discussed in Thread: CC1310

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https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/1269582/cc1310-false-sync-events

器件型号：CC1310

您好！

我使用的是高速( 1.5 CC1310上的 Mbps 4-FSK)数据包结构： RFC_CMD_HS_RX_s 和 RFC_CMD_HS_TX_s 。

现在出现的情况是、我的接收对讲机偶尔报告同步字检测、而另一个对讲机没有发射、并且一段时间(例如~10ms)( 请参阅随附的图像。 请注意、显示的信号直接来自射频内核、由 TI 通过覆盖项进行配置：

/* RF Core monitors */
    (uint32_t)0x008F88B3, // For RAT_GPO1
    //                           MOD (MCE_GPO0) to RFC_GPO0           DEMOD (MCE_GPO1) to RFC_GPO1         TX (RAT_GPO0) to RFC_GPO2                RX (RAT_GPO1) to RFC_GPO3
    HW_REG_OVERRIDE(0x1110, RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 | RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 | RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 | RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1),

)。

我没有实现地址滤波、因此我有一个 TI 已定义但无法更改的32位同步字。因此、我预计平均每2^32 / 1.5 x 10^6次出现伪同步指示= 2863秒 (根据传输占空比进行调整、因此这是一个非常保守的估算值)。在现实中,这一事件发生在一分钟内开始一个传输/接收序列,占空比约为1:2 (传输:噪音)。

我可以启用地址过滤、这大概可以解决这个问题、但 a)当我尝试时、这导致了其他问题(我将在另一个线程中讨论)和 b)由于我不希望经常看到同步字检测这种情况、我显然不明白稍后可能变得很重要的东西(我宁愿理解当前问题而不是简单地解决它)。

HS RX 命令的模板结构：

rfc_CMD_HS_RX_t RF_cmdRxHS =
{
    .commandNo = CMD_HS_RX,
    .status = 0x0000,
    .pNextOp = 0x00000000,
    .startTime = 0x00000000,
    .startTrigger.triggerType = 0x0,
    .startTrigger.bEnaCmd = 0x0,
    .startTrigger.triggerNo = 0x0,
    .startTrigger.pastTrig = 0x0,
    .condition.rule = 0x1,
    .condition.nSkip = 0x0,
    .pktConf.bFsOff = 0,
    .pktConf.bUseCrc = 0,
    .pktConf.bVarLen = 0,
    .pktConf.bRepeatOk = 0,
    .pktConf.bRepeatNok = 0,
    .pktConf.addressMode = 0,
    .rxConf.bAutoFlushCrcErr = 0,
    .rxConf.bIncludeLen = 0,
    .rxConf.bIncludeCrc = 0,
    .rxConf.bAppendStatus = 0,
    .rxConf.bAppendTimestamp = 0,
    .maxPktLen = 0,
    .address0 = 0,
    .address1 = 0,
    .__dummy0 = 0,
    .endTrigger.triggerType = 1,
    .endTrigger.bEnaCmd = 0,
    .endTrigger.triggerNo = 0,
    .endTrigger.pastTrig = 0,
    .endTime = 0,
    .pQueue = 0,
    .pOutput = 0,    
};

PHY 贴片：

// TI-RTOS RF Mode Object (includes patches for high speed operation)
// e2e.ti.com/.../2363574
static const RF_Mode RfSettings_RF_prop_hs_4fsk =
{
    .rfMode       =  RF_MODE_PROPRIETARY_SUB_1,
    .cpePatchFxn  =  &rf_patch_cpe_ghs,
    .mcePatchFxn  =  &rf_patch_mce_ghs,
    .rfePatchFxn  =  &rf_patch_rfe_ghs,
};

PHY 基本设置：

// 1.5Mbps

// See SVS's post here for these trusted, official settings:
// e2e.ti.com/.../2363574
const rfc_CMD_PROP_RADIO_DIV_SETUP_t Cc1310_Rf900vol_PHY_900M_750KSYM_4fsk_g =
{
    // Use Smart RF Studio to generate rxBw, rateWord, deviation and preScale. 
    // Refer to RD1155 Rev 1.1 Section 3.2.4.2

    .commandNo = 0x3807,
    .status = 0x0000,
    .pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
    .startTime = 0x00000000,
    .startTrigger.triggerType = 0x0,
    .startTrigger.bEnaCmd = 0x0,
    .startTrigger.triggerNo = 0x0,
    .startTrigger.pastTrig = 0x0,
    .condition.rule = 0x1,
    .condition.nSkip = 0x0,
    .modulation.modType = 0x1,
    .modulation.deviation = 600,
    .symbolRate.preScale = 8,
    .symbolRate.rateWord = 262144,
    .rxBw = 0x30,
    .preamConf.nPreamBytes = 0x6,
    .preamConf.preamMode = 0x1,
    .formatConf.nSwBits = 0x20,
    .formatConf.bBitReversal = 0x0,
    .formatConf.bMsbFirst = 0x1,
    .formatConf.fecMode = 9,
    .formatConf.whitenMode = 0x0,
    .config.frontEndMode = 0x0,
    .config.biasMode = 0x1,
    .config.frontEndMode = 0x02, // Single-ended Mode RFN.
    .config.bNoFsPowerUp = 0x0,
    .txPower = 0x23F,
    .pRegOverride = (uint32_t*)PHY_900M_4_fsk_pOverrides,
    .centerFreq = 915,
    .intFreq = 0x0A66,
    .loDivider = 0x05,
};

PHY 覆盖：

static const uint32_t PHY_900M_4_fsk_pOverrides[] =
{
    // PHY: Use MCE RAM patch, RFE RAM patch 
    MCE_RFE_OVERRIDE(1, 0, 0, 1, 0, 0),
    // Rx: Set anti-aliasing filter bandwidth to Maximum
    ADI_HALFREG_OVERRIDE(0,61,0xF,0x0),
    // Synth: Set recommended RTRIM to 7
    HW_REG_OVERRIDE(0x4038,0x0037),
    // Synth: Configure fine calibration setting
    HW_REG_OVERRIDE(0x4020,0x7F00),
    // Synth: Configure fine calibration setting
    HW_REG_OVERRIDE(0x4064,0x0040),
    // Synth: Set Fref to 4 MHz
    (uint32_t)0x000684A3,
    // Synth: Configure fine calibration setting
    (uint32_t)0xC0040141,             
    (uint32_t)0x0533B107, 
    // Synth: Set loop bandwidth after lock
    (uint32_t)0xA480583,              
    (uint32_t)0x7AB80603,
    // Synth: Configure VCO LDO (in ADI1, set VCOLDOCFG=0x9F to use voltage input reference)
    ADI_REG_OVERRIDE(1,4,0x9F),
    // Synth: Configure synth LDO (in ADI1, set SLDOCTL0.COMP_CAP=1)
    ADI_HALFREG_OVERRIDE(1,7,0x4,0x4),
    // Rx: Set LNA bias current trim offset to 3
    (uint32_t)0x00038883,
    // Rx: Set RSSI offset to adjust reported RSSI
    (uint32_t)0x00FB88A3,             
    // Synth: Use 24 MHz XOSC as synth clock, enable extra PLL filtering
    (uint32_t)0x02010403,
    // Synth: Configure extra PLL filtering
    (uint32_t)0x00108463,
    // Synth: Increase synth programming timeout (0x04B0 RAT ticks = 300 us)
    (uint32_t)0x04B00243,
    /* #### scc: See software-dl.ti.com/.../packet-format.html
     * for a discussion of Sync Words.
     */
    //Configure threshold for Sync word detection
    HW_REG_OVERRIDE(0x5104,0x302B),
    //Set FIFO threshold
    (uint32_t) 0x002C82C3,            
    (uint32_t) 0x002882D3,
    // Rx: Do not freeze RSSI on sync found event
    HW_REG_OVERRIDE(0x6084,0x25F1),
    // ****PA Ramping overrides
    HW_REG_OVERRIDE(0x6088,0x4121),    
    HW_REG_OVERRIDE(0x608C,0x0A12), 
    // ****Length of CW tone
    HW_REG_OVERRIDE(0x52B0,0x00F0),    
    // DC estimation
    HW_REG_OVERRIDE(0x51F8,0x0F90),
    //Zero IF in TX
    (uint32_t) 0x00000343, 
    // Tx: Set PA trim to max (in ADI0, set PACTL0=0xF8)
    ADI_REG_OVERRIDE(0,12,0xF8),

    // Single-ended Operation
    ADI_HALFREG_OVERRIDE(0, 16, 0x7, 1), // Output on RFP
    
    /* RF Core monitors */
    (uint32_t)0x008F88B3, // For RAT_GPO1
    //                           MOD (MCE_GPO0) to RFC_GPO0           DEMOD (MCE_GPO1) to RFC_GPO1         TX (RAT_GPO0) to RFC_GPO2                RX (RAT_GPO1) to RFC_GPO3
    HW_REG_OVERRIDE(0x1110, RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 | RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 | RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 | RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1),
    
    // End Override
    (uint32_t)0xFFFFFFFF,              
};

在发布接收命令之前进行的修改：

if(Cc1310_RfSettings_IsHighSpeedMode() || Cc1310_RfSettings_Is4fskMode()) // High Speed mode
    {                    
        /* Configure high speed TX command */
        RF_cmdRxHS.pQueue = &RxQueue;

         // CRC not applicable, since we are using infinite length transmission mode there is no
         // * automatic CRC checking for us                     
        RF_cmdRxHS.pktConf.bUseCrc = 0;
        // According to software-dl.ti.com/.../structrfc___c_m_d___h_s___r_x__s.html,
        // CC1310 must be considering the packet of VARIABLE length
        RF_cmdRxHS.maxPktLen = 16;
        RF_cmdRxHS.startTrigger.triggerType = TRIG_NOW;
        RF_cmdRxHS.startTrigger.pastTrig = 1;
        RF_cmdRxHS.startTime = 0;
        RF_cmdRxHS.pOutput = &RxStatsHs;

        // RF_cmdRxHS.rxConf.bAppendStatus = 1;

        RxOperation = (RF_Op*)&RF_cmdRxHS;
    }
    else // Standard speed
    {

射频队列设置：

static void SetupBlockQueue(uint8_t numBlocks, boolean_t highSpeed)
{
    rfc_dataEntryPointer_t* pointerDataEntryPtr;    

    /* Although the RF core will only receive into a single entry and will 
     * not automatically move onto the next data entry, RxQueue and Data Entry Queue 
     * are still apparently necessary to get the RF Core working. 
     */
    RxQueue.pCurrEntry = RxEntryQueue; // Current entry is the first in the queue
    RxQueue.pLastEntry = RxQueue.pCurrEntry;    
    RxEntryCurrent = (rfc_dataEntryPointer_t*)(RxQueue.pCurrEntry);

    // Configuration of generic data entry header    
    pointerDataEntryPtr = (rfc_dataEntryPointer_t*)RxEntryQueue;  // Re-interpretation of simple byte array
    pointerDataEntryPtr->status = DATA_ENTRY_PENDING;
    pointerDataEntryPtr->config.type = DATA_ENTRY_TYPE_PTR;
    // Make the entry exactly the same size as an SPI transaction, thereby forcing the IRQ_RX_ENTRY_DONE interrupt.
    pointerDataEntryPtr->length = 16;

    // This will return a pointer to either the General Buffer or a Pipeline entry/vacancy.
    pointerDataEntryPtr->pData = Cc1310_BbBlocks_GetBufferWrPtr(pointerDataEntryPtr->length, CC1310_BBBLOCKS_REGULAR, CCRF_MODE_RX_BLOCKS);

    // Data entry queue is pointless for DATA_ENTRY_TYPE_PTR since pipelining of Rx is not possible for any entry type besides _PARTIAL_
    pointerDataEntryPtr->pNextEntry = NULL;         
}

接收命令：

 RxHandle = RF_postCmd(
        Cc1310_CcRf_RfHandle_g,
        RxOperation,
        RF_PriorityNormal,
        &RxBlocksCallback,
        RF_EventRxEntryDone
    );

当 RxBlocksCallback ()被执行时,我看到 IRQ_RX_ENTRY_DONE 和 IRQ_LAST_COMMAND_DONE 真正的接收时所做的那样。另外、我进行了一些调试、输出 RxEntryCurrent -> length、指示16个字节、根据我的要求-没有明显的迹象表明出现了任何问题。

我注意到、 https://software-dl.ti.com/simplelink/esd/simplelink_cc13x0_sdk/4.10.02.04/exports/docs/proprietary-rf/proprietary-rf-users-guide/proprietary-rf/packet-format.html 讨论了同步字阈值、这也讨论了设置两个相关器阈值的覆盖、但它没有指示 YY 和 ZZ 值的上限和下限以及它们实际对应的值：